ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16     EXPORT  ArmInvalidateInstructionCache
  17     EXPORT  ArmInvalidateDataCacheEntryByMVA
  18     EXPORT  ArmCleanDataCacheEntryByMVA
  19     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  20     EXPORT  ArmInvalidateDataCacheEntryBySetWay
  21     EXPORT  ArmCleanDataCacheEntryBySetWay
  22     EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
  23     EXPORT  ArmDrainWriteBuffer
  24     EXPORT  ArmEnableMmu
  25     EXPORT  ArmDisableMmu
  26     EXPORT  ArmDisableCachesAndMmu
  27     EXPORT  ArmMmuEnabled
  28     EXPORT  ArmEnableDataCache
  29     EXPORT  ArmDisableDataCache
  30     EXPORT  ArmEnableInstructionCache
  31     EXPORT  ArmDisableInstructionCache
  32     EXPORT  ArmEnableSWPInstruction
  33     EXPORT  ArmEnableBranchPrediction
  34     EXPORT  ArmDisableBranchPrediction
  35     EXPORT  ArmSetLowVectors
  36     EXPORT  ArmSetHighVectors
  37     EXPORT  ArmV7AllDataCachesOperation
  38     EXPORT  ArmDataMemoryBarrier
  39     EXPORT  ArmDataSyncronizationBarrier
  40     EXPORT  ArmInstructionSynchronizationBarrier
  41     EXPORT  ArmWriteVBar
  42     EXPORT  ArmEnableVFP
  43     EXPORT  ArmCallWFI
  44     EXPORT  ArmReadCbar
  45     EXPORT  ArmInvalidateInstructionAndDataTlb
  46     EXPORT  ArmReadMpidr
  47     EXPORT  ArmReadTpidrurw
  48     EXPORT  ArmWriteTpidrurw
  49     EXPORT  ArmIsArchTimerImplemented
  50     EXPORT  ArmReadIdPfr1
  51
  52     AREA    ArmV7Support, CODE, READONLY
  53     PRESERVE8
  54
  55 DC_ON           EQU     ( 0x1:SHL:2 )
  56 IC_ON           EQU     ( 0x1:SHL:12 )
  57 CTRL_M_BIT      EQU     (1 << 0)
  58 CTRL_C_BIT      EQU     (1 << 2)
  59 CTRL_B_BIT      EQU     (1 << 7)
  60 CTRL_I_BIT      EQU     (1 << 12)
  61
  62
  63 ArmInvalidateDataCacheEntryByMVA
  64   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  65   dsb
  66   isb
  67   bx      lr
  68
  69 ArmCleanDataCacheEntryByMVA
  70   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  71   dsb
  72   isb
  73   bx      lr
  74
  75
  76 ArmCleanInvalidateDataCacheEntryByMVA
  77   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  78   dsb
  79   isb
  80   bx      lr
  81
  82
  83 ArmInvalidateDataCacheEntryBySetWay
  84   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  85   dsb
  86   isb
  87   bx      lr
  88
  89
  90 ArmCleanInvalidateDataCacheEntryBySetWay
  91   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  92   dsb
  93   isb
  94   bx      lr
  95
  96
  97 ArmCleanDataCacheEntryBySetWay
  98   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
  99   dsb
 100   isb
 101   bx      lr
 102
 103
 104 ArmInvalidateInstructionCache
 105   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
 106   isb
 107   bx      LR
 108
 109 ArmEnableMmu
 110   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 111   orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
 112   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 113   dsb
 114   isb
 115   bx      LR
 116
 117 ArmDisableMmu
 118   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 119   bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
 120   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 121
 122   mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
 123   mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
 124   dsb
 125   isb
 126   bx      LR
 127
 128 ArmDisableCachesAndMmu
 129   mrc   p15, 0, r0, c1, c0, 0           ; Get control register
 130   bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
 131   bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
 132   bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
 133   mcr   p15, 0, r0, c1, c0, 0           ; Write control register
 134   dsb
 135   isb
 136   bx      LR
 137
 138 ArmMmuEnabled
 139   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 140   and     R0,R0,#1
 141   bx      LR
 142
 143 ArmEnableDataCache
 144   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 145   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 146   orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
 147   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 148   dsb
 149   isb
 150   bx      LR
 151
 152 ArmDisableDataCache
 153   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 154   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 155   bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
 156   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 157   dsb
 158   isb
 159   bx      LR
 160
 161 ArmEnableInstructionCache
 162   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 163   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 164   orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
 165   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 166   dsb
 167   isb
 168   bx      LR
 169
 170 ArmDisableInstructionCache
 171   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 172   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 173   BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
 174   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 175   isb
 176   bx      LR
 177
 178 ArmEnableSWPInstruction
 179   mrc     p15, 0, r0, c1, c0, 0
 180   orr     r0, r0, #0x00000400
 181   mcr     p15, 0, r0, c1, c0, 0
 182   isb
 183   bx      LR
 184
 185 ArmEnableBranchPrediction
 186   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 187   orr     r0, r0, #0x00000800   ;
 188   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 189   dsb
 190   isb
 191   bx      LR
 192
 193 ArmDisableBranchPrediction
 194   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 195   bic     r0, r0, #0x00000800   ;
 196   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 197   dsb
 198   isb
 199   bx      LR
 200
 201 ArmSetLowVectors
 202   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 203   bic     r0, r0, #0x00002000   ; clear V bit
 204   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 205   isb
 206   bx      LR
 207
 208 ArmSetHighVectors
 209   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 210   orr     r0, r0, #0x00002000   ; clear V bit
 211   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 212   isb
 213   bx      LR
 214
 215 ArmV7AllDataCachesOperation
 216   stmfd SP!,{r4-r12, LR}
 217   mov   R1, R0                ; Save Function call in R1
 218   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 219   ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 220   mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 221   beq   Finished
 222   mov   R10, #0
 223
 224 Loop1
 225   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 226   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 227   and   R12, R12, #7            ; get those 3 bits alone
 228   cmp   R12, #2
 229   blt   Skip                    ; no cache or only instruction cache at this level
 230   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 231   isb                           ; isb to sync the change to the CacheSizeID reg
 232   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 233   and   R2, R12, #&7            ; extract the line length field
 234   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 235   ldr   R4, =0x3FF
 236   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 237   clz   R5, R4                  ; R5 is the bit position of the way size increment
 238   ldr   R7, =0x00007FFF
 239   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 240
 241 Loop2
 242   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 243
 244 Loop3
 245   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 246   orr   R0, R0, R7, LSL R2      ; factor in the index number
 247
 248   blx   R1
 249
 250   subs  R9, R9, #1              ; decrement the way number
 251   bge   Loop3
 252   subs  R7, R7, #1              ; decrement the index
 253   bge   Loop2
 254 Skip
 255   add   R10, R10, #2            ; increment the cache number
 256   cmp   R3, R10
 257   bgt   Loop1
 258
 259 Finished
 260   dsb
 261   ldmfd SP!, {r4-r12, lr}
 262   bx    LR
 263
 264 ArmDataMemoryBarrier
 265   dmb
 266   bx      LR
 267
 268 ArmDataSyncronizationBarrier
 269 ArmDrainWriteBuffer
 270   dsb
 271   bx      LR
 272
 273 ArmInstructionSynchronizationBarrier
 274   isb
 275   bx      LR
 276
 277 ArmWriteVBar
 278   // Set the Address of the Vector Table in the VBAR register
 279   mcr     p15, 0, r0, c12, c0, 0
 280   // Ensure the SCTLR.V bit is clear
 281   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 282   bic     r0, r0, #0x00002000   ; clear V bit
 283   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 284   isb
 285   bx      lr
 286
 287 ArmEnableVFP
 288   // Read CPACR (Coprocessor Access Control Register)
 289   mrc     p15, 0, r0, c1, c0, 2
 290   // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 291   orr     r0, r0, #0x00f00000
 292   // Write back CPACR (Coprocessor Access Control Register)
 293   mcr     p15, 0, r0, c1, c0, 2
 294   // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 295   mov     r0, #0x40000000
 296   mcr     p10,#0x7,r0,c8,c0,#0
 297   bx      lr
 298
 299 ArmCallWFI
 300   wfi
 301   bx      lr
 302
 303 //Note: Return 0 in Uniprocessor implementation
 304 ArmReadCbar
 305   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
 306   bx      lr
 307
 308 ArmInvalidateInstructionAndDataTlb
 309   mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB
 310   dsb
 311   bx lr
 312
 313 ArmReadMpidr
 314   mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR
 315   bx      lr
 316
 317 ArmReadTpidrurw
 318   mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW
 319   bx      lr
 320
 321 ArmWriteTpidrurw
 322   mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW
 323   bx      lr
 324
 325 ArmIsArchTimerImplemented
 326   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1
 327   and    r0, r0, #0x000F0000
 328   bx     lr
 329
 330 ArmReadIdPfr1
 331   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register
 332   bx     lr
 333
 334  END