ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16     EXPORT  ArmInvalidateInstructionCache
  17     EXPORT  ArmInvalidateDataCacheEntryByMVA
  18     EXPORT  ArmCleanDataCacheEntryByMVA
  19     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  20     EXPORT  ArmInvalidateDataCacheEntryBySetWay
  21     EXPORT  ArmCleanDataCacheEntryBySetWay
  22     EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
  23     EXPORT  ArmDrainWriteBuffer
  24     EXPORT  ArmEnableMmu
  25     EXPORT  ArmDisableMmu
  26     EXPORT  ArmDisableCachesAndMmu
  27     EXPORT  ArmMmuEnabled
  28     EXPORT  ArmEnableDataCache
  29     EXPORT  ArmDisableDataCache
  30     EXPORT  ArmEnableInstructionCache
  31     EXPORT  ArmDisableInstructionCache
  32     EXPORT  ArmEnableSWPInstruction
  33     EXPORT  ArmEnableBranchPrediction
  34     EXPORT  ArmDisableBranchPrediction
  35     EXPORT  ArmSetLowVectors
  36     EXPORT  ArmSetHighVectors
  37     EXPORT  ArmV7AllDataCachesOperation
  38     EXPORT  ArmDataMemoryBarrier
  39     EXPORT  ArmDataSynchronizationBarrier
  40     EXPORT  ArmInstructionSynchronizationBarrier
  41     EXPORT  ArmReadVBar
  42     EXPORT  ArmWriteVBar
  43     EXPORT  ArmEnableVFP
  44     EXPORT  ArmCallWFI
  45     EXPORT  ArmReadCbar
  46     EXPORT  ArmReadMpidr
  47     EXPORT  ArmReadTpidrurw
  48     EXPORT  ArmWriteTpidrurw
  49     EXPORT  ArmIsArchTimerImplemented
  50     EXPORT  ArmReadIdPfr1
  51
  52     AREA    ArmV7Support, CODE, READONLY
  53     PRESERVE8
  54
  55 DC_ON           EQU     ( 0x1:SHL:2 )
  56 IC_ON           EQU     ( 0x1:SHL:12 )
  57 CTRL_M_BIT      EQU     (1 << 0)
  58 CTRL_C_BIT      EQU     (1 << 2)
  59 CTRL_B_BIT      EQU     (1 << 7)
  60 CTRL_I_BIT      EQU     (1 << 12)
  61
  62
  63 ArmInvalidateDataCacheEntryByMVA
  64   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  65   bx      lr
  66
  67 ArmCleanDataCacheEntryByMVA
  68   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  69   bx      lr
  70
  71
  72 ArmCleanInvalidateDataCacheEntryByMVA
  73   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  74   bx      lr
  75
  76
  77 ArmInvalidateDataCacheEntryBySetWay
  78   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  79   bx      lr
  80
  81
  82 ArmCleanInvalidateDataCacheEntryBySetWay
  83   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  84   bx      lr
  85
  86
  87 ArmCleanDataCacheEntryBySetWay
  88   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
  89   bx      lr
  90
  91
  92 ArmInvalidateInstructionCache
  93   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  94   isb
  95   bx      LR
  96
  97 ArmEnableMmu
  98   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  99   orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
 100   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 101   dsb
 102   isb
 103   bx      LR
 104
 105 ArmDisableMmu
 106   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 107   bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
 108   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 109
 110   mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
 111   mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
 112   dsb
 113   isb
 114   bx      LR
 115
 116 ArmDisableCachesAndMmu
 117   mrc   p15, 0, r0, c1, c0, 0           ; Get control register
 118   bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
 119   bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
 120   bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
 121   mcr   p15, 0, r0, c1, c0, 0           ; Write control register
 122   dsb
 123   isb
 124   bx      LR
 125
 126 ArmMmuEnabled
 127   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 128   and     R0,R0,#1
 129   bx      LR
 130
 131 ArmEnableDataCache
 132   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 133   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 134   orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
 135   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 136   dsb
 137   isb
 138   bx      LR
 139
 140 ArmDisableDataCache
 141   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 142   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 143   bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
 144   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 145   dsb
 146   isb
 147   bx      LR
 148
 149 ArmEnableInstructionCache
 150   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 151   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 152   orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
 153   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 154   dsb
 155   isb
 156   bx      LR
 157
 158 ArmDisableInstructionCache
 159   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 160   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 161   BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
 162   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 163   isb
 164   bx      LR
 165
 166 ArmEnableSWPInstruction
 167   mrc     p15, 0, r0, c1, c0, 0
 168   orr     r0, r0, #0x00000400
 169   mcr     p15, 0, r0, c1, c0, 0
 170   isb
 171   bx      LR
 172
 173 ArmEnableBranchPrediction
 174   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 175   orr     r0, r0, #0x00000800   ;
 176   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 177   dsb
 178   isb
 179   bx      LR
 180
 181 ArmDisableBranchPrediction
 182   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 183   bic     r0, r0, #0x00000800   ;
 184   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 185   dsb
 186   isb
 187   bx      LR
 188
 189 ArmSetLowVectors
 190   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 191   bic     r0, r0, #0x00002000   ; clear V bit
 192   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 193   isb
 194   bx      LR
 195
 196 ArmSetHighVectors
 197   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 198   orr     r0, r0, #0x00002000   ; Set V bit
 199   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 200   isb
 201   bx      LR
 202
 203 ArmV7AllDataCachesOperation
 204   stmfd SP!,{r4-r12, LR}
 205   mov   R1, R0                ; Save Function call in R1
 206   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 207   ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 208   mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 209   beq   Finished
 210   mov   R10, #0
 211
 212 Loop1
 213   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 214   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 215   and   R12, R12, #7            ; get those 3 bits alone
 216   cmp   R12, #2
 217   blt   Skip                    ; no cache or only instruction cache at this level
 218   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 219   isb                           ; isb to sync the change to the CacheSizeID reg
 220   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 221   and   R2, R12, #&7            ; extract the line length field
 222   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 223   ldr   R4, =0x3FF
 224   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 225   clz   R5, R4                  ; R5 is the bit position of the way size increment
 226   ldr   R7, =0x00007FFF
 227   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 228
 229 Loop2
 230   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 231
 232 Loop3
 233   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 234   orr   R0, R0, R7, LSL R2      ; factor in the index number
 235
 236   blx   R1
 237
 238   subs  R9, R9, #1              ; decrement the way number
 239   bge   Loop3
 240   subs  R7, R7, #1              ; decrement the index
 241   bge   Loop2
 242 Skip
 243   add   R10, R10, #2            ; increment the cache number
 244   cmp   R3, R10
 245   bgt   Loop1
 246
 247 Finished
 248   dsb
 249   ldmfd SP!, {r4-r12, lr}
 250   bx    LR
 251
 252 ArmDataMemoryBarrier
 253   dmb
 254   bx      LR
 255
 256 ArmDataSynchronizationBarrier
 257 ArmDrainWriteBuffer
 258   dsb
 259   bx      LR
 260
 261 ArmInstructionSynchronizationBarrier
 262   isb
 263   bx      LR
 264
 265 ArmReadVBar
 266   // Set the Address of the Vector Table in the VBAR register
 267   mrc     p15, 0, r0, c12, c0, 0
 268   bx      lr
 269
 270 ArmWriteVBar
 271   // Set the Address of the Vector Table in the VBAR register
 272   mcr     p15, 0, r0, c12, c0, 0
 273   // Ensure the SCTLR.V bit is clear
 274   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 275   bic     r0, r0, #0x00002000   ; clear V bit
 276   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 277   isb
 278   bx      lr
 279
 280 ArmEnableVFP
 281   // Read CPACR (Coprocessor Access Control Register)
 282   mrc     p15, 0, r0, c1, c0, 2
 283   // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 284   orr     r0, r0, #0x00f00000
 285   // Write back CPACR (Coprocessor Access Control Register)
 286   mcr     p15, 0, r0, c1, c0, 2
 287   isb
 288   // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 289   mov     r0, #0x40000000
 290   mcr     p10,#0x7,r0,c8,c0,#0
 291   bx      lr
 292
 293 ArmCallWFI
 294   wfi
 295   bx      lr
 296
 297 //Note: Return 0 in Uniprocessor implementation
 298 ArmReadCbar
 299   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
 300   bx      lr
 301
 302 ArmReadMpidr
 303   mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR
 304   bx      lr
 305
 306 ArmReadTpidrurw
 307   mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW
 308   bx      lr
 309
 310 ArmWriteTpidrurw
 311   mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW
 312   bx      lr
 313
 314 ArmIsArchTimerImplemented
 315   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1
 316   and    r0, r0, #0x000F0000
 317   bx     lr
 318
 319 ArmReadIdPfr1
 320   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register
 321   bx     lr
 322
 323  END