ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16     EXPORT  ArmInvalidateInstructionCache
  17     EXPORT  ArmInvalidateDataCacheEntryByMVA
  18     EXPORT  ArmCleanDataCacheEntryByMVA
  19     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  20     EXPORT  ArmInvalidateDataCacheEntryBySetWay
  21     EXPORT  ArmCleanDataCacheEntryBySetWay
  22     EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
  23     EXPORT  ArmDrainWriteBuffer
  24     EXPORT  ArmEnableMmu
  25     EXPORT  ArmDisableMmu
  26     EXPORT  ArmDisableCachesAndMmu
  27     EXPORT  ArmMmuEnabled
  28     EXPORT  ArmEnableDataCache
  29     EXPORT  ArmDisableDataCache
  30     EXPORT  ArmEnableInstructionCache
  31     EXPORT  ArmDisableInstructionCache
  32     EXPORT  ArmEnableSWPInstruction
  33     EXPORT  ArmEnableBranchPrediction
  34     EXPORT  ArmDisableBranchPrediction
  35     EXPORT  ArmSetLowVectors
  36     EXPORT  ArmSetHighVectors
  37     EXPORT  ArmV7AllDataCachesOperation
  38     EXPORT  ArmV7PerformPoUDataCacheOperation
  39     EXPORT  ArmDataMemoryBarrier
  40     EXPORT  ArmDataSyncronizationBarrier
  41     EXPORT  ArmInstructionSynchronizationBarrier
  42     EXPORT  ArmReadVBar
  43     EXPORT  ArmWriteVBar
  44     EXPORT  ArmEnableVFP
  45     EXPORT  ArmCallWFI
  46     EXPORT  ArmReadCbar
  47     EXPORT  ArmInvalidateInstructionAndDataTlb
  48     EXPORT  ArmReadMpidr
  49     EXPORT  ArmReadTpidrurw
  50     EXPORT  ArmWriteTpidrurw
  51     EXPORT  ArmIsArchTimerImplemented
  52     EXPORT  ArmReadIdPfr1
  53
  54     AREA    ArmV7Support, CODE, READONLY
  55     PRESERVE8
  56
  57 DC_ON           EQU     ( 0x1:SHL:2 )
  58 IC_ON           EQU     ( 0x1:SHL:12 )
  59 CTRL_M_BIT      EQU     (1 << 0)
  60 CTRL_C_BIT      EQU     (1 << 2)
  61 CTRL_B_BIT      EQU     (1 << 7)
  62 CTRL_I_BIT      EQU     (1 << 12)
  63
  64
  65 ArmInvalidateDataCacheEntryByMVA
  66   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  67   dsb
  68   isb
  69   bx      lr
  70
  71 ArmCleanDataCacheEntryByMVA
  72   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  73   dsb
  74   isb
  75   bx      lr
  76
  77
  78 ArmCleanInvalidateDataCacheEntryByMVA
  79   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  80   dsb
  81   isb
  82   bx      lr
  83
  84
  85 ArmInvalidateDataCacheEntryBySetWay
  86   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  87   dsb
  88   isb
  89   bx      lr
  90
  91
  92 ArmCleanInvalidateDataCacheEntryBySetWay
  93   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  94   dsb
  95   isb
  96   bx      lr
  97
  98
  99 ArmCleanDataCacheEntryBySetWay
 100   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
 101   dsb
 102   isb
 103   bx      lr
 104
 105
 106 ArmInvalidateInstructionCache
 107   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
 108   isb
 109   bx      LR
 110
 111 ArmEnableMmu
 112   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 113   orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
 114   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 115   dsb
 116   isb
 117   bx      LR
 118
 119 ArmDisableMmu
 120   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 121   bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
 122   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 123
 124   mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
 125   mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
 126   dsb
 127   isb
 128   bx      LR
 129
 130 ArmDisableCachesAndMmu
 131   mrc   p15, 0, r0, c1, c0, 0           ; Get control register
 132   bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
 133   bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
 134   bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
 135   mcr   p15, 0, r0, c1, c0, 0           ; Write control register
 136   dsb
 137   isb
 138   bx      LR
 139
 140 ArmMmuEnabled
 141   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 142   and     R0,R0,#1
 143   bx      LR
 144
 145 ArmEnableDataCache
 146   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 147   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 148   orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
 149   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 150   dsb
 151   isb
 152   bx      LR
 153
 154 ArmDisableDataCache
 155   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 156   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 157   bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
 158   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 159   dsb
 160   isb
 161   bx      LR
 162
 163 ArmEnableInstructionCache
 164   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 165   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 166   orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
 167   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 168   dsb
 169   isb
 170   bx      LR
 171
 172 ArmDisableInstructionCache
 173   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 174   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 175   BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
 176   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 177   isb
 178   bx      LR
 179
 180 ArmEnableSWPInstruction
 181   mrc     p15, 0, r0, c1, c0, 0
 182   orr     r0, r0, #0x00000400
 183   mcr     p15, 0, r0, c1, c0, 0
 184   isb
 185   bx      LR
 186
 187 ArmEnableBranchPrediction
 188   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 189   orr     r0, r0, #0x00000800   ;
 190   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 191   dsb
 192   isb
 193   bx      LR
 194
 195 ArmDisableBranchPrediction
 196   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 197   bic     r0, r0, #0x00000800   ;
 198   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 199   dsb
 200   isb
 201   bx      LR
 202
 203 ArmSetLowVectors
 204   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 205   bic     r0, r0, #0x00002000   ; clear V bit
 206   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 207   isb
 208   bx      LR
 209
 210 ArmSetHighVectors
 211   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 212   orr     r0, r0, #0x00002000   ; Set V bit
 213   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 214   isb
 215   bx      LR
 216
 217 ArmV7AllDataCachesOperation
 218   stmfd SP!,{r4-r12, LR}
 219   mov   R1, R0                ; Save Function call in R1
 220   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 221   ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 222   mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 223   beq   Finished
 224   mov   R10, #0
 225
 226 Loop1
 227   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 228   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 229   and   R12, R12, #7            ; get those 3 bits alone
 230   cmp   R12, #2
 231   blt   Skip                    ; no cache or only instruction cache at this level
 232   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 233   isb                           ; isb to sync the change to the CacheSizeID reg
 234   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 235   and   R2, R12, #&7            ; extract the line length field
 236   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 237   ldr   R4, =0x3FF
 238   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 239   clz   R5, R4                  ; R5 is the bit position of the way size increment
 240   ldr   R7, =0x00007FFF
 241   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 242
 243 Loop2
 244   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 245
 246 Loop3
 247   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 248   orr   R0, R0, R7, LSL R2      ; factor in the index number
 249
 250   blx   R1
 251
 252   subs  R9, R9, #1              ; decrement the way number
 253   bge   Loop3
 254   subs  R7, R7, #1              ; decrement the index
 255   bge   Loop2
 256 Skip
 257   add   R10, R10, #2            ; increment the cache number
 258   cmp   R3, R10
 259   bgt   Loop1
 260
 261 Finished
 262   dsb
 263   ldmfd SP!, {r4-r12, lr}
 264   bx    LR
 265
 266 ArmV7PerformPoUDataCacheOperation
 267   stmfd SP!,{r4-r12, LR}
 268   mov   R1, R0                ; Save Function call in R1
 269   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 270   ands  R3, R6, #&38000000    ; Mask out all but Level of Unification (LoU)
 271   mov   R3, R3, LSR #26       ; Cache level value (naturally aligned)
 272   beq   Finished2
 273   mov   R10, #0
 274
 275 Loop4
 276   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 277   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 278   and   R12, R12, #7            ; get those 3 bits alone
 279   cmp   R12, #2
 280   blt   Skip2                   ; no cache or only instruction cache at this level
 281   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 282   isb                           ; isb to sync the change to the CacheSizeID reg
 283   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 284   and   R2, R12, #&7            ; extract the line length field
 285   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 286   ldr   R4, =0x3FF
 287   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 288   clz   R5, R4                  ; R5 is the bit position of the way size increment
 289   ldr   R7, =0x00007FFF
 290   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 291
 292 Loop5
 293   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 294
 295 Loop6
 296   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 297   orr   R0, R0, R7, LSL R2      ; factor in the index number
 298
 299   blx   R1
 300
 301   subs  R9, R9, #1              ; decrement the way number
 302   bge   Loop6
 303   subs  R7, R7, #1              ; decrement the index
 304   bge   Loop5
 305 Skip2
 306   add   R10, R10, #2            ; increment the cache number
 307   cmp   R3, R10
 308   bgt   Loop4
 309
 310 Finished2
 311   dsb
 312   ldmfd SP!, {r4-r12, lr}
 313   bx    LR
 314
 315 ArmDataMemoryBarrier
 316   dmb
 317   bx      LR
 318
 319 ArmDataSyncronizationBarrier
 320 ArmDrainWriteBuffer
 321   dsb
 322   bx      LR
 323
 324 ArmInstructionSynchronizationBarrier
 325   isb
 326   bx      LR
 327
 328 ArmReadVBar
 329   // Set the Address of the Vector Table in the VBAR register
 330   mrc     p15, 0, r0, c12, c0, 0
 331   bx      lr
 332
 333 ArmWriteVBar
 334   // Set the Address of the Vector Table in the VBAR register
 335   mcr     p15, 0, r0, c12, c0, 0
 336   // Ensure the SCTLR.V bit is clear
 337   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 338   bic     r0, r0, #0x00002000   ; clear V bit
 339   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 340   isb
 341   bx      lr
 342
 343 ArmEnableVFP
 344   // Read CPACR (Coprocessor Access Control Register)
 345   mrc     p15, 0, r0, c1, c0, 2
 346   // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 347   orr     r0, r0, #0x00f00000
 348   // Write back CPACR (Coprocessor Access Control Register)
 349   mcr     p15, 0, r0, c1, c0, 2
 350   isb
 351   // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 352   mov     r0, #0x40000000
 353   mcr     p10,#0x7,r0,c8,c0,#0
 354   bx      lr
 355
 356 ArmCallWFI
 357   wfi
 358   bx      lr
 359
 360 //Note: Return 0 in Uniprocessor implementation
 361 ArmReadCbar
 362   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
 363   bx      lr
 364
 365 ArmInvalidateInstructionAndDataTlb
 366   mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB
 367   dsb
 368   bx lr
 369
 370 ArmReadMpidr
 371   mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR
 372   bx      lr
 373
 374 ArmReadTpidrurw
 375   mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW
 376   bx      lr
 377
 378 ArmWriteTpidrurw
 379   mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW
 380   bx      lr
 381
 382 ArmIsArchTimerImplemented
 383   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1
 384   and    r0, r0, #0x000F0000
 385   bx     lr
 386
 387 ArmReadIdPfr1
 388   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register
 389   bx     lr
 390
 391  END