VOID\r
);\r
\r
-UINT32\r
-EFIAPI\r
-Cp15IdCode (\r
- VOID\r
- );\r
- \r
UINT32\r
EFIAPI\r
Cp15CacheInfo (\r
GCC_ASM_EXPORT (ArmCallWFI)\r
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
GCC_ASM_EXPORT (ArmReadMpidr)\r
-GCC_ASM_EXPORT (ArmReadMidr)\r
GCC_ASM_EXPORT (ArmReadTpidrurw)\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
mrs x0, mpidr_el1 // read EL1 MPIDR\r
ret\r
\r
-ASM_PFX(ArmReadMidr):\r
- mrs x0, midr_el1 // Read Main ID Register\r
- ret\r
\r
// Keep old function names for C compatibilty for now. Change later?\r
ASM_PFX(ArmReadTpidrurw):\r
GCC_ASM_EXPORT(ArmIsMpCore)\r
GCC_ASM_EXPORT(ArmCallWFI)\r
GCC_ASM_EXPORT(ArmReadMpidr)\r
-GCC_ASM_EXPORT(ArmReadMidr)\r
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
GCC_ASM_EXPORT(ArmEnableFiq)\r
GCC_ASM_EXPORT(ArmDisableFiq)\r
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
bx lr\r
\r
-ASM_PFX(ArmReadMpidr):\r
- mrc p15, 0, r0, c0, c0, 0 @ Read Main ID Register\r
- bx lr\r
-\r
ASM_PFX(ArmEnableFiq):\r
mrs R0,CPSR\r
bic R0,R0,#0x40 @Enable FIQ interrupts\r
GCC_ASM_EXPORT (ArmReadCbar)\r
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
GCC_ASM_EXPORT (ArmReadMpidr)\r
-GCC_ASM_EXPORT (ArmReadMidr)\r
GCC_ASM_EXPORT (ArmReadTpidrurw)\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
ASM_PFX(ArmReadMpidr):\r
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
bx lr\r
-\r
-ASM_PFX(ArmReadMidr):\r
- mrc p15, 0, r0, c0, c0, 0 @ Read Main ID Register\r
- bx lr\r
-\r
+ \r
ASM_PFX(ArmReadTpidrurw):\r
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r
bx lr\r
EXPORT ArmReadCbar\r
EXPORT ArmInvalidateInstructionAndDataTlb\r
EXPORT ArmReadMpidr\r
- EXPORT ArmReadMidr\r
EXPORT ArmReadTpidrurw\r
EXPORT ArmWriteTpidrurw\r
EXPORT ArmIsArchTimerImplemented\r
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
bx lr\r
\r
-ArmReadMidr\r
- mrc p15, 0, r0, c0, c0, 0 ; Read Main ID Register\r
- bx lr\r
-\r
ArmReadTpidrurw\r
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
bx lr\r
\r
.text\r
.align 3\r
-GCC_ASM_EXPORT (ArmMainIdCode)\r
+GCC_ASM_EXPORT (ArmReadMidr)\r
GCC_ASM_EXPORT (ArmCacheInfo)\r
GCC_ASM_EXPORT (ArmGetInterruptState)\r
GCC_ASM_EXPORT (ArmGetFiqState)\r
.set DAIF_FIQ_BIT, (1 << 0)\r
.set DAIF_IRQ_BIT, (1 << 1)\r
\r
-ASM_PFX(ArmiMainIdCode):\r
+ASM_PFX(ArmReadMidr):\r
mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r
ret\r
\r
#------------------------------------------------------------------------------ \r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
.text\r
.align 2\r
-GCC_ASM_EXPORT(Cp15IdCode)\r
+GCC_ASM_EXPORT(ArmReadMidr)\r
GCC_ASM_EXPORT(Cp15CacheInfo)\r
GCC_ASM_EXPORT(ArmGetInterruptState)\r
GCC_ASM_EXPORT(ArmGetFiqState)\r
\r
#------------------------------------------------------------------------------\r
\r
-ASM_PFX(Cp15IdCode):\r
+ASM_PFX(ArmReadMidr):\r
mrc p15,0,R0,c0,c0,0\r
bx LR\r
\r
//------------------------------------------------------------------------------ \r
//\r
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
#define dsb\r
#endif\r
\r
- EXPORT Cp15IdCode\r
+ EXPORT ArmReadMidr\r
EXPORT Cp15CacheInfo\r
EXPORT ArmGetInterruptState\r
EXPORT ArmGetFiqState\r
\r
AREA ArmLibSupport, CODE, READONLY\r
\r
-Cp15IdCode\r
+ArmReadMidr\r
mrc p15,0,R0,c0,c0,0\r
bx LR\r
\r