ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLibV8.h>
  17
  18 .text
  19 .align 3
  20 GCC_ASM_EXPORT (ArmMainIdCode)
  21 GCC_ASM_EXPORT (ArmCacheInfo)
  22 GCC_ASM_EXPORT (ArmGetInterruptState)
  23 GCC_ASM_EXPORT (ArmGetFiqState)
  24 GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)
  25 GCC_ASM_EXPORT (ArmSetTTBR0)
  26 GCC_ASM_EXPORT (ArmGetTCR)
  27 GCC_ASM_EXPORT (ArmSetTCR)
  28 GCC_ASM_EXPORT (ArmGetMAIR)
  29 GCC_ASM_EXPORT (ArmSetMAIR)
  30 GCC_ASM_EXPORT (ArmWriteCpacr)
  31 GCC_ASM_EXPORT (ArmWriteAuxCr)
  32 GCC_ASM_EXPORT (ArmReadAuxCr)
  33 GCC_ASM_EXPORT (ArmInvalidateTlb)
  34 GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)
  35 GCC_ASM_EXPORT (ArmWriteNsacr)
  36 GCC_ASM_EXPORT (ArmWriteScr)
  37 GCC_ASM_EXPORT (ArmWriteMVBar)
  38 GCC_ASM_EXPORT (ArmCallWFE)
  39 GCC_ASM_EXPORT (ArmCallSEV)
  40
  41 #------------------------------------------------------------------------------
  42
  43 .set DAIF_FIQ_BIT,   (1 << 0)
  44 .set DAIF_IRQ_BIT,   (1 << 1)
  45
  46 ASM_PFX(ArmiMainIdCode):
  47   mrs     x0, midr_el1        // Read from Main ID Register (MIDR)
  48   ret
  49
  50 ASM_PFX(ArmCacheInfo):
  51   mrs     x0, ctr_el0         // Read from Cache Type Regiter (CTR)
  52   ret
  53
  54 ASM_PFX(ArmGetInterruptState):
  55   mrs     x0, daif
  56   tst     w0, #DAIF_IRQ_BIT   // Check if IRQ is enabled. Enabled if 0.
  57   mov     w0, #0
  58   mov     w1, #1
  59   csel    w0, w1, w0, ne
  60   ret
  61
  62 ASM_PFX(ArmGetFiqState):
  63   mrs     x0, daif
  64   tst     w0, #DAIF_FIQ_BIT   // Check if FIQ is enabled. Enabled if 0.
  65   mov     w0, #0
  66   mov     w1, #1
  67   csel    w0, w1, w0, ne
  68   ret
  69
  70 ASM_PFX(ArmWriteCpacr):
  71   msr     cpacr_el1, x0      // Coprocessor Access Control Reg (CPACR)
  72   ret
  73
  74 ASM_PFX(ArmWriteAuxCr):
  75   EL1_OR_EL2(x1)
  76 1:msr     actlr_el1, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  77   b       3f
  78 2:msr     actlr_el2, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  79 3:ret
  80
  81 ASM_PFX(ArmReadAuxCr):
  82   EL1_OR_EL2(x1)
  83 1:mrs     x0, actlr_el1      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  84   b       3f
  85 2:mrs     x0, actlr_el2      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  86 3:ret
  87
  88 ASM_PFX(ArmSetTTBR0):
  89   EL1_OR_EL2_OR_EL3(x1)
  90 1:msr     ttbr0_el1, x0      // Translation Table Base Reg 0 (TTBR0)
  91   b       4f
  92 2:msr     ttbr0_el2, x0      // Translation Table Base Reg 0 (TTBR0)
  93   b       4f
  94 3:msr     ttbr0_el3, x0      // Translation Table Base Reg 0 (TTBR0)
  95 4:isb
  96   ret
  97
  98 ASM_PFX(ArmGetTTBR0BaseAddress):
  99   EL1_OR_EL2(x1)
 100 1:mrs     x0, ttbr0_el1
 101   b       3f
 102 2:mrs     x0, ttbr0_el2
 103 3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */
 104   and     x0, x0, x1
 105   isb
 106   ret
 107
 108 ASM_PFX(ArmGetTCR):
 109   EL1_OR_EL2_OR_EL3(x1)
 110 1:mrs     x0, tcr_el1
 111   b       4f
 112 2:mrs     x0, tcr_el2
 113   b       4f
 114 3:mrs     x0, tcr_el3
 115 4:isb
 116   ret
 117
 118 ASM_PFX(ArmSetTCR):
 119   EL1_OR_EL2_OR_EL3(x1)
 120 1:msr     tcr_el1, x0
 121   b       4f
 122 2:msr     tcr_el2, x0
 123   b       4f
 124 3:msr     tcr_el3, x0
 125 4:isb
 126   ret
 127
 128 ASM_PFX(ArmGetMAIR):
 129   EL1_OR_EL2_OR_EL3(x1)
 130 1:mrs     x0, mair_el1
 131   b       4f
 132 2:mrs     x0, mair_el2
 133   b       4f
 134 3:mrs     x0, mair_el3
 135 4:isb
 136   ret
 137
 138 ASM_PFX(ArmSetMAIR):
 139   EL1_OR_EL2_OR_EL3(x1)
 140 1:msr     mair_el1, x0
 141   b       4f
 142 2:msr     mair_el2, x0
 143   b       4f
 144 3:msr     mair_el3, x0
 145 4:isb
 146   ret
 147
 148
 149 //
 150 //VOID
 151 //ArmUpdateTranslationTableEntry (
 152 //  IN VOID  *TranslationTableEntry  // X0
 153 //  IN VOID  *MVA                    // X1
 154 //  );
 155 ASM_PFX(ArmUpdateTranslationTableEntry):
 156    dc      civac, x0             // Clean and invalidate data line
 157    dsb     sy
 158    EL1_OR_EL2_OR_EL3(x0)
 159 1: tlbi    vaae1, x1             // TLB Invalidate VA , EL1
 160    b       4f
 161 2: tlbi    vae2, x1              // TLB Invalidate VA , EL2
 162    b       4f
 163 3: tlbi    vae3, x1              // TLB Invalidate VA , EL3
 164 4: dsb     sy
 165    isb
 166    ret
 167
 168 ASM_PFX(ArmInvalidateTlb):
 169    EL1_OR_EL2_OR_EL3(x0)
 170 1: tlbi  alle1
 171    b     4f
 172 2: tlbi  alle2
 173    b     4f
 174 3: tlbi  alle3
 175 4: dsb   sy
 176    isb
 177    ret
 178
 179 ASM_PFX(ArmWriteNsacr):
 180   msr     cptr_el3, x0           // EL3 Coprocessor Trap Reg (CPTR)
 181   ret                            // Non-Secure Access Control Reg (NSACR) in ARMv7
 182
 183 ASM_PFX(ArmWriteScr):
 184   msr     scr_el3, x0            // Secure configuration register EL3
 185   ret
 186
 187 ASM_PFX(ArmWriteMVBar):
 188   msr    vbar_el3, x0            // Excpetion Vector Base address for Monitor on EL3
 189   ret
 190
 191 ASM_PFX(ArmCallWFE):
 192   wfe
 193   ret
 194
 195 ASM_PFX(ArmCallSEV):
 196   sev
 197   ret
 198
 199 dead:
 200   b       dead
 201
 202 ASM_FUNCTION_REMOVE_IF_UNREFERENCED