ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLibV8.h>
  17
  18 .text
  19 .align 3
  20 GCC_ASM_EXPORT (ArmReadMidr)
  21 GCC_ASM_EXPORT (ArmCacheInfo)
  22 GCC_ASM_EXPORT (ArmGetInterruptState)
  23 GCC_ASM_EXPORT (ArmGetFiqState)
  24 GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)
  25 GCC_ASM_EXPORT (ArmSetTTBR0)
  26 GCC_ASM_EXPORT (ArmGetTCR)
  27 GCC_ASM_EXPORT (ArmSetTCR)
  28 GCC_ASM_EXPORT (ArmGetMAIR)
  29 GCC_ASM_EXPORT (ArmSetMAIR)
  30 GCC_ASM_EXPORT (ArmWriteCpacr)
  31 GCC_ASM_EXPORT (ArmWriteAuxCr)
  32 GCC_ASM_EXPORT (ArmReadAuxCr)
  33 GCC_ASM_EXPORT (ArmInvalidateTlb)
  34 GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)
  35 GCC_ASM_EXPORT (ArmWriteCptr)
  36 GCC_ASM_EXPORT (ArmWriteScr)
  37 GCC_ASM_EXPORT (ArmWriteMVBar)
  38 GCC_ASM_EXPORT (ArmCallWFE)
  39 GCC_ASM_EXPORT (ArmCallSEV)
  40 GCC_ASM_EXPORT (ArmReadCpuActlr)
  41 GCC_ASM_EXPORT (ArmWriteCpuActlr)
  42 GCC_ASM_EXPORT (ArmReadSctlr)
  43
  44 #------------------------------------------------------------------------------
  45
  46 .set DAIF_RD_FIQ_BIT,   (1 << 6)
  47 .set DAIF_RD_IRQ_BIT,   (1 << 7)
  48
  49 ASM_PFX(ArmReadMidr):
  50   mrs     x0, midr_el1        // Read from Main ID Register (MIDR)
  51   ret
  52
  53 ASM_PFX(ArmCacheInfo):
  54   mrs     x0, ctr_el0         // Read from Cache Type Regiter (CTR)
  55   ret
  56
  57 ASM_PFX(ArmGetInterruptState):
  58   mrs     x0, daif
  59   tst     w0, #DAIF_RD_IRQ_BIT  // Check if IRQ is enabled. Enabled if 0 (Z=1)
  60   cset    w0, eq                // if Z=1 return 1, else 0
  61   ret
  62
  63 ASM_PFX(ArmGetFiqState):
  64   mrs     x0, daif
  65   tst     w0, #DAIF_RD_FIQ_BIT  // Check if FIQ is enabled. Enabled if 0 (Z=1)
  66   cset    w0, eq                // if Z=1 return 1, else 0
  67   ret
  68
  69 ASM_PFX(ArmWriteCpacr):
  70   msr     cpacr_el1, x0      // Coprocessor Access Control Reg (CPACR)
  71   ret
  72
  73 ASM_PFX(ArmWriteAuxCr):
  74   EL1_OR_EL2(x1)
  75 1:msr     actlr_el1, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  76   ret
  77 2:msr     actlr_el2, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  78   ret
  79
  80 ASM_PFX(ArmReadAuxCr):
  81   EL1_OR_EL2(x1)
  82 1:mrs     x0, actlr_el1      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  83   ret
  84 2:mrs     x0, actlr_el2      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
  85   ret
  86
  87 ASM_PFX(ArmSetTTBR0):
  88   EL1_OR_EL2_OR_EL3(x1)
  89 1:msr     ttbr0_el1, x0      // Translation Table Base Reg 0 (TTBR0)
  90   b       4f
  91 2:msr     ttbr0_el2, x0      // Translation Table Base Reg 0 (TTBR0)
  92   b       4f
  93 3:msr     ttbr0_el3, x0      // Translation Table Base Reg 0 (TTBR0)
  94 4:isb
  95   ret
  96
  97 ASM_PFX(ArmGetTTBR0BaseAddress):
  98   EL1_OR_EL2(x1)
  99 1:mrs     x0, ttbr0_el1
 100   b       3f
 101 2:mrs     x0, ttbr0_el2
 102 3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */
 103   and     x0, x0, x1
 104   isb
 105   ret
 106
 107 ASM_PFX(ArmGetTCR):
 108   EL1_OR_EL2_OR_EL3(x1)
 109 1:mrs     x0, tcr_el1
 110   b       4f
 111 2:mrs     x0, tcr_el2
 112   b       4f
 113 3:mrs     x0, tcr_el3
 114 4:isb
 115   ret
 116
 117 ASM_PFX(ArmSetTCR):
 118   EL1_OR_EL2_OR_EL3(x1)
 119 1:msr     tcr_el1, x0
 120   b       4f
 121 2:msr     tcr_el2, x0
 122   b       4f
 123 3:msr     tcr_el3, x0
 124 4:isb
 125   ret
 126
 127 ASM_PFX(ArmGetMAIR):
 128   EL1_OR_EL2_OR_EL3(x1)
 129 1:mrs     x0, mair_el1
 130   b       4f
 131 2:mrs     x0, mair_el2
 132   b       4f
 133 3:mrs     x0, mair_el3
 134 4:isb
 135   ret
 136
 137 ASM_PFX(ArmSetMAIR):
 138   EL1_OR_EL2_OR_EL3(x1)
 139 1:msr     mair_el1, x0
 140   b       4f
 141 2:msr     mair_el2, x0
 142   b       4f
 143 3:msr     mair_el3, x0
 144 4:isb
 145   ret
 146
 147
 148 //
 149 //VOID
 150 //ArmUpdateTranslationTableEntry (
 151 //  IN VOID  *TranslationTableEntry  // X0
 152 //  IN VOID  *MVA                    // X1
 153 //  );
 154 ASM_PFX(ArmUpdateTranslationTableEntry):
 155    dc      civac, x0             // Clean and invalidate data line
 156    dsb     sy
 157    EL1_OR_EL2_OR_EL3(x0)
 158 1: tlbi    vaae1, x1             // TLB Invalidate VA , EL1
 159    b       4f
 160 2: tlbi    vae2, x1              // TLB Invalidate VA , EL2
 161    b       4f
 162 3: tlbi    vae3, x1              // TLB Invalidate VA , EL3
 163 4: dsb     sy
 164    isb
 165    ret
 166
 167 ASM_PFX(ArmInvalidateTlb):
 168    EL1_OR_EL2_OR_EL3(x0)
 169 1: tlbi  vmalle1
 170    b     4f
 171 2: tlbi  alle2
 172    b     4f
 173 3: tlbi  alle3
 174 4: dsb   sy
 175    isb
 176    ret
 177
 178 ASM_PFX(ArmWriteCptr):
 179   msr     cptr_el3, x0           // EL3 Coprocessor Trap Reg (CPTR)
 180   ret
 181
 182 ASM_PFX(ArmWriteScr):
 183   msr     scr_el3, x0            // Secure configuration register EL3
 184   isb
 185   ret
 186
 187 ASM_PFX(ArmWriteMVBar):
 188   msr    vbar_el3, x0            // Exception Vector Base address for Monitor on EL3
 189   ret
 190
 191 ASM_PFX(ArmCallWFE):
 192   wfe
 193   ret
 194
 195 ASM_PFX(ArmCallSEV):
 196   sev
 197   ret
 198
 199 ASM_PFX(ArmReadCpuActlr):
 200   mrs   x0, S3_1_c15_c2_0
 201   ret
 202
 203 ASM_PFX(ArmWriteCpuActlr):
 204   msr   S3_1_c15_c2_0, x0
 205   dsb   sy
 206   isb
 207   ret
 208
 209 ASM_PFX(ArmReadSctlr):
 210   EL1_OR_EL2_OR_EL3(x1)
 211 1:mrs   x0, sctlr_el1
 212   ret
 213 2:mrs   x0, sctlr_el2
 214   ret
 215 3:mrs   x0, sctlr_el3
 216 4:ret
 217
 218 ASM_FUNCTION_REMOVE_IF_UNREFERENCED