ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18     INCLUDE AsmMacroIoLib.inc
  19
  20 #ifdef ARM_CPU_ARMv6
  21 // No memory barriers for ARMv6
  22 #define isb
  23 #define dsb
  24 #endif
  25
  26     EXPORT Cp15IdCode
  27     EXPORT Cp15CacheInfo
  28     EXPORT ArmGetInterruptState
  29     EXPORT ArmGetFiqState
  30     EXPORT ArmGetTTBR0BaseAddress
  31     EXPORT ArmSetTTBR0
  32     EXPORT ArmSetDomainAccessControl
  33     EXPORT CPSRMaskInsert
  34     EXPORT CPSRRead
  35     EXPORT ArmWriteCPACR
  36     EXPORT ArmWriteAuxCr
  37     EXPORT ArmReadAuxCr
  38     EXPORT ArmInvalidateTlb
  39     EXPORT ArmUpdateTranslationTableEntry
  40     EXPORT ArmWriteNsacr
  41     EXPORT ArmWriteScr
  42     EXPORT ArmWriteVMBar
  43     EXPORT ArmCallWFE
  44     EXPORT ArmCallSEV
  45
  46     AREA ArmLibSupport, CODE, READONLY
  47
  48 Cp15IdCode
  49   mrc     p15,0,R0,c0,c0,0
  50   bx      LR
  51
  52 Cp15CacheInfo
  53   mrc     p15,0,R0,c0,c0,1
  54   bx      LR
  55
  56 ArmGetInterruptState
  57   mrs     R0,CPSR
  58   tst     R0,#0x80      // Check if IRQ is enabled.
  59   moveq   R0,#1
  60   movne   R0,#0
  61   bx      LR
  62
  63 ArmGetFiqState
  64   mrs     R0,CPSR
  65   tst     R0,#0x40      // Check if FIQ is enabled.
  66   moveq   R0,#1
  67   movne   R0,#0
  68   bx      LR
  69
  70 ArmSetDomainAccessControl
  71   mcr     p15,0,r0,c3,c0,0
  72   bx      lr
  73
  74 CPSRMaskInsert    // on entry, r0 is the mask and r1 is the field to insert
  75   stmfd   sp!, {r4-r12, lr} // save all the banked registers
  76   mov     r3, sp            // copy the stack pointer into a non-banked register
  77   mrs     r2, cpsr          // read the cpsr
  78   bic     r2, r2, r0        // clear mask in the cpsr
  79   and     r1, r1, r0        // clear bits outside the mask in the input
  80   orr     r2, r2, r1        // set field
  81   msr     cpsr_cxsf, r2     // write back cpsr (may have caused a mode switch)
  82   isb
  83   mov     sp, r3            // restore stack pointer
  84   ldmfd   sp!, {r4-r12, lr} // restore registers
  85   bx      lr                // return (hopefully thumb-safe!)             // return (hopefully thumb-safe!)
  86
  87 CPSRRead
  88   mrs     r0, cpsr
  89   bx      lr
  90
  91 ArmWriteCPACR
  92   mcr     p15, 0, r0, c1, c0, 2
  93   isb
  94   bx      lr
  95
  96 ArmWriteAuxCr
  97   mcr     p15, 0, r0, c1, c0, 1
  98   bx      lr
  99
 100 ArmReadAuxCr
 101   mrc     p15, 0, r0, c1, c0, 1
 102   bx      lr
 103
 104 ArmSetTTBR0
 105   mcr     p15,0,r0,c2,c0,0
 106   isb
 107   bx      lr
 108
 109 ArmGetTTBR0BaseAddress
 110   mrc     p15,0,r0,c2,c0,0
 111   LoadConstantToReg(0xFFFFC000, r1)
 112   and     r0, r0, r1
 113   isb
 114   bx      lr
 115
 116 //
 117 //VOID
 118 //ArmUpdateTranslationTableEntry (
 119 //  IN VOID  *TranslationTableEntry  // R0
 120 //  IN VOID  *MVA                    // R1
 121 //  );
 122 ArmUpdateTranslationTableEntry
 123   mcr     p15,0,R0,c7,c14,1     // DCCIMVAC Clean data cache by MVA
 124   dsb
 125   mcr     p15,0,R1,c8,c7,1      // TLBIMVA TLB Invalidate MVA
 126   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 127   dsb
 128   isb
 129   bx      lr
 130
 131 ArmInvalidateTlb
 132   mov     r0,#0
 133   mcr     p15,0,r0,c8,c7,0
 134   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 135   dsb
 136   isb
 137   bx      lr
 138
 139 ArmWriteNsacr
 140   mcr     p15, 0, r0, c1, c1, 2
 141   bx      lr
 142
 143 ArmWriteScr
 144   mcr     p15, 0, r0, c1, c1, 0
 145   bx      lr
 146
 147 ArmWriteVMBar
 148   mcr     p15, 0, r0, c12, c0, 1
 149   bx      lr
 150
 151 ArmCallWFE
 152   wfe
 153   blx   lr
 154
 155 ArmCallSEV
 156   sev
 157   blx   lr
 158
 159   END