ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18     INCLUDE AsmMacroIoLib.inc
  19
  20 #ifdef ARM_CPU_ARMv6
  21 // No memory barriers for ARMv6
  22 #define isb
  23 #define dsb
  24 #endif
  25
  26     EXPORT Cp15IdCode
  27     EXPORT Cp15CacheInfo
  28     EXPORT ArmGetInterruptState
  29     EXPORT ArmGetFiqState
  30     EXPORT ArmGetTTBR0BaseAddress
  31     EXPORT ArmSetTTBR0
  32     EXPORT ArmSetDomainAccessControl
  33     EXPORT CPSRMaskInsert
  34     EXPORT CPSRRead
  35     EXPORT ArmWriteCPACR
  36     EXPORT ArmWriteAuxCr
  37     EXPORT ArmReadAuxCr
  38     EXPORT ArmInvalidateTlb
  39     EXPORT ArmUpdateTranslationTableEntry
  40     EXPORT ArmWriteNsacr
  41     EXPORT ArmWriteScr
  42     EXPORT ArmWriteVMBar
  43
  44     AREA ArmLibSupport, CODE, READONLY
  45
  46 Cp15IdCode
  47   mrc     p15,0,R0,c0,c0,0
  48   bx      LR
  49
  50 Cp15CacheInfo
  51   mrc     p15,0,R0,c0,c0,1
  52   bx      LR
  53
  54 ArmGetInterruptState
  55   mrs     R0,CPSR
  56   tst     R0,#0x80      // Check if IRQ is enabled.
  57   moveq   R0,#1
  58   movne   R0,#0
  59   bx      LR
  60
  61 ArmGetFiqState
  62   mrs     R0,CPSR
  63   tst     R0,#0x40      // Check if FIQ is enabled.
  64   moveq   R0,#1
  65   movne   R0,#0
  66   bx      LR
  67
  68 ArmSetDomainAccessControl
  69   mcr     p15,0,r0,c3,c0,0
  70   bx      lr
  71
  72 CPSRMaskInsert    // on entry, r0 is the mask and r1 is the field to insert
  73   stmfd   sp!, {r4-r12, lr} // save all the banked registers
  74   mov     r3, sp            // copy the stack pointer into a non-banked register
  75   mrs     r2, cpsr          // read the cpsr
  76   bic     r2, r2, r0        // clear mask in the cpsr
  77   and     r1, r1, r0        // clear bits outside the mask in the input
  78   orr     r2, r2, r1        // set field
  79   msr     cpsr_cxsf, r2     // write back cpsr (may have caused a mode switch)
  80   isb
  81   mov     sp, r3            // restore stack pointer
  82   ldmfd   sp!, {r4-r12, lr} // restore registers
  83   bx      lr                // return (hopefully thumb-safe!)             // return (hopefully thumb-safe!)
  84
  85 CPSRRead
  86   mrs     r0, cpsr
  87   bx      lr
  88
  89 ArmWriteCPACR
  90   mcr     p15, 0, r0, c1, c0, 2
  91   isb
  92   bx      lr
  93
  94 ArmWriteAuxCr
  95   mcr     p15, 0, r0, c1, c0, 1
  96   bx      lr
  97
  98 ArmReadAuxCr
  99   mrc     p15, 0, r0, c1, c0, 1
 100   bx      lr
 101
 102 ArmSetTTBR0
 103   mcr     p15,0,r0,c2,c0,0
 104   isb
 105   bx      lr
 106
 107 ArmGetTTBR0BaseAddress
 108   mrc     p15,0,r0,c2,c0,0
 109   LoadConstantToReg(0xFFFFC000, r1)
 110   and     r0, r0, r1
 111   isb
 112   bx      lr
 113
 114 //
 115 //VOID
 116 //ArmUpdateTranslationTableEntry (
 117 //  IN VOID  *TranslationTableEntry  // R0
 118 //  IN VOID  *MVA                    // R1
 119 //  );
 120 ArmUpdateTranslationTableEntry
 121   mcr     p15,0,R0,c7,c14,1     // DCCIMVAC Clean data cache by MVA
 122   dsb
 123   mcr     p15,0,R1,c8,c7,1      // TLBIMVA TLB Invalidate MVA
 124   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 125   dsb
 126   isb
 127   bx      lr
 128
 129 ArmInvalidateTlb
 130   mov     r0,#0
 131   mcr     p15,0,r0,c8,c7,0
 132   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 133   dsb
 134   isb
 135   bx      lr
 136
 137 ArmWriteNsacr
 138   mcr     p15, 0, r0, c1, c1, 2
 139   bx      lr
 140
 141 ArmWriteScr
 142   mcr     p15, 0, r0, c1, c1, 0
 143   bx      lr
 144
 145 ArmWriteVMBar
 146   mcr     p15, 0, r0, c12, c0, 1
 147   bx      lr
 148
 149   END