ArmEnableVFP could crash on an out-of-order CPU. Adding an instruction barrier after writing to CPACR cures the problem.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13134
6f19259b-4bc3-4df7-8a09-
765794883524
orr r0, r0, #0x00f00000\r
# Write back CPACR (Coprocessor Access Control Register)\r
mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
mov r0, #0x40000000\r
mcr p10,#0x7,r0,c8,c0,#0\r
orr r0, r0, #0x00f00000\r
// Write back CPACR (Coprocessor Access Control Register)\r
mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
mov r0, #0x40000000\r
mcr p10,#0x7,r0,c8,c0,#0\r
\r
ASM_PFX(ArmWriteCPACR):\r
mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
bx lr\r
\r
ASM_PFX(ArmWriteAuxCr):\r
\r
ArmWriteCPACR\r
mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
bx lr\r
\r
ArmWriteAuxCr\r