1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 // Copyright (c) 2011, ARM Limited. All rights reserved.
6 // This program and the accompanying materials
7 // are licensed and made available under the terms and conditions of the BSD License
8 // which accompanies this distribution. The full text of the license may be found at
9 // http://opensource.org/licenses/bsd-license.php
11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 //------------------------------------------------------------------------------
16 #include <AsmMacroIoLib.h>
18 INCLUDE AsmMacroIoLib.inc
21 // No memory barriers for ARMv6
28 EXPORT ArmGetInterruptState
30 EXPORT ArmGetTTBR0BaseAddress
32 EXPORT ArmSetDomainAccessControl
38 EXPORT ArmInvalidateTlb
39 EXPORT ArmUpdateTranslationTableEntry
46 AREA ArmLibSupport, CODE, READONLY
58 tst R0,#0x80 // Check if IRQ is enabled.
65 tst R0,#0x40 // Check if FIQ is enabled.
70 ArmSetDomainAccessControl
74 CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert
75 stmfd sp!, {r4-r12, lr} // save all the banked registers
76 mov r3, sp // copy the stack pointer into a non-banked register
77 mrs r2, cpsr // read the cpsr
78 bic r2, r2, r0 // clear mask in the cpsr
79 and r1, r1, r0 // clear bits outside the mask in the input
80 orr r2, r2, r1 // set field
81 msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)
83 mov sp, r3 // restore stack pointer
84 ldmfd sp!, {r4-r12, lr} // restore registers
85 bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)
92 mcr p15, 0, r0, c1, c0, 2
97 mcr p15, 0, r0, c1, c0, 1
101 mrc p15, 0, r0, c1, c0, 1
109 ArmGetTTBR0BaseAddress
111 LoadConstantToReg(0xFFFFC000, r1)
118 //ArmUpdateTranslationTableEntry (
119 // IN VOID *TranslationTableEntry // R0
120 // IN VOID *MVA // R1
122 ArmUpdateTranslationTableEntry
123 mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA
125 mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA
126 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
134 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
140 mcr p15, 0, r0, c1, c1, 2
144 mcr p15, 0, r0, c1, c1, 0
148 mcr p15, 0, r0, c12, c0, 1