ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h

   1 /** @file
   2 *  Header defining Versatile Express constants (Base addresses, sizes, flags)
   3 *
   4 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #ifndef __ARM_VEXPRESS_H__
  17 #define __ARM_VEXPRESS_H__
  18
  19 /*******************************************
  20 // Platform Memory Map
  21 *******************************************/
  22
  23 // Can be NOR0, NOR1, DRAM
  24 #define ARM_VE_REMAP_BASE                       0x00000000
  25 #define ARM_VE_REMAP_SZ                         0x04000000
  26
  27 // Motherboard Peripheral and On-chip peripheral
  28 #define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE       0x10000000
  29 #define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ         0x10000000 /* 256 MB */
  30 #define ARM_VE_BOARD_PERIPH_BASE                0x10000000
  31 #define ARM_VE_CHIP_PERIPH_BASE                 0x10020000
  32
  33 // SMC
  34 #define ARM_VE_SMC_BASE                         0x40000000
  35 #define ARM_VE_SMC_SZ                           0x1C000000
  36
  37 // NOR Flash 1
  38 #define ARM_VE_SMB_NOR0_BASE                    0x40000000
  39 #define ARM_VE_SMB_NOR0_SZ                      0x04000000 /* 64 MB */
  40 // NOR Flash 2
  41 #define ARM_VE_SMB_NOR1_BASE                    0x44000000
  42 #define ARM_VE_SMB_NOR1_SZ                      0x04000000 /* 64 MB */
  43 // SRAM
  44 #define ARM_VE_SMB_SRAM_BASE                    0x48000000
  45 #define ARM_VE_SMB_SRAM_SZ                      0x02000000 /* 32 MB */
  46 // USB, Ethernet, VRAM
  47 #define ARM_VE_SMB_PERIPH_BASE                  0x4C000000
  48 #define ARM_VE_SMB_PERIPH_VRAM                  0x4C000000
  49 #define ARM_VE_SMB_PERIPH_SZ                    0x04000000 /* 32 MB */
  50
  51 // DRAM
  52 #define ARM_VE_DRAM_BASE                        0x60000000
  53 #define ARM_VE_DRAM_SZ                          0x40000000
  54
  55 // External AXI between daughterboards (Logic Tile)
  56 #define ARM_VE_EXT_AXI_BASE                     0xE0000000
  57 #define ARM_VE_EXT_AXI_SZ                       0x20000000
  58
  59 /*******************************************
  60 // Motherboard peripherals
  61 *******************************************/
  62
  63 // Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
  64 #define ARM_VE_SYS_FLAGS_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
  65 #define ARM_VE_SYS_FLAGS_SET_REG                (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
  66 #define ARM_VE_SYS_FLAGS_CLR_REG                (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
  67 #define ARM_VE_SYS_FLAGS_NV_REG                 (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
  68 #define ARM_VE_SYS_FLAGS_NV_SET_REG             (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
  69 #define ARM_VE_SYS_FLAGS_NV_CLR_REG             (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
  70 #define ARM_VE_SYS_PROCID0_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
  71 #define ARM_VE_SYS_PROCID1_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
  72 #define ARM_VE_SYS_CFGDATA_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
  73 #define ARM_VE_SYS_CFGCTRL_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
  74 #define ARM_VE_SYS_CFGSTAT_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
  75
  76 // SP810 Controller
  77 #define SP810_CTRL_BASE                      (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
  78
  79 // Uart0
  80 #define PL011_CONSOLE_UART_BASE                (ARM_VE_BOARD_PERIPH_BASE + 0x09000)
  81 #define PL011_CONSOLE_UART_SPEED               38400
  82
  83 // SP804 Timer Bases
  84 #define SP804_TIMER0_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x11000)
  85 #define SP804_TIMER1_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x11020)
  86 #define SP804_TIMER2_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x12000)
  87 #define SP804_TIMER3_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x12020)
  88
  89 // Dynamic Memory Controller Base
  90 #define ARM_VE_DMC_BASE                         0x100E0000
  91
  92 // Static Memory Controller Base
  93 #define ARM_VE_SMC_CTRL_BASE                    0x100E1000
  94
  95 // System Configuration Controller register Base addresses
  96 //#define ARM_VE_SYS_CFG_CTRL_BASE                0x100E2000
  97 #define ARM_VE_SYS_CFGRW0_REG                   0x100E2000
  98 #define ARM_VE_SYS_CFGRW1_REG                   0x100E2004
  99 #define ARM_VE_SYS_CFGRW2_REG                   0x100E2008
 100
 101 #define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK         0x2000
 102 #define ARM_VE_CFGRW1_REMAP_NOR0                0
 103 #define ARM_VE_CFGRW1_REMAP_NOR1                (1 << 28)
 104 #define ARM_VE_CFGRW1_REMAP_EXT_AXI             (1 << 29)
 105 #define ARM_VE_CFGRW1_REMAP_DRAM                (1 << 30)
 106
 107 // TZPC Base Address
 108 #define ARM_VE_TZPC_BASE                        0x100E6000
 109
 110 // PL301 Fast AXI Base Address
 111 #define ARM_VE_FAXI_BASE                        0x100E9000
 112
 113 // TZASC Defintions
 114 #define ARM_VE_TZASC_BASE                       0x100EC000
 115 #define ARM_VE_DECPROT_BIT_TZPC                 (1 << 6)
 116 #define ARM_VE_DECPROT_BIT_DMC_TZASC            (1 << 11)
 117 #define ARM_VE_DECPROT_BIT_NMC_TZASC            (1 << 12)
 118 #define ARM_VE_DECPROT_BIT_SMC_TZASC            (1 << 13)
 119 #define ARM_VE_DECPROT_BIT_EXT_MAST_TZ          (1)
 120 #define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK       (1 << 3)
 121 #define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK       (1 << 4)
 122 #define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK       (1 << 5)
 123
 124 // L2x0 Cache Controller Base Address
 125 //#define ARM_VE_L2x0_CTLR_BASE                   0x1E00A000
 126
 127
 128 /*******************************************
 129 // Interrupt Map
 130 *******************************************/
 131
 132 // Timer Interrupts
 133 #define TIMER01_INTERRUPT_NUM                34
 134 #define TIMER23_INTERRUPT_NUM                35
 135
 136
 137 /*******************************************
 138 // EFI Memory Map in Permanent Memory (DRAM)
 139 *******************************************/
 140
 141 // This region is allocated at the bottom of the DRAM. It will be used
 142 // for fixed address allocations such as Vector Table
 143 #define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ        SIZE_8MB
 144
 145 // This region is the memory declared to PEI as permanent memory for PEI
 146 // and DXE. EFI stacks and heaps will be declared in this region.
 147 #define ARM_VE_EFI_MEMORY_REGION_SZ             0x1000000
 148
 149
 150 #endif