ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/IoLib.h>
  16 #include <Library/ArmPlatformLib.h>
  17 #include <Library/DebugLib.h>
  18 #include <Library/PcdLib.h>
  19
  20 #include <Drivers/SP804Timer.h>
  21
  22 #include <Ppi/ArmMpCoreInfo.h>
  23
  24 #include <ArmPlatform.h>
  25
  26 UINTN
  27 ArmGetCpuCountPerCluster (
  28   VOID
  29   );
  30
  31 ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {
  32   {
  33     // Cluster 0, Core 0
  34     0x0, 0x0,
  35
  36     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  37     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  38     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  39     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  40     (UINT64)0xFFFFFFFF
  41   },
  42   {
  43     // Cluster 0, Core 1
  44     0x0, 0x1,
  45
  46     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  47     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  48     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  49     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  50     (UINT64)0xFFFFFFFF
  51   },
  52   {
  53     // Cluster 0, Core 2
  54     0x0, 0x2,
  55
  56     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  57     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  58     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  59     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  60     (UINT64)0xFFFFFFFF
  61   },
  62   {
  63     // Cluster 0, Core 3
  64     0x0, 0x3,
  65
  66     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  67     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  68     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  69     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  70     (UINT64)0xFFFFFFFF
  71   }
  72 };
  73
  74 /**
  75   Return the current Boot Mode
  76
  77   This function returns the boot reason on the platform
  78
  79   @return   Return the current Boot Mode of the platform
  80
  81 **/
  82 EFI_BOOT_MODE
  83 ArmPlatformGetBootMode (
  84   VOID
  85   )
  86 {
  87   return BOOT_WITH_FULL_CONFIGURATION;
  88 }
  89
  90 /**
  91   Remap the memory at 0x0
  92
  93   Some platform requires or gives the ability to remap the memory at the address 0x0.
  94   This function can do nothing if this feature is not relevant to your platform.
  95
  96 **/
  97 VOID
  98 ArmPlatformBootRemapping (
  99   VOID
 100   )
 101 {
 102   // Disable memory remapping and return to normal mapping
 103   MmioOr32 (SP810_CTRL_BASE, BIT8);
 104 }
 105
 106 /**
 107   Initialize controllers that must setup in the normal world
 108
 109   This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
 110   in the PEI phase.
 111
 112 **/
 113 VOID
 114 ArmPlatformNormalInitialize (
 115   VOID
 116   )
 117 {
 118   // Nothing to do here
 119 }
 120
 121 /**
 122   Initialize the system (or sometimes called permanent) memory
 123
 124   This memory is generally represented by the DRAM.
 125
 126 **/
 127 VOID
 128 ArmPlatformInitializeSystemMemory (
 129   VOID
 130   )
 131 {
 132   // Configure periodic timer (TIMER0) for 1MHz operation
 133   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
 134   // Configure 1MHz clock
 135   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
 136   // configure SP810 to use 1MHz clock and disable
 137   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
 138   // Configure SP810 to use 1MHz clock and disable
 139   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
 140 }
 141
 142 EFI_STATUS
 143 PrePeiCoreGetMpCoreInfo (
 144   OUT UINTN                   *CoreCount,
 145   OUT ARM_CORE_INFO           **ArmCoreTable
 146   )
 147 {
 148   UINT32   ProcType;
 149
 150   ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
 151   if (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) {
 152     // Only support one cluster
 153     *CoreCount    = ArmGetCpuCountPerCluster ();
 154     *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
 155     return EFI_SUCCESS;
 156   } else {
 157     return EFI_UNSUPPORTED;
 158   }
 159 }
 160
 161 // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
 162 EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
 163 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
 164
 165 EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
 166   {
 167     EFI_PEI_PPI_DESCRIPTOR_PPI,
 168     &mArmMpCoreInfoPpiGuid,
 169     &mMpCoreInfoPpi
 170   }
 171 };
 172
 173 VOID
 174 ArmPlatformGetPlatformPpiList (
 175   OUT UINTN                   *PpiListSize,
 176   OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
 177   )
 178 {
 179   *PpiListSize = sizeof(gPlatformPpiTable);
 180   *PpiList = gPlatformPpiTable;
 181 }