ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Uefi.h>
  16
  17 #include <Library/IoLib.h>
  18 #include <Library/DebugLib.h>
  19
  20 #include <Drivers/PL341Dmc.h>
  21
  22 // Macros for writing to DDR2 controller.
  23 #define DmcWriteReg(reg,val)                    MmioWrite32(DmcBase + reg, val)
  24 #define DmcReadReg(reg)                         MmioRead32(DmcBase + reg)
  25
  26 // Macros for writing/reading to DDR2 PHY controller
  27 #define DmcPhyWriteReg(reg,val)                    MmioWrite32(DmcPhyBase + reg, val)
  28 #define DmcPhyReadReg(reg)                         MmioRead32(DmcPhyBase + reg)
  29
  30 // Initialise PL341 Dynamic Memory Controller
  31 VOID
  32 PL341DmcInit (
  33   IN  UINTN             DmcBase,
  34   IN  PL341_DMC_CONFIG* DmcConfig
  35   )
  36 {
  37   UINTN Index;
  38   UINT32 Chip;
  39
  40   // Set config mode
  41   DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);
  42
  43   //
  44   // Setup the QoS AXI ID bits
  45   //
  46   if (DmcConfig->HasQos) {
  47     // CLCD AXIID = 000
  48     DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);
  49
  50     // Default disable QoS
  51     DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  52     DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  53     DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  54     DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  55     DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  56     DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  57     DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  58     DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  59     DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  60     DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  61     DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  62     DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  63     DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  64     DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  65     DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  66   }
  67
  68   //
  69   // Initialise memory controlller
  70   //
  71   DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->RefreshPeriod);
  72   DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->CasLatency);
  73   DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->WriteLatency);
  74   DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);
  75   DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);
  76   DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);
  77   DmcWriteReg(DMC_T_RCD_REG, DmcConfig->t_rcd);
  78   DmcWriteReg(DMC_T_RFC_REG, DmcConfig->t_rfc);
  79   DmcWriteReg(DMC_T_RP_REG, DmcConfig->t_rp);
  80   DmcWriteReg(DMC_T_RRD_REG, DmcConfig->t_rrd);
  81   DmcWriteReg(DMC_T_WR_REG, DmcConfig->t_wr);
  82   DmcWriteReg(DMC_T_WTR_REG, DmcConfig->t_wtr);
  83   DmcWriteReg(DMC_T_XP_REG, DmcConfig->t_xp);
  84   DmcWriteReg(DMC_T_XSR_REG, DmcConfig->t_xsr);
  85   DmcWriteReg(DMC_T_ESR_REG, DmcConfig->t_esr);
  86   DmcWriteReg(DMC_T_FAW_REG, DmcConfig->t_faw);
  87   DmcWriteReg(DMC_T_WRLAT_DIFF, DmcConfig->t_wdata_en);
  88   DmcWriteReg(DMC_T_RDATA_EN, DmcConfig->t_data_en);
  89
  90   //
  91   // Initialise PL341 Mem Config Registers
  92   //
  93
  94   // Set PL341 Memory Config
  95   DmcWriteReg(DMC_MEMORY_CONFIG_REG, DmcConfig->MemoryCfg);
  96
  97   // Set PL341 Memory Config 2
  98   DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);
  99
 100   // Set PL341 Memory Config 3
 101   DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);
 102
 103   // Set PL341 Chip Select <n>
 104   DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);
 105   DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);
 106   DmcWriteReg(DMC_CHIP_2_CFG_REG, DmcConfig->ChipCfg2);
 107   DmcWriteReg(DMC_CHIP_3_CFG_REG, DmcConfig->ChipCfg3);
 108
 109   // Delay
 110   for (Index = 0; Index < 10; Index++) {
 111     DmcReadReg(DMC_STATUS_REG);
 112   }
 113
 114   if (DmcConfig->IsUserCfg) {
 115     //
 116     // Set Test Chip PHY Registers via PL341 User Config Reg
 117     // Note that user_cfgX registers are Write Only
 118     //
 119     // DLL Freq set = 250MHz - 266MHz
 120     //
 121     DmcWriteReg(DMC_USER_0_CFG_REG, DmcConfig->User0Cfg);
 122
 123     // user_config2
 124     // ------------
 125     // Set defaults before calibrating the DDR2 buffer impendence
 126     // - Disable ODT
 127     // - Default drive strengths
 128     DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);
 129
 130     //
 131     // Auto calibrate the DDR2 buffers impendence
 132     //
 133     while (!(DmcReadReg(DMC_USER_STATUS_REG) & 0x100));
 134
 135     // Set the output driven strength
 136     DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | DmcConfig->User2Cfg);
 137
 138     //
 139     // Set PL341 Feature Control Register
 140     //
 141     // Disable early BRESP - use to optimise CLCD performance
 142     DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);
 143   }
 144
 145   //
 146   // Config memories
 147   //
 148   for (Chip = 0; Chip < DmcConfig->MaxChip; Chip++) {
 149     // Send nop
 150     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_NOP);
 151
 152     // Pre-charge all
 153     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
 154
 155     // Delay
 156     for (Index = 0; Index < 10; Index++) {
 157       DmcReadReg(DMC_STATUS_REG);
 158     }
 159
 160     // Set (EMR2) extended mode register 2
 161     DmcWriteReg(DMC_DIRECT_CMD_REG,
 162       DMC_DIRECT_CMD_CHIP_ADDR(Chip) |
 163       DMC_DIRECT_CMD_BANKADDR(2) |
 164       DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
 165
 166     // Set (EMR3) extended mode register 3
 167     DmcWriteReg(DMC_DIRECT_CMD_REG,
 168       DMC_DIRECT_CMD_CHIP_ADDR(Chip) |
 169       DMC_DIRECT_CMD_BANKADDR(3) |
 170       DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
 171
 172     //
 173     // Set (EMR) Extended Mode Register
 174     //
 175     // Put into OCD default state
 176     DmcWriteReg(DMC_DIRECT_CMD_REG,DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_BANKADDR(1) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
 177
 178     //
 179     // Set (MR) mode register - With DLL reset
 180     //
 181     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg | DDR2_MR_DLL_RESET);
 182
 183     // Pre-charge all
 184     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
 185     // Auto-refresh
 186     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
 187     // Auto-refresh
 188     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
 189
 190     //
 191     // Set (MR) mode register - Without DLL reset
 192     //
 193     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg);
 194
 195     // Delay
 196     for (Index = 0; Index < 10; Index++) {
 197       DmcReadReg(DMC_STATUS_REG);
 198     }
 199
 200     //
 201     // Set (EMR) extended mode register - Enable OCD defaults
 202     //
 203     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |
 204         (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);
 205
 206     // Delay
 207     for (Index = 0; Index < 10; Index++) {
 208       DmcReadReg(DMC_STATUS_REG);
 209     }
 210
 211     // Set (EMR) extended mode register - OCD Exit
 212     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |
 213         (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);
 214
 215     // Delay
 216     for (Index = 0; Index < 10; Index++) {
 217       DmcReadReg(DMC_STATUS_REG);
 218     }
 219   }
 220
 221   // Move DDR2 Controller to Ready state by issueing GO command
 222   DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_GO);
 223
 224   // wait for ready
 225   while (!(DmcReadReg(DMC_STATUS_REG) & DMC_STATUS_READY));
 226
 227 }