ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.S

   1 #
   2 #  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 #
   4 #  This program and the accompanying materials
   5 #  are licensed and made available under the terms and conditions of the BSD License
   6 #  which accompanies this distribution.  The full text of the license may be found at
   7 #  http:#opensource.org/licenses/bsd-license.php
   8 #
   9 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 #
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Library/PcdLib.h>
  16 #include <AutoGen.h>
  17 #include <Drivers/PL35xSmc.h>
  18
  19 .text
  20
  21 #Maintain 8 byte alignment
  22 .align 3
  23
  24
  25 GCC_ASM_EXPORT(SMCInitializeNOR)
  26 GCC_ASM_EXPORT(SMCInitializeSRAM)
  27 GCC_ASM_EXPORT(SMCInitializePeripherals)
  28 GCC_ASM_EXPORT(SMCInitializeVRAM)
  29
  30
  31 # CS0  CS0-Interf0     NOR1 flash on the motherboard
  32 # CS1  CS1-Interf0     Reserved for the motherboard
  33 # CS2  CS2-Interf0     SRAM on the motherboard
  34 # CS3  CS3-Interf0     memory-mapped Ethernet and USB controllers on the motherboard
  35 # CS4  CS0-Interf1     NOR2 flash on the motherboard
  36 # CS5  CS1-Interf1     memory-mapped peripherals
  37 # CS6  CS2-Interf1     memory-mapped peripherals
  38 # CS7  CS3-Interf1     system memory-mapped peripherals on the motherboard.
  39
  40 // IN r1 SmcBase
  41 // IN r2 ChipSelect
  42 // NOTE: This code is been called before any stack has been setup. It means some registers
  43 //       could be overwritten (case of 'r0')
  44 ASM_PFX(SMCInitializeNOR):
  45 #
  46 # Setup NOR1 (CS0-Interface0)
  47 #
  48
  49   # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
  50      #Read cycle timeout = 0xA (0:3)
  51      #Write cycle timeout = 0x3(7:4)
  52      #OE Assertion Delay = 0x9(11:8)
  53      #WE Assertion delay = 0x3(15:12)
  54      #Page cycle timeout = 0x2(19:16)
  55   LoadConstantToReg (0x0002393A,r0)       @ldr     r0, = 0x0002393A
  56   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
  57
  58   # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
  59      # 0x00000002 = MemoryWidth: 32bit
  60      # 0x00000028 = ReadMemoryBurstLength:continuous
  61      # 0x00000280 = WriteMemoryBurstLength:continuous
  62      # 0x00000800 = Set Address Valid
  63   LoadConstantToReg (0x00000AAA,r0)       @ldr     r0, = 0x00000AAA
  64   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
  65
  66  # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
  67      # 0x00000000 = ChipSelect0-Interface 0
  68      # 0x00400000 = CmdTypes: UpdateRegs
  69   LoadConstantToReg (0x00400000,r0)       @ldr     r0, = 0x00400000
  70   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
  71
  72   bx lr
  73
  74 ASM_PFX(SMCInitializeSRAM):
  75 #
  76 # Setup SRAM (CS2-Interface0)
  77 #
  78   LoadConstantToReg (0x00027158,r0)       @ldr     r0, = 0x00027158
  79   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
  80
  81   # 0x00000002 = MemoryWidth: 32bit
  82   # 0x00000800 = Set Address Valid
  83   LoadConstantToReg (0x00000802,r0)       @ldr     r0, = 0x00000802
  84   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
  85
  86   # 0x01000000 = ChipSelect2-Interface 0
  87   # 0x00400000 = CmdTypes: UpdateRegs
  88   LoadConstantToReg (0x01400000,r0)       @ldr     r0, = 0x01400000
  89   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
  90
  91   bx    lr
  92
  93 ASM_PFX(SMCInitializePeripherals):
  94 #
  95 # USB/Eth/VRAM (CS3-Interface0)
  96 #
  97   LoadConstantToReg (0x000CD2AA,r0)      @ldr     r0, = 0x000CD2AA
  98   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
  99
 100   # 0x00000002 = MemoryWidth: 32bit
 101   # 0x00000004 = Memory reads are synchronous
 102   # 0x00000040 = Memory writes are synchronous
 103   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046
 104   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 105
 106   # 0x01800000 = ChipSelect3-Interface 0
 107   # 0x00400000 = CmdTypes: UpdateRegs
 108   LoadConstantToReg (0x01C00000,r0)      @ldr     r0, = 0x01C00000
 109   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 110
 111 #
 112 # Setup NOR3 (CS0-Interface1)
 113 #
 114   LoadConstantToReg (0x0002393A,r0)      @ldr     r0, = 0x0002393A
 115   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
 116
 117   # 0x00000002 = MemoryWidth: 32bit
 118   # 0x00000028 = ReadMemoryBurstLength:continuous
 119   # 0x00000280 = WriteMemoryBurstLength:continuous
 120   # 0x00000800 = Set Address Valid
 121   LoadConstantToReg (0x00000AAA,r0)      @ldr     r0, = 0x00000AAA
 122   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 123
 124   # 0x02000000 = ChipSelect0-Interface 1
 125   # 0x00400000 = CmdTypes: UpdateRegs
 126   LoadConstantToReg (0x02400000,r0)      @ldr     r0, = 0x02400000
 127   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 128
 129 #
 130 # Setup Peripherals (CS3-Interface1)
 131 #
 132   LoadConstantToReg (0x00025156,r0)      @ldr     r0, = 0x00025156
 133   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
 134
 135   # 0x00000002 = MemoryWidth: 32bit
 136   # 0x00000004 = Memory reads are synchronous
 137   # 0x00000040 = Memory writes are synchronous
 138   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046
 139   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 140
 141   # 0x03800000 = ChipSelect3-Interface 1
 142   # 0x00400000 = CmdTypes: UpdateRegs
 143   LoadConstantToReg (0x03C00000,r0)      @ldr     r0, = 0x03C00000
 144   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 145   bx    lr
 146
 147 // IN r1 SmcBase
 148 // IN r2 VideoSRamBase
 149 // NOTE: This code is been called before any stack has been setup. It means some registers
 150 //       could be overwritten (case of 'r0')
 151 ASM_PFX(SMCInitializeVRAM):
 152 #
 153 # Setup VRAM (CS1-Interface0)
 154 #
 155   LoadConstantToReg (0x00049249,r0)      @ldr     r0, =  0x00049249
 156   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
 157
 158   # 0x00000002 = MemoryWidth: 32bit
 159   # 0x00000004 = Memory reads are synchronous
 160   # 0x00000040 = Memory writes are synchronous
 161   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046
 162   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 163
 164   # 0x00800000 = ChipSelect1-Interface 0
 165   # 0x00400000 = CmdTypes: UpdateRegs
 166   LoadConstantToReg (0x00C00000,r0)      @ldr     r0, = 0x00C00000
 167   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 168
 169 #
 170 # Page mode setup for VRAM
 171 #
 172   #read current state
 173   ldr     r0, [r2, #0]
 174   ldr     r0, [r2, #0]
 175   LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000
 176   str     r0, [r2, #0]
 177   ldr     r0, [r2, #0]
 178
 179   #enable page mode
 180   ldr     r0, [r2, #0]
 181   ldr     r0, [r2, #0]
 182   LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000
 183   str     r0, [r2, #0]
 184   LoadConstantToReg (0x00900090,r0)      @ldr     r0, = 0x00900090
 185   str     r0, [r2, #0]
 186
 187   #confirm page mode enabled
 188   ldr     r0, [r2, #0]
 189   ldr     r0, [r2, #0]
 190   LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000
 191   str     r0, [r2, #0]
 192   ldr     r0, [r2, #0]
 193
 194   bx    lr
 195
 196 ASM_FUNCTION_REMOVE_IF_UNREFERENCED