ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/ArmPlatformHelper.S

   1 //
   2 //  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLibV8.h>
  15 #include <Library/ArmLib.h>
  16
  17 .text
  18 .align 2
  19
  20 GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
  21 GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
  22 GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
  23 GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
  24
  25 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)
  26 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
  27
  28 ASM_PFX(ArmPlatformPeiBootAction):
  29   ret
  30
  31 //UINTN
  32 //ArmPlatformGetCorePosition (
  33 //  IN UINTN MpId
  34 //  );
  35 // With this function: CorePos = (ClusterId * 4) + CoreId
  36 ASM_PFX(ArmPlatformGetCorePosition):
  37   and   x1, x0, #ARM_CORE_MASK
  38   and   x0, x0, #ARM_CLUSTER_MASK
  39   add   x0, x1, x0, LSR #6
  40   ret
  41
  42 //UINTN
  43 //ArmPlatformGetPrimaryCoreMpId (
  44 //  VOID
  45 //  );
  46 ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
  47   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)
  48   ldrh  w0, [x0]
  49   ret
  50
  51 //UINTN
  52 //ArmPlatformIsPrimaryCore (
  53 //  IN UINTN MpId
  54 //  );
  55 ASM_PFX(ArmPlatformIsPrimaryCore):
  56   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1)
  57   ldrh  w1, [x1]
  58   and   x0, x0, x1
  59   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x1)
  60   ldrh  w1, [x1]
  61   cmp   w0, w1
  62   mov   x0, #1
  63   mov   x1, #0
  64   csel  x0, x0, x1, eq
  65   ret