ArmPlatformPkg/Sec/SecEntryPoint.S

   1 //
   2 //  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AutoGen.h>
  15 #include <AsmMacroIoLib.h>
  16 #include "SecInternal.h"
  17
  18 .text
  19 .align 3
  20
  21 GCC_ASM_IMPORT(CEntryPoint)
  22 GCC_ASM_IMPORT(ArmPlatformSecBootAction)
  23 GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
  24 GCC_ASM_IMPORT(ArmDisableInterrupts)
  25 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
  26 GCC_ASM_IMPORT(ArmWriteVBar)
  27 GCC_ASM_IMPORT(ArmReadMpidr)
  28 GCC_ASM_IMPORT(SecVectorTable)
  29 GCC_ASM_IMPORT(ArmCpuSynchronizeWait)
  30 GCC_ASM_EXPORT(_ModuleEntryPoint)
  31
  32 StartupAddr:        .word       ASM_PFX(CEntryPoint)
  33
  34 ASM_PFX(_ModuleEntryPoint):
  35   // First ensure all interrupts are disabled
  36   bl    ASM_PFX(ArmDisableInterrupts)
  37
  38   // Ensure that the MMU and caches are off
  39   bl    ASM_PFX(ArmDisableCachesAndMmu)
  40
  41   // Jump to Platform Specific Boot Action function
  42   blx   ASM_PFX(ArmPlatformSecBootAction)
  43
  44   // Set VBAR to the start of the exception vectors in Secure Mode
  45   LoadConstantToReg (ASM_PFX(SecVectorTable), r0)
  46   bl    ASM_PFX(ArmWriteVBar)
  47
  48 _IdentifyCpu:
  49   // Identify CPU ID
  50   bl    ASM_PFX(ArmReadMpidr)
  51   // Get ID of this CPU in Multicore system
  52   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
  53   and   r5, r0, r1
  54
  55   // Is it the Primary Core ?
  56   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
  57   cmp   r5, r1
  58   // Only the primary core initialize the memory (SMC)
  59   beq   _InitMem
  60
  61 _WaitInitMem:
  62   mov   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
  63   bl    ASM_PFX(ArmCpuSynchronizeWait)
  64   // Now the Init Mem is initialized, we setup the secondary core stacks
  65   b     _SetupSecondaryCoreStack
  66
  67 _InitMem:
  68   // Initialize Init Boot Memory
  69   bl    ASM_PFX(ArmPlatformInitializeBootMemory)
  70
  71   // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
  72   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
  73
  74 _SetupPrimaryCoreStack:
  75   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)
  76   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)
  77   // Calculate the Top of the Stack
  78   add   r2, r2, r3
  79   LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)
  80
  81   // The reserved space for global variable must be 8-bytes aligned for pushing
  82   // 64-bit variable on the stack
  83   SetPrimaryStack (r2, r3, r1)
  84
  85   // Set all the SEC global variables to 0
  86   mov     r3, sp
  87   mov     r1, #0x0
  88 _InitGlobals:
  89   str     r1, [r3], #4
  90   cmp     r3, r2
  91   blt     _InitGlobals
  92
  93   b     _PrepareArguments
  94
  95 _SetupSecondaryCoreStack:
  96   // Get the Core Position (ClusterId * 4) + CoreId
  97   GetCorePositionInStack(r0, r5, r1)
  98   // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
  99   add   r0, r0, #1
 100
 101   // Get the base of the stack for the secondary cores
 102   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
 103   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
 104   add   r1, r1, r2
 105
 106   // StackOffset = CorePos * StackSize
 107   mul   r0, r0, r2
 108   // SP = StackBase + StackOffset
 109   add   sp, r1, r0
 110
 111
 112 _PrepareArguments:
 113   // Move sec startup address into a data register
 114   // Ensure we're jumping to FV version of the code (not boot remapped alias)
 115   ldr   r3, StartupAddr
 116
 117   // Jump to SEC C code
 118   //    r0 = mp_id
 119   mov   r0, r5
 120   blx   r3
 121
 122 _NeverReturn:
 123   b _NeverReturn