3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
34 UINT32 UpdateRevision
;
38 UINT32 LoaderRevision
;
39 UINT32 ProcessorFlags
;
43 } EFI_CPU_MICROCODE_HEADER
;
46 UINT32 ExtendedSignatureCount
;
47 UINT32 ExtendedTableChecksum
;
49 } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER
;
52 UINT32 ProcessorSignature
;
54 UINT32 ProcessorChecksum
;
55 } EFI_CPU_MICROCODE_EXTENDED_TABLE
;
63 UINT32 ExtendedModel
: 4;
64 UINT32 ExtendedFamily
: 8;
68 #define EFI_CPUID_SIGNATURE 0x0
69 #define EFI_CPUID_VERSION_INFO 0x1
70 #define EFI_CPUID_CACHE_INFO 0x2
71 #define EFI_CPUID_SERIAL_NUMBER 0x3
72 #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
73 #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
74 #define EFI_CPUID_BRAND_STRING1 0x80000002
75 #define EFI_CPUID_BRAND_STRING2 0x80000003
76 #define EFI_CPUID_BRAND_STRING3 0x80000004
78 #define EFI_MSR_IA32_PLATFORM_ID 0x17
79 #define EFI_MSR_IA32_APIC_BASE 0x1B
80 #define EFI_MSR_EBC_HARD_POWERON 0x2A
81 #define EFI_MSR_EBC_SOFT_POWERON 0x2B
82 #define BINIT_DRIVER_DISABLE 0x40
83 #define INTERNAL_MCERR_DISABLE 0x20
84 #define INITIATOR_MCERR_DISABLE 0x10
85 #define EFI_MSR_EBC_FREQUENCY_ID 0x2C
86 #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
87 #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
88 #define EFI_MSR_PSB_CLOCK_STATUS 0xCD
89 #define EFI_APIC_GLOBAL_ENABLE 0x800
90 #define EFI_MSR_IA32_MISC_ENABLE 0x1A0
91 #define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000
92 #define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008
93 #define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004
94 #define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002
95 #define FAST_STRING_ENABLE_BIT 0x00000001
97 #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
98 #define EFI_CACHE_VARIABLE_MTRR_END 0x20F
99 #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
100 #define EFI_CACHE_MTRR_VALID 0x800
101 #define EFI_CACHE_FIXED_MTRR_VALID 0x400
102 #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
103 #define EFI_MSR_VALID_MASK 0xFFFFFFFFF
104 #define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
105 #define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF
107 #define EFI_IA32_MTRR_FIX64K_00000 0x250
108 #define EFI_IA32_MTRR_FIX16K_80000 0x258
109 #define EFI_IA32_MTRR_FIX16K_A0000 0x259
110 #define EFI_IA32_MTRR_FIX4K_C0000 0x268
111 #define EFI_IA32_MTRR_FIX4K_C8000 0x269
112 #define EFI_IA32_MTRR_FIX4K_D0000 0x26A
113 #define EFI_IA32_MTRR_FIX4K_D8000 0x26B
114 #define EFI_IA32_MTRR_FIX4K_E0000 0x26C
115 #define EFI_IA32_MTRR_FIX4K_E8000 0x26D
116 #define EFI_IA32_MTRR_FIX4K_F0000 0x26E
117 #define EFI_IA32_MTRR_FIX4K_F8000 0x26F
119 #define EFI_IA32_MCG_CAP 0x179
120 #define EFI_IA32_MCG_CTL 0x17B
121 #define EFI_IA32_MC0_CTL 0x400
122 #define EFI_IA32_MC0_STATUS 0x401
124 #define EFI_IA32_PERF_STATUS 0x198
125 #define EFI_IA32_PERF_CTL 0x199
127 #define EFI_CACHE_UNCACHEABLE 0
128 #define EFI_CACHE_WRITECOMBINING 1
129 #define EFI_CACHE_WRITETHROUGH 4
130 #define EFI_CACHE_WRITEPROTECTED 5
131 #define EFI_CACHE_WRITEBACK 6
134 // Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number
136 #define EfiMakeCpuVersion(f, m, s) \
137 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
161 Write back and invalidate the Cpu cache
175 Invalidate the Cpu cache
184 IN UINT32 RegisterInEax
,
185 OUT EFI_CPUID_REGISTER
*Regs
190 Get the Cpu info by excute the CPUID instruction
192 RegisterInEax: -The input value to put into register EAX
193 Regs: -The Output value
201 IN UINT32 RegisterInEax
,
202 IN UINT32 CacheLevel
,
203 OUT EFI_CPUID_REGISTER
*Regs
207 When RegisterInEax != 4, the functionality is the same as EfiCpuid.
208 When RegisterInEax == 4, the function return the deterministic cache
209 parameters by excuting the CPUID instruction
211 RegisterInEax: - The input value to put into register EAX
212 CacheLevel: - The deterministic cache level
213 Regs: - The Output value
229 Index: -The index value to select the register
245 Index: -The index value to select the register
246 Value: -The value to write to the selected register
272 Writing back and invalidate the cache,then diable it
286 Invalidate the cache,then Enable it
304 Return the Eflags value
308 EfiDisableInterrupts (
322 EfiEnableInterrupts (
339 IN UINT16
*FamilyId
, OPTIONAL
340 IN UINT8
*Model
, OPTIONAL
341 IN UINT8
*SteppingId
, OPTIONAL
342 IN UINT8
*Processor OPTIONAL
347 Extract CPU detail version infomation
350 FamilyId - FamilyId, including ExtendedFamilyId
351 Model - Model, including ExtendedModel
352 SteppingId - SteppingId
353 Processor - Processor