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3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 EdkIIGluePciExpressLib.h
19 Public header file for Pci Express Lib
23 #ifndef __EDKII_GLUE_PCI_EXPRESS_LIB_H__
24 #define __EDKII_GLUE_PCI_EXPRESS_LIB_H__
28 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
29 address that can be passed to the PCI Library functions.
31 Computes an address that is compatible with the PCI Library functions. The
32 unused upper bits of Bus, Device, Function and Register are stripped prior to
33 the generation of the address.
35 @param Bus PCI Bus number. Range 0..255.
36 @param Device PCI Device number. Range 0..31.
37 @param Function PCI Function number. Range 0..7.
38 @param Register PCI Register number. Range 0..4095.
40 @return The encode PCI address.
43 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
44 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
47 Reads an 8-bit PCI configuration register.
49 Reads and returns the 8-bit PCI configuration register specified by Address.
50 This function must guarantee that all PCI read and write operations are
53 If Address > 0x0FFFFFFF, then ASSERT().
55 @param Address Address that encodes the PCI Bus, Device, Function and
58 @return The read value from the PCI configuration register.
68 Writes an 8-bit PCI configuration register.
70 Writes the 8-bit PCI configuration register specified by Address with the
71 value specified by Value. Value is returned. This function must guarantee
72 that all PCI read and write operations are serialized.
74 If Address > 0x0FFFFFFF, then ASSERT().
76 @param Address Address that encodes the PCI Bus, Device, Function and
78 @param Value The value to write.
80 @return The value written to the PCI configuration register.
91 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
94 Reads the 8-bit PCI configuration register specified by Address, performs a
95 bitwise inclusive OR between the read result and the value specified by
96 OrData, and writes the result to the 8-bit PCI configuration register
97 specified by Address. The value written to the PCI configuration register is
98 returned. This function must guarantee that all PCI read and write operations
101 If Address > 0x0FFFFFFF, then ASSERT().
103 @param Address Address that encodes the PCI Bus, Device, Function and
105 @param OrData The value to OR with the PCI configuration register.
107 @return The value written back to the PCI configuration register.
118 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
121 Reads the 8-bit PCI configuration register specified by Address, performs a
122 bitwise AND between the read result and the value specified by AndData, and
123 writes the result to the 8-bit PCI configuration register specified by
124 Address. The value written to the PCI configuration register is returned.
125 This function must guarantee that all PCI read and write operations are
128 If Address > 0x0FFFFFFF, then ASSERT().
130 @param Address Address that encodes the PCI Bus, Device, Function and
132 @param AndData The value to AND with the PCI configuration register.
134 @return The value written back to the PCI configuration register.
145 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
146 value, followed a bitwise inclusive OR with another 8-bit value.
148 Reads the 8-bit PCI configuration register specified by Address, performs a
149 bitwise AND between the read result and the value specified by AndData,
150 performs a bitwise inclusive OR between the result of the AND operation and
151 the value specified by OrData, and writes the result to the 8-bit PCI
152 configuration register specified by Address. The value written to the PCI
153 configuration register is returned. This function must guarantee that all PCI
154 read and write operations are serialized.
156 If Address > 0x0FFFFFFF, then ASSERT().
158 @param Address Address that encodes the PCI Bus, Device, Function and
160 @param AndData The value to AND with the PCI configuration register.
161 @param OrData The value to OR with the result of the AND operation.
163 @return The value written back to the PCI configuration register.
168 PciExpressAndThenOr8 (
175 Reads a bit field of a PCI configuration register.
177 Reads the bit field in an 8-bit PCI configuration register. The bit field is
178 specified by the StartBit and the EndBit. The value of the bit field is
181 If Address > 0x0FFFFFFF, then ASSERT().
182 If StartBit is greater than 7, then ASSERT().
183 If EndBit is greater than 7, then ASSERT().
184 If EndBit is less than StartBit, then ASSERT().
186 @param Address PCI configuration register to read.
187 @param StartBit The ordinal of the least significant bit in the bit field.
189 @param EndBit The ordinal of the most significant bit in the bit field.
192 @return The value of the bit field read from the PCI configuration register.
197 PciExpressBitFieldRead8 (
204 Writes a bit field to a PCI configuration register.
206 Writes Value to the bit field of the PCI configuration register. The bit
207 field is specified by the StartBit and the EndBit. All other bits in the
208 destination PCI configuration register are preserved. The new value of the
209 8-bit register is returned.
211 If Address > 0x0FFFFFFF, then ASSERT().
212 If StartBit is greater than 7, then ASSERT().
213 If EndBit is greater than 7, then ASSERT().
214 If EndBit is less than StartBit, then ASSERT().
216 @param Address PCI configuration register to write.
217 @param StartBit The ordinal of the least significant bit in the bit field.
219 @param EndBit The ordinal of the most significant bit in the bit field.
221 @param Value New value of the bit field.
223 @return The value written back to the PCI configuration register.
228 PciExpressBitFieldWrite8 (
236 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
237 writes the result back to the bit field in the 8-bit port.
239 Reads the 8-bit PCI configuration register specified by Address, performs a
240 bitwise inclusive OR between the read result and the value specified by
241 OrData, and writes the result to the 8-bit PCI configuration register
242 specified by Address. The value written to the PCI configuration register is
243 returned. This function must guarantee that all PCI read and write operations
244 are serialized. Extra left bits in OrData are stripped.
246 If Address > 0x0FFFFFFF, then ASSERT().
247 If StartBit is greater than 7, then ASSERT().
248 If EndBit is greater than 7, then ASSERT().
249 If EndBit is less than StartBit, then ASSERT().
251 @param Address PCI configuration register to write.
252 @param StartBit The ordinal of the least significant bit in the bit field.
254 @param EndBit The ordinal of the most significant bit in the bit field.
256 @param OrData The value to OR with the PCI configuration register.
258 @return The value written back to the PCI configuration register.
263 PciExpressBitFieldOr8 (
271 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
272 AND, and writes the result back to the bit field in the 8-bit register.
274 Reads the 8-bit PCI configuration register specified by Address, performs a
275 bitwise AND between the read result and the value specified by AndData, and
276 writes the result to the 8-bit PCI configuration register specified by
277 Address. The value written to the PCI configuration register is returned.
278 This function must guarantee that all PCI read and write operations are
279 serialized. Extra left bits in AndData are stripped.
281 If Address > 0x0FFFFFFF, then ASSERT().
282 If StartBit is greater than 7, then ASSERT().
283 If EndBit is greater than 7, then ASSERT().
284 If EndBit is less than StartBit, then ASSERT().
286 @param Address PCI configuration register to write.
287 @param StartBit The ordinal of the least significant bit in the bit field.
289 @param EndBit The ordinal of the most significant bit in the bit field.
291 @param AndData The value to AND with the PCI configuration register.
293 @return The value written back to the PCI configuration register.
298 PciExpressBitFieldAnd8 (
306 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
307 bitwise inclusive OR, and writes the result back to the bit field in the
310 Reads the 8-bit PCI configuration register specified by Address, performs a
311 bitwise AND followed by a bitwise inclusive OR between the read result and
312 the value specified by AndData, and writes the result to the 8-bit PCI
313 configuration register specified by Address. The value written to the PCI
314 configuration register is returned. This function must guarantee that all PCI
315 read and write operations are serialized. Extra left bits in both AndData and
318 If Address > 0x0FFFFFFF, then ASSERT().
319 If StartBit is greater than 7, then ASSERT().
320 If EndBit is greater than 7, then ASSERT().
321 If EndBit is less than StartBit, then ASSERT().
323 @param Address PCI configuration register to write.
324 @param StartBit The ordinal of the least significant bit in the bit field.
326 @param EndBit The ordinal of the most significant bit in the bit field.
328 @param AndData The value to AND with the PCI configuration register.
329 @param OrData The value to OR with the result of the AND operation.
331 @return The value written back to the PCI configuration register.
336 PciExpressBitFieldAndThenOr8 (
345 Reads a 16-bit PCI configuration register.
347 Reads and returns the 16-bit PCI configuration register specified by Address.
348 This function must guarantee that all PCI read and write operations are
351 If Address > 0x0FFFFFFF, then ASSERT().
352 If Address is not aligned on a 16-bit boundary, then ASSERT().
354 @param Address Address that encodes the PCI Bus, Device, Function and
357 @return The read value from the PCI configuration register.
367 Writes a 16-bit PCI configuration register.
369 Writes the 16-bit PCI configuration register specified by Address with the
370 value specified by Value. Value is returned. This function must guarantee
371 that all PCI read and write operations are serialized.
373 If Address > 0x0FFFFFFF, then ASSERT().
374 If Address is not aligned on a 16-bit boundary, then ASSERT().
376 @param Address Address that encodes the PCI Bus, Device, Function and
378 @param Value The value to write.
380 @return The value written to the PCI configuration register.
391 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
394 Reads the 16-bit PCI configuration register specified by Address, performs a
395 bitwise inclusive OR between the read result and the value specified by
396 OrData, and writes the result to the 16-bit PCI configuration register
397 specified by Address. The value written to the PCI configuration register is
398 returned. This function must guarantee that all PCI read and write operations
401 If Address > 0x0FFFFFFF, then ASSERT().
402 If Address is not aligned on a 16-bit boundary, then ASSERT().
404 @param Address Address that encodes the PCI Bus, Device, Function and
406 @param OrData The value to OR with the PCI configuration register.
408 @return The value written back to the PCI configuration register.
419 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
422 Reads the 16-bit PCI configuration register specified by Address, performs a
423 bitwise AND between the read result and the value specified by AndData, and
424 writes the result to the 16-bit PCI configuration register specified by
425 Address. The value written to the PCI configuration register is returned.
426 This function must guarantee that all PCI read and write operations are
429 If Address > 0x0FFFFFFF, then ASSERT().
430 If Address is not aligned on a 16-bit boundary, then ASSERT().
432 @param Address Address that encodes the PCI Bus, Device, Function and
434 @param AndData The value to AND with the PCI configuration register.
436 @return The value written back to the PCI configuration register.
447 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
448 value, followed a bitwise inclusive OR with another 16-bit value.
450 Reads the 16-bit PCI configuration register specified by Address, performs a
451 bitwise AND between the read result and the value specified by AndData,
452 performs a bitwise inclusive OR between the result of the AND operation and
453 the value specified by OrData, and writes the result to the 16-bit PCI
454 configuration register specified by Address. The value written to the PCI
455 configuration register is returned. This function must guarantee that all PCI
456 read and write operations are serialized.
458 If Address > 0x0FFFFFFF, then ASSERT().
459 If Address is not aligned on a 16-bit boundary, then ASSERT().
461 @param Address Address that encodes the PCI Bus, Device, Function and
463 @param AndData The value to AND with the PCI configuration register.
464 @param OrData The value to OR with the result of the AND operation.
466 @return The value written back to the PCI configuration register.
471 PciExpressAndThenOr16 (
478 Reads a bit field of a PCI configuration register.
480 Reads the bit field in a 16-bit PCI configuration register. The bit field is
481 specified by the StartBit and the EndBit. The value of the bit field is
484 If Address > 0x0FFFFFFF, then ASSERT().
485 If Address is not aligned on a 16-bit boundary, then ASSERT().
486 If StartBit is greater than 15, then ASSERT().
487 If EndBit is greater than 15, then ASSERT().
488 If EndBit is less than StartBit, then ASSERT().
490 @param Address PCI configuration register to read.
491 @param StartBit The ordinal of the least significant bit in the bit field.
493 @param EndBit The ordinal of the most significant bit in the bit field.
496 @return The value of the bit field read from the PCI configuration register.
501 PciExpressBitFieldRead16 (
508 Writes a bit field to a PCI configuration register.
510 Writes Value to the bit field of the PCI configuration register. The bit
511 field is specified by the StartBit and the EndBit. All other bits in the
512 destination PCI configuration register are preserved. The new value of the
513 16-bit register is returned.
515 If Address > 0x0FFFFFFF, then ASSERT().
516 If Address is not aligned on a 16-bit boundary, then ASSERT().
517 If StartBit is greater than 15, then ASSERT().
518 If EndBit is greater than 15, then ASSERT().
519 If EndBit is less than StartBit, then ASSERT().
521 @param Address PCI configuration register to write.
522 @param StartBit The ordinal of the least significant bit in the bit field.
524 @param EndBit The ordinal of the most significant bit in the bit field.
526 @param Value New value of the bit field.
528 @return The value written back to the PCI configuration register.
533 PciExpressBitFieldWrite16 (
541 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
542 writes the result back to the bit field in the 16-bit port.
544 Reads the 16-bit PCI configuration register specified by Address, performs a
545 bitwise inclusive OR between the read result and the value specified by
546 OrData, and writes the result to the 16-bit PCI configuration register
547 specified by Address. The value written to the PCI configuration register is
548 returned. This function must guarantee that all PCI read and write operations
549 are serialized. Extra left bits in OrData are stripped.
551 If Address > 0x0FFFFFFF, then ASSERT().
552 If Address is not aligned on a 16-bit boundary, then ASSERT().
553 If StartBit is greater than 15, then ASSERT().
554 If EndBit is greater than 15, then ASSERT().
555 If EndBit is less than StartBit, then ASSERT().
557 @param Address PCI configuration register to write.
558 @param StartBit The ordinal of the least significant bit in the bit field.
560 @param EndBit The ordinal of the most significant bit in the bit field.
562 @param OrData The value to OR with the PCI configuration register.
564 @return The value written back to the PCI configuration register.
569 PciExpressBitFieldOr16 (
577 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
578 AND, and writes the result back to the bit field in the 16-bit register.
580 Reads the 16-bit PCI configuration register specified by Address, performs a
581 bitwise AND between the read result and the value specified by AndData, and
582 writes the result to the 16-bit PCI configuration register specified by
583 Address. The value written to the PCI configuration register is returned.
584 This function must guarantee that all PCI read and write operations are
585 serialized. Extra left bits in AndData are stripped.
587 If Address > 0x0FFFFFFF, then ASSERT().
588 If Address is not aligned on a 16-bit boundary, then ASSERT().
589 If StartBit is greater than 15, then ASSERT().
590 If EndBit is greater than 15, then ASSERT().
591 If EndBit is less than StartBit, then ASSERT().
593 @param Address PCI configuration register to write.
594 @param StartBit The ordinal of the least significant bit in the bit field.
596 @param EndBit The ordinal of the most significant bit in the bit field.
598 @param AndData The value to AND with the PCI configuration register.
600 @return The value written back to the PCI configuration register.
605 PciExpressBitFieldAnd16 (
613 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
614 bitwise inclusive OR, and writes the result back to the bit field in the
617 Reads the 16-bit PCI configuration register specified by Address, performs a
618 bitwise AND followed by a bitwise inclusive OR between the read result and
619 the value specified by AndData, and writes the result to the 16-bit PCI
620 configuration register specified by Address. The value written to the PCI
621 configuration register is returned. This function must guarantee that all PCI
622 read and write operations are serialized. Extra left bits in both AndData and
625 If Address > 0x0FFFFFFF, then ASSERT().
626 If Address is not aligned on a 16-bit boundary, then ASSERT().
627 If StartBit is greater than 15, then ASSERT().
628 If EndBit is greater than 15, then ASSERT().
629 If EndBit is less than StartBit, then ASSERT().
631 @param Address PCI configuration register to write.
632 @param StartBit The ordinal of the least significant bit in the bit field.
634 @param EndBit The ordinal of the most significant bit in the bit field.
636 @param AndData The value to AND with the PCI configuration register.
637 @param OrData The value to OR with the result of the AND operation.
639 @return The value written back to the PCI configuration register.
644 PciExpressBitFieldAndThenOr16 (
653 Reads a 32-bit PCI configuration register.
655 Reads and returns the 32-bit PCI configuration register specified by Address.
656 This function must guarantee that all PCI read and write operations are
659 If Address > 0x0FFFFFFF, then ASSERT().
660 If Address is not aligned on a 32-bit boundary, then ASSERT().
662 @param Address Address that encodes the PCI Bus, Device, Function and
665 @return The read value from the PCI configuration register.
675 Writes a 32-bit PCI configuration register.
677 Writes the 32-bit PCI configuration register specified by Address with the
678 value specified by Value. Value is returned. This function must guarantee
679 that all PCI read and write operations are serialized.
681 If Address > 0x0FFFFFFF, then ASSERT().
682 If Address is not aligned on a 32-bit boundary, then ASSERT().
684 @param Address Address that encodes the PCI Bus, Device, Function and
686 @param Value The value to write.
688 @return The value written to the PCI configuration register.
699 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
702 Reads the 32-bit PCI configuration register specified by Address, performs a
703 bitwise inclusive OR between the read result and the value specified by
704 OrData, and writes the result to the 32-bit PCI configuration register
705 specified by Address. The value written to the PCI configuration register is
706 returned. This function must guarantee that all PCI read and write operations
709 If Address > 0x0FFFFFFF, then ASSERT().
710 If Address is not aligned on a 32-bit boundary, then ASSERT().
712 @param Address Address that encodes the PCI Bus, Device, Function and
714 @param OrData The value to OR with the PCI configuration register.
716 @return The value written back to the PCI configuration register.
727 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
730 Reads the 32-bit PCI configuration register specified by Address, performs a
731 bitwise AND between the read result and the value specified by AndData, and
732 writes the result to the 32-bit PCI configuration register specified by
733 Address. The value written to the PCI configuration register is returned.
734 This function must guarantee that all PCI read and write operations are
737 If Address > 0x0FFFFFFF, then ASSERT().
738 If Address is not aligned on a 32-bit boundary, then ASSERT().
740 @param Address Address that encodes the PCI Bus, Device, Function and
742 @param AndData The value to AND with the PCI configuration register.
744 @return The value written back to the PCI configuration register.
755 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
756 value, followed a bitwise inclusive OR with another 32-bit value.
758 Reads the 32-bit PCI configuration register specified by Address, performs a
759 bitwise AND between the read result and the value specified by AndData,
760 performs a bitwise inclusive OR between the result of the AND operation and
761 the value specified by OrData, and writes the result to the 32-bit PCI
762 configuration register specified by Address. The value written to the PCI
763 configuration register is returned. This function must guarantee that all PCI
764 read and write operations are serialized.
766 If Address > 0x0FFFFFFF, then ASSERT().
767 If Address is not aligned on a 32-bit boundary, then ASSERT().
769 @param Address Address that encodes the PCI Bus, Device, Function and
771 @param AndData The value to AND with the PCI configuration register.
772 @param OrData The value to OR with the result of the AND operation.
774 @return The value written back to the PCI configuration register.
779 PciExpressAndThenOr32 (
786 Reads a bit field of a PCI configuration register.
788 Reads the bit field in a 32-bit PCI configuration register. The bit field is
789 specified by the StartBit and the EndBit. The value of the bit field is
792 If Address > 0x0FFFFFFF, then ASSERT().
793 If Address is not aligned on a 32-bit boundary, then ASSERT().
794 If StartBit is greater than 31, then ASSERT().
795 If EndBit is greater than 31, then ASSERT().
796 If EndBit is less than StartBit, then ASSERT().
798 @param Address PCI configuration register to read.
799 @param StartBit The ordinal of the least significant bit in the bit field.
801 @param EndBit The ordinal of the most significant bit in the bit field.
804 @return The value of the bit field read from the PCI configuration register.
809 PciExpressBitFieldRead32 (
816 Writes a bit field to a PCI configuration register.
818 Writes Value to the bit field of the PCI configuration register. The bit
819 field is specified by the StartBit and the EndBit. All other bits in the
820 destination PCI configuration register are preserved. The new value of the
821 32-bit register is returned.
823 If Address > 0x0FFFFFFF, then ASSERT().
824 If Address is not aligned on a 32-bit boundary, then ASSERT().
825 If StartBit is greater than 31, then ASSERT().
826 If EndBit is greater than 31, then ASSERT().
827 If EndBit is less than StartBit, then ASSERT().
829 @param Address PCI configuration register to write.
830 @param StartBit The ordinal of the least significant bit in the bit field.
832 @param EndBit The ordinal of the most significant bit in the bit field.
834 @param Value New value of the bit field.
836 @return The value written back to the PCI configuration register.
841 PciExpressBitFieldWrite32 (
849 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
850 writes the result back to the bit field in the 32-bit port.
852 Reads the 32-bit PCI configuration register specified by Address, performs a
853 bitwise inclusive OR between the read result and the value specified by
854 OrData, and writes the result to the 32-bit PCI configuration register
855 specified by Address. The value written to the PCI configuration register is
856 returned. This function must guarantee that all PCI read and write operations
857 are serialized. Extra left bits in OrData are stripped.
859 If Address > 0x0FFFFFFF, then ASSERT().
860 If Address is not aligned on a 32-bit boundary, then ASSERT().
861 If StartBit is greater than 31, then ASSERT().
862 If EndBit is greater than 31, then ASSERT().
863 If EndBit is less than StartBit, then ASSERT().
865 @param Address PCI configuration register to write.
866 @param StartBit The ordinal of the least significant bit in the bit field.
868 @param EndBit The ordinal of the most significant bit in the bit field.
870 @param OrData The value to OR with the PCI configuration register.
872 @return The value written back to the PCI configuration register.
877 PciExpressBitFieldOr32 (
885 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
886 AND, and writes the result back to the bit field in the 32-bit register.
888 Reads the 32-bit PCI configuration register specified by Address, performs a
889 bitwise AND between the read result and the value specified by AndData, and
890 writes the result to the 32-bit PCI configuration register specified by
891 Address. The value written to the PCI configuration register is returned.
892 This function must guarantee that all PCI read and write operations are
893 serialized. Extra left bits in AndData are stripped.
895 If Address > 0x0FFFFFFF, then ASSERT().
896 If Address is not aligned on a 32-bit boundary, then ASSERT().
897 If StartBit is greater than 31, then ASSERT().
898 If EndBit is greater than 31, then ASSERT().
899 If EndBit is less than StartBit, then ASSERT().
901 @param Address PCI configuration register to write.
902 @param StartBit The ordinal of the least significant bit in the bit field.
904 @param EndBit The ordinal of the most significant bit in the bit field.
906 @param AndData The value to AND with the PCI configuration register.
908 @return The value written back to the PCI configuration register.
913 PciExpressBitFieldAnd32 (
921 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
922 bitwise inclusive OR, and writes the result back to the bit field in the
925 Reads the 32-bit PCI configuration register specified by Address, performs a
926 bitwise AND followed by a bitwise inclusive OR between the read result and
927 the value specified by AndData, and writes the result to the 32-bit PCI
928 configuration register specified by Address. The value written to the PCI
929 configuration register is returned. This function must guarantee that all PCI
930 read and write operations are serialized. Extra left bits in both AndData and
933 If Address > 0x0FFFFFFF, then ASSERT().
934 If Address is not aligned on a 32-bit boundary, then ASSERT().
935 If StartBit is greater than 31, then ASSERT().
936 If EndBit is greater than 31, then ASSERT().
937 If EndBit is less than StartBit, then ASSERT().
939 @param Address PCI configuration register to write.
940 @param StartBit The ordinal of the least significant bit in the bit field.
942 @param EndBit The ordinal of the most significant bit in the bit field.
944 @param AndData The value to AND with the PCI configuration register.
945 @param OrData The value to OR with the result of the AND operation.
947 @return The value written back to the PCI configuration register.
952 PciExpressBitFieldAndThenOr32 (
961 Reads a range of PCI configuration registers into a caller supplied buffer.
963 Reads the range of PCI configuration registers specified by StartAddress and
964 Size into the buffer specified by Buffer. This function only allows the PCI
965 configuration registers from a single PCI function to be read. Size is
966 returned. When possible 32-bit PCI configuration read cycles are used to read
967 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
968 and 16-bit PCI configuration read cycles may be used at the beginning and the
971 If StartAddress > 0x0FFFFFFF, then ASSERT().
972 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
973 If Size > 0 and Buffer is NULL, then ASSERT().
975 @param StartAddress Starting address that encodes the PCI Bus, Device,
976 Function and Register.
977 @param Size Size in bytes of the transfer.
978 @param Buffer Pointer to a buffer receiving the data read.
985 PciExpressReadBuffer (
986 IN UINTN StartAddress
,
992 Copies the data in a caller supplied buffer to a specified range of PCI
995 Writes the range of PCI configuration registers specified by StartAddress and
996 Size from the buffer specified by Buffer. This function only allows the PCI
997 configuration registers from a single PCI function to be written. Size is
998 returned. When possible 32-bit PCI configuration write cycles are used to
999 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1000 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1001 and the end of the range.
1003 If StartAddress > 0x0FFFFFFF, then ASSERT().
1004 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1005 If Size > 0 and Buffer is NULL, then ASSERT().
1007 @param StartAddress Starting address that encodes the PCI Bus, Device,
1008 Function and Register.
1009 @param Size Size in bytes of the transfer.
1010 @param Buffer Pointer to a buffer containing the data to write.
1017 PciExpressWriteBuffer (
1018 IN UINTN StartAddress
,