EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/X64/Thunk16.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
   4 # This program and the accompanying materials
   5 # are licensed and made available under the terms and conditions of the BSD License
   6 # which accompanies this distribution.  The full text of the license may be found at
   7 # http://opensource.org/licenses/bsd-license.php
   8 #
   9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 # Module Name:
  13 #
  14 #   Thunk16.S
  15 #
  16 # Abstract:
  17 #
  18 #   Real mode thunk
  19 #
  20 #------------------------------------------------------------------------------
  21
  22 #include <EdkIIGlueBase.h>
  23
  24 .globl ASM_PFX(m16Start)
  25 .globl ASM_PFX(m16Size)
  26 .globl ASM_PFX(mThunk16Attr)
  27 .globl ASM_PFX(m16Gdt)
  28 .globl ASM_PFX(m16GdtrBase)
  29 .globl ASM_PFX(mTransition)
  30 .globl ASM_PFX(InternalAsmThunk16)
  31
  32 # define the structure of IA32_REGS
  33 .set  _EDI, 0       #size 4
  34 .set  _ESI, 4       #size 4
  35 .set  _EBP, 8       #size 4
  36 .set  _ESP, 12      #size 4
  37 .set  _EBX, 16      #size 4
  38 .set  _EDX, 20      #size 4
  39 .set  _ECX, 24      #size 4
  40 .set  _EAX, 28      #size 4
  41 .set  _DS,  32      #size 2
  42 .set  _ES,  34      #size 2
  43 .set  _FS,  36      #size 2
  44 .set  _GS,  38      #size 2
  45 .set  _EFLAGS, 40   #size 8
  46 .set  _EIP, 48      #size 4
  47 .set  _CS, 52       #size 2
  48 .set  _SS, 54       #size 2
  49 .set  IA32_REGS_SIZE, 56
  50
  51     .data
  52
  53 #ifndef __APPLE__
  54 ASM_PFX(m16Size):         .word      ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
  55 ASM_PFX(mThunk16Attr):    .word      _ThunkAttr - ASM_PFX(m16Start)
  56 ASM_PFX(m16Gdt):          .word      ASM_PFX(NullSeg) - ASM_PFX(m16Start)
  57 ASM_PFX(m16GdtrBase):     .word      _16GdtrBase - ASM_PFX(m16Start)
  58 ASM_PFX(mTransition):     .word      _EntryPoint - ASM_PFX(m16Start)
  59 #endif
  60
  61     .text
  62
  63 ASM_PFX(m16Start):
  64
  65 SavedGdt:    .space 10
  66
  67 #------------------------------------------------------------------------------
  68 # _BackFromUserCode() takes control in real mode after 'retf' has been executed
  69 # by user code. It will be shadowed to somewhere in memory below 1MB.
  70 #------------------------------------------------------------------------------
  71 .globl ASM_PFX(BackFromUserCode)
  72 ASM_PFX(BackFromUserCode):
  73 #ifdef __APPLE__
  74     int $3
  75 #else
  76     #
  77     # The order of saved registers on the stack matches the order they appears
  78     # in IA32_REGS structure. This facilitates wrapper function to extract them
  79     # into that structure.
  80     #
  81     # Some instructions for manipulation of segment registers have to be written
  82     # in opcode since 64-bit MASM prevents accesses to those registers.
  83     #
  84     .byte 0x16                          # push ss
  85     .byte 0xe                           # push cs
  86     .byte 0x66
  87     call    L_Base                       # push eip
  88 L_Base:
  89     .byte 0x66
  90     pushq   $0                          # reserved high order 32 bits of EFlags
  91     .byte 0x66, 0x9c                    # pushfd actually
  92     cli                                 # disable interrupts
  93     push    %gs
  94     push    %fs
  95     .byte 6                             # push es
  96     .byte 0x1e                          # push ds
  97     .byte 0x66,0x60                     # pushad
  98     .byte 0x66,0xba                     # mov edx, imm32
  99 _ThunkAttr:  .space  4
 100     testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl
 101     jz      L_1
 102     movl    $0x15cd2401,%eax            # mov ax, 2401h & int 15h
 103     cli                                 # disable interrupts
 104     jnc     L_2
 105 L_1:
 106     testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl
 107     jz      L_2
 108     inb     $0x92,%al
 109     orb     $2,%al
 110     outb    %al, $0x92                   # deactivate A20M#
 111 L_2:
 112     xorw    %ax,%ax                      # xor eax, eax
 113     movl    %ss,%eax                     # mov ax, ss
 114     lea     IA32_REGS_SIZE(%esp), %bp
 115     #
 116     # rsi in the following 2 instructions is indeed bp in 16-bit code
 117     #
 118     movw    %bp, (_ESP - IA32_REGS_SIZE)(%rsi)
 119     .byte 0x66
 120     movl    (_EIP - IA32_REGS_SIZE)(%rsi), %ebx
 121     shlw    $4,%ax                      # shl eax, 4
 122     addw    %ax,%bp                     # add ebp, eax
 123     movw    %cs,%ax
 124     shlw    $4,%ax
 125     lea     (L_64BitCode - L_Base)(%ebx, %eax), %ax
 126     .byte 0x66,0x2e,0x89,0x87           # mov cs:[bx + (L_64Eip - L_Base)], eax
 127     .word   L_64Eip - L_Base
 128     .byte 0x66,0xb8                     # mov eax, imm32
 129 SavedCr4:   .space  4
 130     movq    %rax, %cr4
 131     #
 132     # rdi in the instruction below is indeed bx in 16-bit code
 133     #
 134     .byte 0x66,0x2e                     # 2eh is "cs:" segment override
 135     lgdt    (SavedGdt - L_Base)(%rdi)
 136     .byte 0x66
 137     movl    $0xc0000080,%ecx
 138     rdmsr
 139     orb     $1,%ah
 140     wrmsr
 141     .byte 0x66,0xb8                     # mov eax, imm32
 142 SavedCr0:    .space      4
 143     movq    %rax, %cr0
 144     .byte 0x66,0xea                     # jmp far cs:L_64Bit
 145 L_64Eip:     .space      4
 146 SavedCs:     .space      2
 147 L_64BitCode:
 148     .byte   0x90
 149     .byte   0x67,0xbc                  # mov esp, imm32
 150 SavedSp:    .space 4                   # restore stack
 151     nop
 152 #endif
 153     ret
 154
 155 #ifndef __APPLE__
 156 _EntryPoint: .long      ASM_PFX(ToUserCode) - ASM_PFX(m16Start)
 157              .word      CODE16
 158 _16Gdtr:     .word      GDT_SIZE - 1
 159 _16GdtrBase: .quad      ASM_PFX(NullSeg)
 160 _16Idtr:     .word      0x3ff
 161              .long      0
 162 #endif
 163
 164 #------------------------------------------------------------------------------
 165 # _ToUserCode() takes control in real mode before passing control to user code.
 166 # It will be shadowed to somewhere in memory below 1MB.
 167 #------------------------------------------------------------------------------
 168 .globl ASM_PFX(ToUserCode)
 169 ASM_PFX(ToUserCode):
 170 #ifdef __APPLE__
 171     int $3
 172 #else
 173     movl    %edx,%ss                    # set new segment selectors
 174     movl    %edx,%ds
 175     movl    %edx,%es
 176     movl    %edx,%fs
 177     movl    %edx,%gs
 178     .byte 0x66
 179     movl    $0xc0000080,%ecx
 180     movq    %rax, %cr0
 181     rdmsr
 182     andb    $0b11111110, %ah
 183     wrmsr
 184     movq    %rbp, %cr4
 185     movl    %esi,%ss                    # set up 16-bit stack segment
 186     movw    %bx,%sp                     # set up 16-bit stack pointer
 187     .byte 0x66                          # make the following call 32-bit
 188     call    L_Base1                       # push eip
 189 L_Base1:
 190     popw    %bp                         # ebp <- address of L_Base1
 191     pushq   (IA32_REGS_SIZE + 2)(%esp)
 192     lea     0x0c(%rsi), %eax
 193     pushq   %rax
 194     lret                                # execution begins at next instruction
 195 L_RealMode:
 196     .byte 0x66,0x2e                     # CS and operand size override
 197     lidt    (_16Idtr - L_Base1)(%rsi)
 198     .byte 0x66,0x61                     # popad
 199     .byte 0x1f                          # pop ds
 200     .byte 0x7                           # pop es
 201     .byte 0x0f, 0xa1                    # pop fs
 202     .byte 0x0f, 0xa9                    # pop gs
 203     .byte 0x66, 0x9d                    # popfd
 204     leaw    4(%esp),%sp                 # skip high order 32 bits of EFlags
 205     .byte 0x66                          # make the following retf 32-bit
 206 #endif
 207      lret                                # transfer control to user code
 208
 209 .set  CODE16,  ASM_PFX(_16Code) - .
 210 .set  DATA16,  ASM_PFX(_16Data) - .
 211 .set  DATA32,  ASM_PFX(_32Data) - .
 212
 213 ASM_PFX(NullSeg):   .quad      0
 214 ASM_PFX(_16Code):
 215             .word -1
 216             .word 0
 217             .byte 0
 218             .byte 0x9b
 219             .byte 0x8f                  # 16-bit segment, 4GB limit
 220             .byte 0
 221 ASM_PFX(_16Data):
 222             .word -1
 223             .word 0
 224             .byte 0
 225             .byte 0x93
 226             .byte 0x8f                  # 16-bit segment, 4GB limit
 227             .byte 0
 228 ASM_PFX(_32Data):
 229             .word -1
 230             .word 0
 231             .byte 0
 232             .byte 0x93
 233             .byte 0xcf                  # 16-bit segment, 4GB limit
 234             .byte 0
 235
 236 .set  GDT_SIZE, . - ASM_PFX(NullSeg)
 237
 238 #------------------------------------------------------------------------------
 239 # IA32_REGISTER_SET *
 240 # EFIAPI
 241 # InternalAsmThunk16 (
 242 #   IN      IA32_REGISTER_SET         *RegisterSet,
 243 #   IN OUT  VOID                      *Transition
 244 #   );
 245 #------------------------------------------------------------------------------
 246
 247 .globl ASM_PFX(InternalAsmThunk16)
 248 ASM_PFX(InternalAsmThunk16):
 249 #ifdef __APPLE__
 250     int $3
 251 #else
 252     pushq   %rbp
 253     pushq   %rbx
 254     pushq   %rsi
 255     pushq   %rdi
 256
 257     movq    %ds, %rbx
 258     pushq   %rbx      # Save ds segment register on the stack
 259     movq    %es, %rbx
 260     pushq   %rbx      # Save es segment register on the stack
 261     movq    %ss, %rbx
 262     pushq   %rbx      # Save ss segment register on the stack
 263
 264     .byte   0x0f, 0xa0                  #push   fs
 265     .byte   0x0f, 0xa8                  #push   gs
 266     movq    %rcx, %rsi
 267     movzwl  _SS(%rsi), %r8d
 268     movl    _ESP(%rsi), %edi
 269     lea     -(IA32_REGS_SIZE + 4)(%edi), %rdi
 270     imul    $16, %r8d, %eax
 271     movl    %edi,%ebx                   # ebx <- stack for 16-bit code
 272     pushq   $(IA32_REGS_SIZE / 4)
 273     addl    %eax,%edi                   # edi <- linear address of 16-bit stack
 274     popq    %rcx
 275     rep
 276     movsl                               # copy RegSet
 277     lea     (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx
 278     movl    %edx,%eax                   # eax <- transition code address
 279     andl    $0xf,%edx
 280     shll    $12,%eax                    # segment address in high order 16 bits
 281     lea     (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax
 282     stosl                               # [edi] <- return address of user code
 283     sgdt    (SavedGdt - SavedCr4)(%rcx)
 284     sidt    0x50(%rsp)
 285     movq    %cr0, %rax
 286     movl    %eax, (SavedCr0 - SavedCr4)(%rcx)
 287     andl    $0x7ffffffe,%eax            # clear PE, PG bits
 288     movq    %cr4, %rbp
 289     movl    %ebp, (%rcx)                # save CR4 in SavedCr4
 290     andl    $0x300,%ebp                 # clear all but PCE and OSFXSR bits
 291     movl    %r8d, %esi                  # esi <- 16-bit stack segment
 292     .byte      0x6a, DATA32
 293     popq    %rdx
 294     lgdt    (_16Gdtr - SavedCr4)(%rcx)
 295     movl    %edx,%ss
 296     pushfq
 297     lea     -8(%rdx), %edx
 298     lea     L_RetFromRealMode, %r8
 299     pushq   %r8
 300     movl    %cs, %r8d
 301     movw    %r8w, (SavedCs - SavedCr4)(%rcx)
 302     movl    %esp, (SavedSp - SavedCr4)(%rcx)
 303     .byte   0xff, 0x69                  #  jmp (_EntryPoint - SavedCr4)(%rcx)
 304     .byte   _EntryPoint - SavedCr4
 305 L_RetFromRealMode:
 306     popfq
 307     lidt    0x50(%rsp)
 308     lea     -IA32_REGS_SIZE(%rbp), %eax
 309     .byte 0x0f, 0xa9                    # pop gs
 310     .byte 0x0f, 0xa1                    # pop fs
 311
 312     popq     %rbx
 313     movq     %rbx, %ss
 314     popq     %rbx
 315     movq     %rbx, %es
 316     popq     %rbx
 317     movq     %rbx, %ds
 318
 319     popq    %rdi
 320     popq    %rsi
 321     popq    %rbx
 322     popq    %rbp
 323 #endif
 324     ret