EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.h

   1 /*++
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14     Ehci.h
  15
  16 Abstract:
  17
  18
  19 Revision History
  20 --*/
  21
  22 #ifndef _EHCI_H
  23 #define _EHCI_H
  24
  25 //
  26 // Universal Host Controller Interface data structures and defines
  27 //
  28 #include <IndustryStandard/pci22.h>
  29
  30
  31 extern UINTN  gEHCDebugLevel;
  32 extern UINTN  gEHCErrorLevel;
  33
  34
  35 #define STALL_1_MACRO_SECOND              1
  36 #define STALL_1_MILLI_SECOND              1000 * STALL_1_MACRO_SECOND
  37 #define STALL_1_SECOND                    1000 * STALL_1_MILLI_SECOND
  38
  39 #define SETUP_PACKET_PID_CODE             0x02
  40 #define INPUT_PACKET_PID_CODE             0x01
  41 #define OUTPUT_PACKET_PID_CODE            0x0
  42
  43 #define ITD_SELECT_TYPE                   0x0
  44 #define QH_SELECT_TYPE                    0x01
  45 #define SITD_SELECT_TYPE                  0x02
  46 #define FSTN_SELECT_TYPE                  0x03
  47
  48 #define EHCI_SET_PORT_RESET_RECOVERY_TIME     50 * STALL_1_MILLI_SECOND
  49 #define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME   STALL_1_MILLI_SECOND
  50 #define EHCI_GENERIC_TIMEOUT                  50 * STALL_1_MILLI_SECOND
  51 #define EHCI_GENERIC_RECOVERY_TIME            50 * STALL_1_MACRO_SECOND
  52 #define EHCI_SYNC_REQUEST_POLLING_TIME        50 * STALL_1_MACRO_SECOND
  53 #define EHCI_ASYNC_REQUEST_POLLING_TIME       50 * STALL_1_MILLI_SECOND
  54
  55 #define USB_BAR_INDEX                     0 /* how many bytes away from USB_BASE to 0x10 */
  56
  57 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1
  58
  59 #define EHCI_MIN_PACKET_SIZE              8
  60 #define EHCI_MAX_PACKET_SIZE              1024
  61 #define EHCI_MAX_FRAME_LIST_LENGTH        1024
  62 #define EHCI_BLOCK_SIZE_WITH_TT           64
  63 #define EHCI_BLOCK_SIZE                   512
  64 #define EHCI_MAX_QTD_CAPACITY             (EFI_PAGE_SIZE * 5)
  65
  66 #define NAK_COUNT_RELOAD                  3
  67 #define QTD_ERROR_COUNTER                 1
  68 #define HIGH_BANDWIDTH_PIPE_MULTIPLIER    1
  69
  70 #define QTD_STATUS_ACTIVE                 0x80
  71 #define QTD_STATUS_HALTED                 0x40
  72 #define QTD_STATUS_BUFFER_ERR             0x20
  73 #define QTD_STATUS_BABBLE_ERR             0x10
  74 #define QTD_STATUS_TRANSACTION_ERR        0x08
  75 #define QTD_STATUS_DO_STOP_SPLIT          0x02
  76 #define QTD_STATUS_DO_START_SPLIT         0
  77 #define QTD_STATUS_DO_PING                0x01
  78 #define QTD_STATUS_DO_OUT                 0
  79
  80 #define DATA0                             0
  81 #define DATA1                             1
  82
  83 #define MICRO_FRAME_0_CHANNEL             0x01
  84 #define MICRO_FRAME_1_CHANNEL             0x02
  85 #define MICRO_FRAME_2_CHANNEL             0x04
  86 #define MICRO_FRAME_3_CHANNEL             0x08
  87 #define MICRO_FRAME_4_CHANNEL             0x10
  88 #define MICRO_FRAME_5_CHANNEL             0x20
  89 #define MICRO_FRAME_6_CHANNEL             0x40
  90 #define MICRO_FRAME_7_CHANNEL             0x80
  91
  92 #define CONTROL_TRANSFER                  0x01
  93 #define BULK_TRANSFER                     0x02
  94 #define SYNC_INTERRUPT_TRANSFER           0x04
  95 #define ASYNC_INTERRUPT_TRANSFER          0x08
  96 #define SYNC_ISOCHRONOUS_TRANSFER         0x10
  97 #define ASYNC_ISOCHRONOUS_TRANSFER        0x20
  98
  99
 100 //
 101 // Enhanced Host Controller Registers definitions
 102 //
 103 extern EFI_DRIVER_BINDING_PROTOCOL  gEhciDriverBinding;
 104 extern EFI_COMPONENT_NAME_PROTOCOL  gEhciComponentName;
 105
 106 #define USBCMD            0x0     /* Command Register Offset 00-03h */
 107 #define USBCMD_RS         0x01    /* Run / Stop */
 108 #define USBCMD_HCRESET    0x02    /* Host controller reset */
 109 #define USBCMD_FLS_512    0x04    /* 512 elements (2048bytes) in Frame List */
 110 #define USBCMD_FLS_256    0x08    /* 256 elements (1024bytes) in Frame List */
 111 #define USBCMD_PSE        0x10    /* Periodic schedule enable */
 112 #define USBCMD_ASE        0x20    /* Asynchronous schedule enable */
 113 #define USBCMD_IAAD       0x40    /* Interrupt on async advance doorbell */
 114
 115 #define USBSTS            0x04    /* Statue Register Offset 04-07h */
 116 #define USBSTS_HSE        0x10    /* Host system error */
 117 #define USBSTS_IAA        0x20    /* Interrupt on async advance */
 118 #define USBSTS_HCH        0x1000  /* Host controller halted */
 119 #define USBSTS_PSS        0x4000  /* Periodic schedule status */
 120 #define USBSTS_ASS        0x8000  /* Asynchronous schedule status */
 121
 122 #define USBINTR           0x08    /* Command Register Offset 08-0bh */
 123
 124 #define FRINDEX           0x0c    /* Frame Index Offset 0c-0fh */
 125
 126 #define CTRLDSSGMENT      0x10    /* 4G Segment Selector Offset 10-13h */
 127
 128 #define PERIODICLISTBASE  0x14    /* Frame List Base Address Offset 14-17h */
 129
 130 #define ASYNCLISTADDR     0x18    /* Next Asynchronous List Address Offset 18-1bh */
 131
 132 #define CONFIGFLAG        0x40    /* Configured Flag Register Offset 40-43h */
 133 #define CONFIGFLAG_CF     0x01    /* Configure Flag */
 134
 135 #define PORTSC            0x44    /* Port Status/Control Offset 44-47h */
 136 #define PORTSC_CCS        0x01    /* Current Connect Status*/
 137 #define PORTSC_CSC        0x02    /* Connect Status Change */
 138 #define PORTSC_PED        0x04    /* Port Enable / Disable */
 139 #define PORTSC_PEDC       0x08    /* Port Enable / Disable Change */
 140 #define PORTSC_OCA        0x10    /* Over current Active */
 141 #define PORTSC_OCC        0x20    /* Over current Change */
 142 #define PORTSC_FPR        0x40    /* Force Port Resume */
 143 #define PORTSC_SUSP       0x80    /* Port Suspend State */
 144 #define PORTSC_PR         0x100   /* Port Reset */
 145 #define PORTSC_LS_KSTATE  0x400   /* Line Status K-state */
 146 #define PORTSC_LS_JSTATE  0x800   /* Line Status J-state */
 147 #define PORTSC_PP         0x1000  /* Port Power */
 148 #define PORTSC_PO         0x2000  /* Port Owner */
 149
 150 #define CAPLENGTH         0       /* Capability Register Length 00h */
 151
 152 #define HCIVERSION        0x02    /* Interface Version Number  02-03h */
 153
 154 #define HCSPARAMS         0x04    /* Structural Parameters 04-07h */
 155 #define HCSP_NPORTS       0x0f    /* Number of physical downstream ports on host controller */
 156
 157 #define HCCPARAMS         0x08    /* Capability Parameters 08-0bh */
 158 #define HCCP_64BIT        0x01    /* 64-bit Addressing Capability */
 159 #define HCCP_PFLF         0x02    /* Programmable Frame List Flag */
 160 #define HCCP_EECP         0xff00  /* EHCI Extemded Capabilities Pointer */
 161
 162 #define HCSPPORTROUTE     0x0c    /* Companion Port Route Description 60b */
 163
 164 #define CLASSC            0x09    /* Class Code 09-0bh */
 165
 166 #define USBBASE           0x10    /* Base Address to Memory-mapped Host Controller Register Space 10-13h */
 167
 168 #define SBRN              0x60    /* Serial Bus Release Number 60h */
 169
 170 #define FLADJ             0x61    /* Frame Length Adjustment Register 61h */
 171
 172 #define PORTWAKECAP       0x62    /* Port wake capablilities register(OPIONAL)  61-62h */
 173
 174 //
 175 // PCI Configuration Registers
 176 //
 177 #define EHCI_PCI_CLASSC         0x09
 178 #define EHCI_PCI_MEMORY_BASE    0x10
 179
 180 //
 181 // Memory Offset Registers
 182 //
 183 #define EHCI_MEMORY_CAPLENGTH   0x0
 184 #define EHCI_MEMORY_CONFIGFLAG  0x40
 185
 186 //
 187 // USB Base Class Code,Sub-Class Code and Programming Interface
 188 //
 189 #define PCI_CLASSC_PI_EHCI      0x20
 190
 191 #define SETUP_PACKET_ID         0x2D
 192 #define INPUT_PACKET_ID         0x69
 193 #define OUTPUT_PACKET_ID        0xE1
 194 #define ERROR_PACKET_ID         0x55
 195
 196 #define bit(a)                  (1 << (a))
 197
 198 #define GET_0B_TO_31B(Addr)     (((UINTN) Addr) & (0xffffffff))
 199 #define GET_32B_TO_63B(Addr)    ((UINTN)RShiftU64((UINTN) Addr, 32) & (0xffffffff))
 200
 201
 202 //
 203 // Ehci Data and Ctrl Structures
 204 //
 205 #pragma pack(1)
 206
 207 typedef struct {
 208   UINT8 PI;
 209   UINT8 SubClassCode;
 210   UINT8 BaseCode;
 211 } USB_CLASSC;
 212
 213 typedef struct {
 214   UINT32  NextQtdTerminate : 1;
 215   UINT32  Rsvd1 : 4;
 216   UINT32  NextQtdPointer : 27;
 217
 218   UINT32  AltNextQtdTerminate : 1;
 219   UINT32  Rsvd2 : 4;
 220   UINT32  AltNextQtdPointer : 27;
 221
 222   UINT32  Status : 8;
 223   UINT32  PidCode : 2;
 224   UINT32  ErrorCount : 2;
 225   UINT32  CurrentPage : 3;
 226   UINT32  InterruptOnComplete : 1;
 227   UINT32  TotalBytes : 15;
 228   UINT32  DataToggle : 1;
 229
 230   UINT32  CurrentOffset : 12;
 231   UINT32  BufferPointer0 : 20;
 232
 233   UINT32  Rsvd3 : 12;
 234   UINT32  BufferPointer1 : 20;
 235
 236   UINT32  Rsvd4 : 12;
 237   UINT32  BufferPointer2 : 20;
 238
 239   UINT32  Rsvd5 : 12;
 240   UINT32  BufferPointer3 : 20;
 241
 242   UINT32  Rsvd6 : 12;
 243   UINT32  BufferPointer4 : 20;
 244
 245   UINT32  ExtBufferPointer0;
 246   UINT32  ExtBufferPointer1;
 247   UINT32  ExtBufferPointer2;
 248   UINT32  ExtBufferPointer3;
 249   UINT32  ExtBufferPointer4;
 250 } EHCI_QTD_HW;
 251
 252 typedef struct {
 253   UINT32  QhTerminate : 1;
 254   UINT32  SelectType : 2;
 255   UINT32  Rsvd1 : 2;
 256   UINT32  QhHorizontalPointer : 27;
 257
 258   UINT32  DeviceAddr : 7;
 259   UINT32  Inactive : 1;
 260   UINT32  EndpointNum : 4;
 261   UINT32  EndpointSpeed : 2;
 262   UINT32  DataToggleControl : 1;
 263   UINT32  HeadReclamationFlag : 1;
 264   UINT32  MaxPacketLen : 11;
 265   UINT32  ControlEndpointFlag : 1;
 266   UINT32  NakCountReload : 4;
 267
 268   UINT32  InerruptScheduleMask : 8;
 269   UINT32  SplitComletionMask : 8;
 270   UINT32  HubAddr : 7;
 271   UINT32  PortNum : 7;
 272   UINT32  Multiplier : 2;
 273
 274   UINT32  Rsvd2 : 5;
 275   UINT32  CurrentQtdPointer : 27;
 276
 277   UINT32  NextQtdTerminate : 1;
 278   UINT32  Rsvd3 : 4;
 279   UINT32  NextQtdPointer : 27;
 280
 281   UINT32  AltNextQtdTerminate : 1;
 282   UINT32  NakCount : 4;
 283   UINT32  AltNextQtdPointer : 27;
 284
 285   UINT32  Status : 8;
 286   UINT32  PidCode : 2;
 287   UINT32  ErrorCount : 2;
 288   UINT32  CurrentPage : 3;
 289   UINT32  InterruptOnComplete : 1;
 290   UINT32  TotalBytes : 15;
 291   UINT32  DataToggle : 1;
 292
 293   UINT32  CurrentOffset : 12;
 294   UINT32  BufferPointer0 : 20;
 295
 296   UINT32  CompleteSplitMask : 8;
 297   UINT32  Rsvd4 : 4;
 298   UINT32  BufferPointer1 : 20;
 299
 300   UINT32  FrameTag : 5;
 301   UINT32  SplitBytes : 7;
 302   UINT32  BufferPointer2 : 20;
 303
 304   UINT32  Rsvd5 : 12;
 305   UINT32  BufferPointer3 : 20;
 306
 307   UINT32  Rsvd6 : 12;
 308   UINT32  BufferPointer4 : 20;
 309
 310   UINT32  ExtBufferPointer0;
 311   UINT32  ExtBufferPointer1;
 312   UINT32  ExtBufferPointer2;
 313   UINT32  ExtBufferPointer3;
 314   UINT32  ExtBufferPointer4;
 315 } EHCI_QH_HW;
 316
 317 typedef struct {
 318   UINT32  LinkTerminate : 1;
 319   UINT32  SelectType : 2;
 320   UINT32  Rsvd : 2;
 321   UINT32  LinkPointer : 27;
 322 } FRAME_LIST_ENTRY;
 323
 324 #pragma pack()
 325
 326 typedef struct _EHCI_QTD_ENTITY     EHCI_QTD_ENTITY;
 327 typedef struct _EHCI_QH_ENTITY      EHCI_QH_ENTITY;
 328 typedef struct _EHCI_ASYNC_REQUEST  EHCI_ASYNC_REQUEST;
 329
 330 struct _EHCI_QTD_ENTITY {
 331   EHCI_QTD_HW     Qtd;
 332   UINT32          TotalBytes;
 333   UINT32          StaticTotalBytes;
 334   UINT32          StaticCurrentOffset;
 335   EHCI_QTD_ENTITY *Prev;
 336   EHCI_QTD_ENTITY *Next;
 337   EHCI_QTD_ENTITY *AltNext;
 338   EHCI_QH_ENTITY  *SelfQh;
 339 };
 340
 341 struct _EHCI_QH_ENTITY {
 342   EHCI_QH_HW      Qh;
 343   EHCI_QH_ENTITY  *Next;
 344   EHCI_QH_ENTITY  *Prev;
 345   EHCI_QTD_ENTITY *FirstQtdPtr;
 346   EHCI_QTD_ENTITY *LastQtdPtr;
 347   EHCI_QTD_ENTITY *AltQtdPtr;
 348   UINTN           Interval;
 349   UINT8           TransferType;
 350 };
 351
 352 #define GET_QH_ENTITY_ADDR(a)   ((EHCI_QH_ENTITY *) a)
 353 #define GET_QTD_ENTITY_ADDR(a)  ((EHCI_QTD_ENTITY *) a)
 354
 355
 356 //
 357 // Ehci Managment Structures
 358 //
 359 #define USB2_HC_DEV_FROM_THIS(a)  CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
 360
 361 #define USB2_HC_DEV_SIGNATURE     EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')
 362
 363 struct _EHCI_ASYNC_REQUEST {
 364   UINT8                           TransferType;
 365   EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;
 366   VOID                            *Context;
 367   EHCI_ASYNC_REQUEST              *Prev;
 368   EHCI_ASYNC_REQUEST              *Next;
 369   EHCI_QH_ENTITY                  *QhPtr;
 370 };
 371
 372 typedef struct _MEMORY_MANAGE_HEADER {
 373   UINT8                         *BitArrayPtr;
 374   UINTN                         BitArraySizeInBytes;
 375   UINT8                         *MemoryBlockPtr;
 376   UINTN                         MemoryBlockSizeInBytes;
 377   VOID                          *Mapping;
 378   struct _MEMORY_MANAGE_HEADER  *Next;
 379 } MEMORY_MANAGE_HEADER;
 380
 381 typedef struct _USB2_HC_DEV {
 382   UINTN                     Signature;
 383   EFI_PCI_IO_PROTOCOL       *PciIo;
 384   EFI_USB2_HC_PROTOCOL      Usb2Hc;
 385   UINTN                     PeriodicFrameListLength;
 386   VOID                      *PeriodicFrameListBuffer;
 387   VOID                      *PeriodicFrameListMap;
 388   VOID                      *AsyncList;
 389   EHCI_ASYNC_REQUEST        *AsyncRequestList;
 390   EFI_EVENT                 AsyncRequestEvent;
 391   EFI_UNICODE_STRING_TABLE  *ControllerNameTable;
 392   MEMORY_MANAGE_HEADER      *MemoryHeader;
 393   UINT8                                         Is64BitCapable;
 394   UINT32                    High32BitAddr;
 395   UINT32                    UsbCapabilityLen;
 396   UINT16                    DeviceSpeed[16];
 397 } USB2_HC_DEV;
 398
 399
 400 //
 401 // Internal Functions Declaration
 402 //
 403
 404 //
 405 // EhciMem Functions
 406 //
 407 EFI_STATUS
 408 CreateMemoryBlock (
 409   IN  USB2_HC_DEV               *HcDev,
 410   OUT MEMORY_MANAGE_HEADER      **MemoryHeader,
 411   IN  UINTN                     MemoryBlockSizeInPages
 412   )
 413 /*++
 414
 415 Routine Description:
 416
 417   Use PciIo->AllocateBuffer to allocate common buffer for the memory block,
 418   and use PciIo->Map to map the common buffer for Bus Master Read/Write.
 419
 420 Arguments:
 421
 422   HcDev                  - USB2_HC_DEV
 423   MemoryHeader           - MEMORY_MANAGE_HEADER to output
 424   MemoryBlockSizeInPages - MemoryBlockSizeInPages
 425
 426 Returns:
 427
 428   EFI_SUCCESS           Success
 429   EFI_OUT_OF_RESOURCES  Fail for no resources
 430   EFI_UNSUPPORTED       Unsupported currently
 431
 432 --*/
 433 ;
 434
 435 EFI_STATUS
 436 FreeMemoryHeader (
 437   IN USB2_HC_DEV               *HcDev,
 438   IN MEMORY_MANAGE_HEADER      *MemoryHeader
 439   )
 440 /*++
 441
 442 Routine Description:
 443
 444   Free Memory Header
 445
 446 Arguments:
 447
 448   HcDev         - USB2_HC_DEV
 449   MemoryHeader  - MemoryHeader to be freed
 450
 451 Returns:
 452
 453   EFI_SUCCESS            Success
 454   EFI_INVALID_PARAMETER  Parameter is error
 455
 456 --*/
 457 ;
 458
 459 VOID
 460 InsertMemoryHeaderToList (
 461   IN MEMORY_MANAGE_HEADER     *MemoryHeader,
 462   IN MEMORY_MANAGE_HEADER     *NewMemoryHeader
 463   )
 464 /*++
 465
 466 Routine Description:
 467
 468   Insert Memory Header To List
 469
 470 Arguments:
 471
 472   MemoryHeader    - MEMORY_MANAGE_HEADER
 473   NewMemoryHeader - MEMORY_MANAGE_HEADER
 474
 475 Returns:
 476
 477   VOID
 478
 479 --*/
 480 ;
 481
 482 EFI_STATUS
 483 AllocMemInMemoryBlock (
 484   IN  MEMORY_MANAGE_HEADER     *MemoryHeader,
 485   OUT VOID                     **Pool,
 486   IN  UINTN                    NumberOfMemoryUnit
 487   )
 488 /*++
 489
 490 Routine Description:
 491
 492   Alloc Memory In MemoryBlock
 493
 494 Arguments:
 495
 496   MemoryHeader        - MEMORY_MANAGE_HEADER
 497   Pool                - Place to store pointer to memory
 498   NumberOfMemoryUnit  - Number Of Memory Unit
 499
 500 Returns:
 501
 502   EFI_SUCCESS    Success
 503   EFI_NOT_FOUND  Can't find the free memory
 504
 505 --*/
 506 ;
 507
 508 BOOLEAN
 509 IsMemoryBlockEmptied (
 510   IN MEMORY_MANAGE_HEADER     *MemoryHeaderPtr
 511   )
 512 /*++
 513
 514 Routine Description:
 515
 516   Is Memory Block Emptied
 517
 518 Arguments:
 519
 520   MemoryHeaderPtr - MEMORY_MANAGE_HEADER
 521
 522 Returns:
 523
 524   TRUE    Empty
 525   FALSE   Not Empty
 526
 527 --*/
 528 ;
 529
 530 VOID
 531 DelinkMemoryBlock (
 532   IN MEMORY_MANAGE_HEADER     *FirstMemoryHeader,
 533   IN MEMORY_MANAGE_HEADER     *NeedFreeMemoryHeader
 534   )
 535 /*++
 536
 537 Routine Description:
 538
 539   Delink Memory Block
 540
 541 Arguments:
 542
 543   FirstMemoryHeader     - MEMORY_MANAGE_HEADER
 544   NeedFreeMemoryHeader  - MEMORY_MANAGE_HEADER
 545
 546 Returns:
 547
 548   VOID
 549
 550 --*/
 551 ;
 552
 553 EFI_STATUS
 554 InitialMemoryManagement (
 555   IN USB2_HC_DEV     *HcDev
 556   )
 557 /*++
 558
 559 Routine Description:
 560
 561   Initialize Memory Management
 562
 563 Arguments:
 564
 565   HcDev - USB2_HC_DEV
 566
 567 Returns:
 568
 569   EFI_SUCCESS        Success
 570   EFI_DEVICE_ERROR   Fail
 571
 572 --*/
 573 ;
 574
 575 EFI_STATUS
 576 DeinitialMemoryManagement (
 577   IN USB2_HC_DEV     *HcDev
 578   )
 579 /*++
 580
 581 Routine Description:
 582
 583   Deinitialize Memory Management
 584
 585 Arguments:
 586
 587   HcDev - USB2_HC_DEV
 588
 589 Returns:
 590
 591   EFI_SUCCESS        Success
 592   EFI_DEVICE_ERROR   Fail
 593
 594 --*/
 595 ;
 596
 597 EFI_STATUS
 598 EhciAllocatePool (
 599   IN  USB2_HC_DEV     *HcDev,
 600   OUT UINT8           **Pool,
 601   IN  UINTN           AllocSize
 602   )
 603 /*++
 604
 605 Routine Description:
 606
 607   Ehci Allocate Pool
 608
 609 Arguments:
 610
 611   HcDev     - USB2_HC_DEV
 612   Pool      - Place to store pointer to the memory buffer
 613   AllocSize - Alloc Size
 614
 615 Returns:
 616
 617   EFI_SUCCESS        Success
 618   EFI_DEVICE_ERROR   Fail
 619
 620 --*/
 621 ;
 622
 623 VOID
 624 EhciFreePool (
 625   IN USB2_HC_DEV     *HcDev,
 626   IN UINT8           *Pool,
 627   IN UINTN           AllocSize
 628   )
 629 /*++
 630
 631 Routine Description:
 632
 633   Uhci Free Pool
 634
 635 Arguments:
 636
 637   HcDev     - USB_HC_DEV
 638   Pool      - Pool to free
 639   AllocSize - Pool size
 640
 641 Returns:
 642
 643   VOID
 644
 645 --*/
 646 ;
 647
 648 //
 649 // EhciReg Functions
 650 //
 651 EFI_STATUS
 652 ReadEhcCapabiltiyReg (
 653   IN USB2_HC_DEV             *HcDev,
 654   IN UINT32                  CapabiltiyRegAddr,
 655   IN OUT UINT32              *Data
 656   )
 657 /*++
 658
 659 Routine Description:
 660
 661   Read  Ehc Capabitlity register
 662
 663 Arguments:
 664
 665   HcDev             - USB2_HC_DEV
 666   CapabiltiyRegAddr - Ehc Capability register address
 667   Data              - A pointer to data read from register
 668
 669 Returns:
 670
 671   EFI_SUCCESS        Success
 672   EFI_DEVICE_ERROR   Fail
 673
 674 --*/
 675 ;
 676
 677 EFI_STATUS
 678 ReadEhcOperationalReg (
 679   IN USB2_HC_DEV             *HcDev,
 680   IN UINT32                  OperationalRegAddr,
 681   IN OUT UINT32              *Data
 682   )
 683 /*++
 684
 685 Routine Description:
 686
 687   Read  Ehc Operation register
 688
 689 Arguments:
 690
 691   HcDev                - USB2_HC_DEV
 692   OperationalRegAddr   - Ehc Operation register address
 693   Data                 - A pointer to data read from register
 694
 695 Returns:
 696
 697   EFI_SUCCESS        Success
 698   EFI_DEVICE_ERROR   Fail
 699
 700 --*/
 701 ;
 702
 703 EFI_STATUS
 704 WriteEhcOperationalReg (
 705   IN USB2_HC_DEV             *HcDev,
 706   IN UINT32                  OperationalRegAddr,
 707   IN UINT32                  Data
 708   )
 709 /*++
 710
 711 Routine Description:
 712
 713   Write  Ehc Operation register
 714
 715 Arguments:
 716
 717   HcDev                - USB2_HC_DEV
 718   OperationalRegAddr   - Ehc Operation register address
 719   Data                 - 32bit write to register
 720
 721 Returns:
 722
 723   EFI_SUCCESS        Success
 724   EFI_DEVICE_ERROR   Fail
 725
 726 --*/
 727 ;
 728
 729 EFI_STATUS
 730 SetEhcDoorbell (
 731   IN  USB2_HC_DEV     *HcDev
 732   )
 733 /*++
 734
 735 Routine Description:
 736
 737   Set Ehc door bell bit
 738
 739 Arguments:
 740
 741   HcDev - USB2_HC_DEV
 742
 743 Returns:
 744
 745   EFI_SUCCESS       Success
 746   EFI_DEVICE_ERROR  Fail
 747
 748 --*/
 749 ;
 750
 751 EFI_STATUS
 752 SetFrameListLen (
 753   IN USB2_HC_DEV     *HcDev,
 754   IN UINTN           Length
 755   )
 756 /*++
 757
 758 Routine Description:
 759
 760   Set the length of Frame List
 761
 762 Arguments:
 763
 764   HcDev    - USB2_HC_DEV
 765   Length   - the required length of frame list
 766
 767 Returns:
 768
 769   EFI_SUCCESS            Success
 770   EFI_INVALID_PARAMETER  Invalid parameter
 771   EFI_DEVICE_ERROR       Fail
 772
 773 --*/
 774 ;
 775
 776 BOOLEAN
 777 IsFrameListProgrammable (
 778   IN  USB2_HC_DEV     *HcDev
 779   )
 780 /*++
 781
 782 Routine Description:
 783
 784   Whether frame list is programmable
 785
 786 Arguments:
 787
 788   HcDev - USB2_HC_DEV
 789
 790 Returns:
 791
 792   TRUE   Programmable
 793   FALSE  Unprogrammable
 794
 795 --*/
 796 ;
 797
 798 BOOLEAN
 799 IsPeriodicScheduleEnabled (
 800   IN  USB2_HC_DEV     *HcDev
 801   )
 802 /*++
 803
 804 Routine Description:
 805
 806   Whether periodic schedule is enabled
 807
 808 Arguments:
 809
 810   HcDev - USB2_HC_DEV
 811
 812 Returns:
 813
 814   TRUE   Enabled
 815   FALSE  Disabled
 816
 817 --*/
 818 ;
 819
 820 BOOLEAN
 821 IsAsyncScheduleEnabled (
 822   IN  USB2_HC_DEV     *HcDev
 823   )
 824 /*++
 825
 826 Routine Description:
 827
 828   Whether asynchronous schedule is enabled
 829
 830 Arguments:
 831
 832   HcDev - USB2_HC_DEV
 833
 834 Returns:
 835
 836   TRUE   Enabled
 837   FALSE  Disabled
 838
 839 --*/
 840 ;
 841
 842 BOOLEAN
 843 IsEhcPortEnabled (
 844   IN  USB2_HC_DEV     *HcDev,
 845   IN  UINT8           PortNum
 846   )
 847 /*++
 848
 849 Routine Description:
 850
 851   Whether port is enabled
 852
 853 Arguments:
 854
 855   HcDev - USB2_HC_DEV
 856
 857 Returns:
 858
 859   TRUE   Enabled
 860   FALSE  Disabled
 861
 862 --*/
 863 ;
 864
 865 BOOLEAN
 866 IsEhcReseted (
 867   IN  USB2_HC_DEV     *HcDev
 868   )
 869 /*++
 870
 871 Routine Description:
 872
 873   Whether Ehc is halted
 874
 875 Arguments:
 876
 877   HcDev - USB2_HC_DEV
 878
 879 Returns:
 880
 881   TRUE   Reseted
 882   FALSE  Unreseted
 883
 884 --*/
 885 ;
 886
 887 BOOLEAN
 888 IsEhcHalted (
 889   IN  USB2_HC_DEV     *HcDev
 890   )
 891 /*++
 892
 893 Routine Description:
 894
 895   Whether Ehc is halted
 896
 897 Arguments:
 898
 899   HcDev  - USB2_HC_DEV
 900
 901 Returns:
 902
 903   TRUE   Halted
 904   FALSE  Not halted
 905
 906 --*/
 907 ;
 908
 909 BOOLEAN
 910 IsEhcSysError (
 911   IN  USB2_HC_DEV     *HcDev
 912   )
 913 /*++
 914
 915 Routine Description:
 916
 917   Whether Ehc is system error
 918
 919 Arguments:
 920
 921   HcDev  - USB2_HC_DEV
 922
 923 Returns:
 924
 925   TRUE   System error
 926   FALSE  No system error
 927
 928 --*/
 929 ;
 930
 931 BOOLEAN
 932 IsHighSpeedDevice (
 933   IN EFI_USB2_HC_PROTOCOL *This,
 934   IN UINT8                PortNum
 935   )
 936 /*++
 937
 938 Routine Description:
 939
 940   Whether high speed device attached
 941
 942 Arguments:
 943
 944   HcDev - USB2_HC_DEV
 945
 946 Returns:
 947
 948   TRUE   High speed
 949   FALSE  Full speed
 950
 951 --*/
 952 ;
 953
 954 EFI_STATUS
 955 WaitForEhcReset (
 956   IN USB2_HC_DEV             *HcDev,
 957   IN UINTN                   Timeout
 958   )
 959 /*++
 960
 961 Routine Description:
 962
 963   wait for Ehc reset or timeout
 964
 965 Arguments:
 966
 967   HcDev   - USB2_HC_DEV
 968   Timeout - timeout threshold
 969
 970 Returns:
 971
 972   EFI_SUCCESS    Success
 973   EFI_TIMEOUT    Timeout
 974
 975 --*/
 976 ;
 977
 978 EFI_STATUS
 979 WaitForEhcHalt (
 980   IN USB2_HC_DEV             *HcDev,
 981   IN UINTN                   Timeout
 982   )
 983 /*++
 984
 985 Routine Description:
 986
 987   wait for Ehc halt or timeout
 988
 989 Arguments:
 990
 991   HcDev   - USB2_HC_DEV
 992   Timeout - timeout threshold
 993
 994 Returns:
 995
 996   EFI_SUCCESS    Success
 997   EFI_TIMEOUT    Timeout
 998
 999 --*/
1000 ;
1001
1002 EFI_STATUS
1003 WaitForEhcNotHalt (
1004   IN USB2_HC_DEV             *HcDev,
1005   IN UINTN                   Timeout
1006   )
1007 /*++
1008
1009 Routine Description:
1010
1011   wait for Ehc not halt or timeout
1012
1013 Arguments:
1014
1015   HcDev   - USB2_HC_DEV
1016   Timeout - timeout threshold
1017
1018 Returns:
1019
1020   EFI_SUCCESS    Success
1021   EFI_TIMEOUT    Timeout
1022
1023 --*/
1024 ;
1025
1026 EFI_STATUS
1027 WaitForEhcDoorbell (
1028   IN  USB2_HC_DEV            *HcDev,
1029   IN UINTN                   Timeout
1030   )
1031 /*++
1032
1033 Routine Description:
1034
1035   Wait for periodic schedule disable or timeout
1036
1037 Arguments:
1038
1039   HcDev   - USB2_HC_DEV
1040   Timeout - timeout threshold
1041
1042 Returns:
1043
1044   EFI_SUCCESS    Success
1045   EFI_TIMEOUT    Timeout
1046
1047 --*/
1048 ;
1049
1050 EFI_STATUS
1051 WaitForAsyncScheduleEnable (
1052   IN USB2_HC_DEV             *HcDev,
1053   IN UINTN                   Timeout
1054   )
1055 /*++
1056
1057 Routine Description:
1058
1059   Wait for Ehc asynchronous schedule enable or timeout
1060
1061 Arguments:
1062
1063   HcDev   - USB2_HC_DEV
1064   Timeout - timeout threshold
1065
1066 Returns:
1067
1068   EFI_SUCCESS    Success
1069   EFI_TIMEOUT    Timeout
1070
1071 --*/
1072 ;
1073
1074 EFI_STATUS
1075 WaitForAsyncScheduleDisable (
1076   IN USB2_HC_DEV             *HcDev,
1077   IN UINTN                   Timeout
1078   )
1079 /*++
1080
1081 Routine Description:
1082
1083   Wait for Ehc asynchronous schedule disable or timeout
1084
1085 Arguments:
1086
1087   HcDev   - USB2_HC_DEV
1088   Timeout - timeout threshold
1089
1090 Returns:
1091
1092   EFI_SUCCESS    Success
1093   EFI_TIMEOUT    Timeout
1094
1095 --*/
1096 ;
1097
1098 EFI_STATUS
1099 WaitForPeriodicScheduleEnable (
1100   IN USB2_HC_DEV             *HcDev,
1101   IN UINTN                   Timeout
1102   )
1103 /*++
1104
1105 Routine Description:
1106
1107   Wait for Ehc periodic schedule enable or timeout
1108
1109 Arguments:
1110
1111   HcDev   - USB2_HC_DEV
1112   Timeout - timeout threshold
1113
1114 Returns:
1115
1116   EFI_SUCCESS    Success
1117   EFI_TIMEOUT    Timeout
1118
1119 --*/
1120 ;
1121
1122 EFI_STATUS
1123 WaitForPeriodicScheduleDisable (
1124   IN USB2_HC_DEV             *HcDev,
1125   IN UINTN                   Timeout
1126   )
1127 /*++
1128
1129 Routine Description:
1130
1131   Wait for periodic schedule disable or timeout
1132
1133 Arguments:
1134
1135   HcDev   - USB2_HC_DEV
1136   Timeout - timeout threshold
1137
1138 Returns:
1139
1140   EFI_SUCCESS    Success
1141   EFI_TIMEOUT    Timeout
1142
1143 --*/
1144 ;
1145
1146 EFI_STATUS
1147 GetCapabilityLen (
1148   IN USB2_HC_DEV     *HcDev
1149   )
1150 /*++
1151
1152 Routine Description:
1153
1154   Get the length of capability register
1155
1156 Arguments:
1157
1158   HcDev - USB2_HC_DEV
1159
1160 Returns:
1161
1162   EFI_SUCCESS       Success
1163   EFI_DEVICE_ERROR  Fail
1164
1165 --*/
1166 ;
1167
1168 EFI_STATUS
1169 SetFrameListBaseAddr (
1170   IN USB2_HC_DEV     *HcDev,
1171   IN UINT32          FrameBuffer
1172   )
1173 /*++
1174
1175 Routine Description:
1176
1177   Set base address of frame list first entry
1178
1179 Arguments:
1180
1181   HcDev       - USB2_HC_DEV
1182   FrameBuffer - base address of first entry of frame list
1183
1184 Returns:
1185
1186   EFI_SUCCESS       Success
1187   EFI_DEVICE_ERROR  Fail
1188
1189 --*/
1190 ;
1191
1192 EFI_STATUS
1193 SetAsyncListAddr (
1194   IN USB2_HC_DEV        *HcDev,
1195   IN EHCI_QH_ENTITY     *QhPtr
1196   )
1197 /*++
1198
1199 Routine Description:
1200
1201   Set address of first Async schedule Qh
1202
1203 Arguments:
1204
1205   HcDev    - USB2_HC_DEV
1206   QhPtr    - A pointer to first Qh in the Async schedule
1207
1208 Returns:
1209
1210   EFI_SUCCESS       Success
1211   EFI_DEVICE_ERROR  Fail
1212
1213 --*/
1214 ;
1215
1216 EFI_STATUS
1217 SetCtrlDataStructSeg (
1218   IN USB2_HC_DEV     *HcDev
1219   )
1220 /*++
1221
1222 Routine Description:
1223
1224   Set address of first Async schedule Qh
1225
1226 Arguments:
1227
1228   HcDev    - USB2_HC_DEV
1229   QhPtr    - A pointer to first Qh in the Async schedule
1230
1231 Returns:
1232
1233   EFI_SUCCESS       Success
1234   EFI_DEVICE_ERROR  Fail
1235
1236 --*/
1237 ;
1238
1239 EFI_STATUS
1240 SetPortRoutingEhc (
1241   IN USB2_HC_DEV     *HcDev
1242   )
1243 /*++
1244
1245 Routine Description:
1246
1247   Set Ehc port routing bit
1248
1249 Arguments:
1250
1251   HcDev - USB2_HC_DEV
1252
1253 Returns:
1254
1255   EFI_SUCCESS       Success
1256   EFI_DEVICE_ERROR  Fail
1257
1258 --*/
1259 ;
1260
1261 EFI_STATUS
1262 EnablePeriodicSchedule (
1263   IN  USB2_HC_DEV     *HcDev
1264   )
1265 /*++
1266
1267 Routine Description:
1268
1269   Enable periodic schedule
1270
1271 Arguments:
1272
1273   HcDev - USB2_HC_DEV
1274
1275 Returns:
1276
1277   EFI_SUCCESS       Success
1278   EFI_DEVICE_ERROR  Fail
1279
1280 --*/
1281 ;
1282
1283 EFI_STATUS
1284 DisablePeriodicSchedule (
1285   IN  USB2_HC_DEV     *HcDev
1286   )
1287 /*++
1288
1289 Routine Description:
1290
1291   Disable periodic schedule
1292
1293 Arguments:
1294
1295   HcDev - USB2_HC_DEV
1296
1297 Returns:
1298
1299   EFI_SUCCESS       Success
1300   EFI_DEVICE_ERROR  Fail
1301
1302 --*/
1303 ;
1304
1305 EFI_STATUS
1306 EnableAsynchronousSchedule (
1307   IN  USB2_HC_DEV     *HcDev
1308   )
1309 /*++
1310
1311 Routine Description:
1312
1313   Enable asynchrounous schedule
1314
1315 Arguments:
1316
1317   HcDev - USB2_HC_DEV
1318
1319 Returns:
1320
1321   EFI_SUCCESS       Success
1322   EFI_DEVICE_ERROR  Fail
1323
1324 --*/
1325 ;
1326
1327 EFI_STATUS
1328 DisableAsynchronousSchedule (
1329   IN  USB2_HC_DEV     *HcDev
1330   )
1331 /*++
1332
1333 Routine Description:
1334
1335   Disable asynchrounous schedule
1336
1337 Arguments:
1338
1339   HcDev - USB2_HC_DEV
1340
1341 Returns:
1342
1343   EFI_SUCCESS       Success
1344   EFI_DEVICE_ERROR  Fail
1345
1346 --*/
1347 ;
1348
1349 EFI_STATUS
1350 StartScheduleExecution (
1351   IN  USB2_HC_DEV     *HcDev
1352   )
1353 /*++
1354
1355 Routine Description:
1356
1357   Start Ehc schedule execution
1358
1359 Arguments:
1360
1361   HcDev - USB2_HC_DEV
1362
1363 Returns:
1364
1365   EFI_SUCCESS       Success
1366   EFI_DEVICE_ERROR  Fail
1367
1368 --*/
1369 ;
1370
1371 EFI_STATUS
1372 ResetEhc (
1373   IN  USB2_HC_DEV     *HcDev
1374   )
1375 /*++
1376
1377 Routine Description:
1378
1379   Reset Ehc
1380
1381 Arguments:
1382
1383   HcDev - USB2_HC_DEV
1384
1385 Returns:
1386
1387   EFI_SUCCESS       Success
1388   EFI_DEVICE_ERROR  Fail
1389
1390 --*/
1391 ;
1392
1393 EFI_STATUS
1394 ClearEhcAllStatus (
1395   IN  USB2_HC_DEV     *HcDev
1396   )
1397 /*++
1398
1399 Routine Description:
1400
1401   Clear Ehc all status bits
1402
1403 Arguments:
1404
1405   HcDev - USB2_HC_DEV
1406
1407 Returns:
1408
1409   EFI_SUCCESS        Success
1410   EFI_DEVICE_ERROR   Fail
1411
1412 --*/
1413 ;
1414
1415 //
1416 // EhciSched Functions
1417 //
1418 EFI_STATUS
1419 InitialPeriodicFrameList (
1420   IN USB2_HC_DEV      *HcDev,
1421   IN UINTN            Length
1422   )
1423 /*++
1424
1425 Routine Description:
1426
1427   Initialize Periodic Schedule Frame List
1428
1429 Arguments:
1430
1431   HcDev   - USB2_HC_DEV
1432   Length  - Frame List Length
1433
1434 Returns:
1435
1436   EFI_SUCCESS        Success
1437   EFI_DEVICE_ERROR   Fail
1438
1439 --*/
1440 ;
1441
1442 VOID
1443 DeinitialPeriodicFrameList (
1444   IN  USB2_HC_DEV     *HcDev
1445   )
1446 /*++
1447
1448 Routine Description:
1449
1450   Deinitialize Periodic Schedule Frame List
1451
1452 Arguments:
1453
1454   HcDev - USB2_HC_DEV
1455
1456 Returns:
1457
1458   VOID
1459
1460 --*/
1461 ;
1462
1463 EFI_STATUS
1464 CreatePollingTimer (
1465   IN  USB2_HC_DEV      *HcDev,
1466   IN  EFI_EVENT_NOTIFY NotifyFunction
1467   )
1468 /*++
1469
1470 Routine Description:
1471
1472   Create Async Request Polling Timer
1473
1474 Arguments:
1475
1476   HcDev          - USB2_HC_DEV
1477   NotifyFunction - Timer Notify Function
1478
1479 Returns:
1480
1481   EFI_SUCCESS        Success
1482   EFI_DEVICE_ERROR   Fail
1483
1484 --*/
1485 ;
1486
1487 EFI_STATUS
1488 DestoryPollingTimer (
1489   IN  USB2_HC_DEV *HcDev
1490   )
1491 /*++
1492
1493 Routine Description:
1494
1495   Destory Async Request Polling Timer
1496
1497 Arguments:
1498
1499   HcDev - USB2_HC_DEV
1500
1501 Returns:
1502
1503   EFI_SUCCESS        Success
1504   EFI_DEVICE_ERROR   Fail
1505
1506 --*/
1507 ;
1508
1509 EFI_STATUS
1510 StartPollingTimer (
1511   IN  USB2_HC_DEV *HcDev
1512   )
1513 /*++
1514
1515 Routine Description:
1516
1517   Start Async Request Polling Timer
1518
1519 Arguments:
1520
1521   HcDev - USB2_HC_DEV
1522
1523 Returns:
1524
1525   EFI_SUCCESS        Success
1526   EFI_DEVICE_ERROR   Fail
1527
1528 --*/
1529 ;
1530
1531 EFI_STATUS
1532 StopPollingTimer (
1533   IN  USB2_HC_DEV *HcDev
1534   )
1535 /*++
1536
1537 Routine Description:
1538
1539   Stop Async Request Polling Timer
1540
1541 Arguments:
1542
1543   HcDev - USB2_HC_DEV
1544
1545 Returns:
1546
1547   EFI_SUCCESS        Success
1548   EFI_DEVICE_ERROR   Fail
1549
1550 --*/
1551 ;
1552
1553 EFI_STATUS
1554 CreateQh (
1555   IN  USB2_HC_DEV         *HcDev,
1556   IN  UINT8               DeviceAddr,
1557   IN  UINT8               Endpoint,
1558   IN  UINT8               DeviceSpeed,
1559   IN  UINTN               MaxPacketLen,
1560   OUT EHCI_QH_ENTITY      **QhPtrPtr
1561   )
1562 /*++
1563
1564 Routine Description:
1565
1566   Create Qh Structure and Pre-Initialize
1567
1568 Arguments:
1569
1570   HcDev          - USB2_HC_DEV
1571   DeviceAddr     - Address of Device
1572   Endpoint       - Endpoint Number
1573   DeviceSpeed    - Device Speed
1574   MaxPacketLen   - Max Length of one Packet
1575   QhPtrPtr       - A pointer of pointer to Qh for return
1576
1577 Returns:
1578
1579   EFI_SUCCESS       Success
1580   EFI_DEVICE_ERROR  Fail
1581
1582 --*/
1583 ;
1584
1585 EFI_STATUS
1586 CreateControlQh (
1587   IN  USB2_HC_DEV                       *HcDev,
1588   IN  UINT8                             DeviceAddr,
1589   IN  UINT8                             DeviceSpeed,
1590   IN UINTN                              MaxPacketLen,
1591   IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1592   OUT EHCI_QH_ENTITY                    **QhPtrPtr
1593   )
1594 /*++
1595
1596 Routine Description:
1597
1598   Create Qh for Control Transfer
1599
1600 Arguments:
1601
1602   HcDev         - USB2_HC_DEV
1603   DeviceAddr    - Address of Device
1604   DeviceSpeed   - Device Speed
1605   MaxPacketLen  - Max Length of one Packet
1606   Translator    - Translator Transaction for SplitX
1607   QhPtrPtr      - A pointer of pointer to Qh for return
1608
1609 Returns:
1610
1611   EFI_SUCCESS       Success
1612   EFI_DEVICE_ERROR  Fail
1613
1614 --*/
1615 ;
1616
1617 EFI_STATUS
1618 CreateBulkQh (
1619   IN  USB2_HC_DEV                         *HcDev,
1620   IN  UINT8                               DeviceAddr,
1621   IN  UINT8                               EndPointAddr,
1622   IN  UINT8                               DeviceSpeed,
1623   IN  UINT8                               DataToggle,
1624   IN  UINTN                               MaxPacketLen,
1625   IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
1626   OUT EHCI_QH_ENTITY                      **QhPtrPtr
1627   )
1628 /*++
1629
1630 Routine Description:
1631
1632   Create Qh for Bulk Transfer
1633
1634 Arguments:
1635
1636   HcDev         - USB2_HC_DEV
1637   DeviceAddr    - Address of Device
1638   EndPointAddr  - Address of Endpoint
1639   DeviceSpeed   - Device Speed
1640   MaxPacketLen  - Max Length of one Packet
1641   Translator    - Translator Transaction for SplitX
1642   QhPtrPtr      - A pointer of pointer to Qh for return
1643
1644 Returns:
1645
1646   EFI_SUCCESS       Success
1647   EFI_DEVICE_ERROR  Fail
1648
1649 --*/
1650 ;
1651
1652 EFI_STATUS
1653 CreateInterruptQh (
1654   IN  USB2_HC_DEV                        *HcDev,
1655   IN  UINT8                              DeviceAddr,
1656   IN  UINT8                              EndPointAddr,
1657   IN  UINT8                              DeviceSpeed,
1658   IN  UINT8                              DataToggle,
1659   IN  UINTN                              MaxPacketLen,
1660   IN  UINTN                              Interval,
1661   IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1662   OUT EHCI_QH_ENTITY                     **QhPtrPtr
1663   )
1664 /*++
1665
1666 Routine Description:
1667
1668   Create Qh for Control Transfer
1669
1670 Arguments:
1671
1672   HcDev        - USB2_HC_DEV
1673   DeviceAddr   - Address of Device
1674   EndPointAddr - Address of Endpoint
1675   DeviceSpeed  - Device Speed
1676   MaxPacketLen - Max Length of one Packet
1677   Interval     - value of interval
1678   Translator   - Translator Transaction for SplitX
1679   QhPtrPtr     - A pointer of pointer to Qh for return
1680
1681 Returns:
1682
1683   EFI_SUCCESS       Success
1684   EFI_DEVICE_ERROR  Fail
1685
1686 --*/
1687 ;
1688
1689 VOID
1690 DestoryQh (
1691   IN  USB2_HC_DEV        *HcDev,
1692   IN EHCI_QH_ENTITY      *QhPtr
1693   )
1694 /*++
1695
1696 Routine Description:
1697
1698   Destory Qh Structure
1699
1700 Arguments:
1701
1702   HcDev - USB2_HC_DEV
1703   QhPtr - A pointer to Qh
1704
1705 Returns:
1706
1707   VOID
1708
1709 --*/
1710 ;
1711
1712 EFI_STATUS
1713 CreateQtd (
1714   IN  USB2_HC_DEV          *HcDev,
1715   IN  UINT8                *DataPtr,
1716   IN  UINTN                DataLen,
1717   IN  UINT8                PktId,
1718   IN  UINT8                Toggle,
1719   IN  UINT8                QtdStatus,
1720   OUT EHCI_QTD_ENTITY      **QtdPtrPtr
1721   )
1722 /*++
1723
1724 Routine Description:
1725
1726   Create Qtd Structure and Pre-Initialize it
1727
1728 Arguments:
1729
1730   HcDev       - USB2_HC_DEV
1731   DataPtr     - A pointer to user data buffer to transfer
1732   DataLen     - Length of user data to transfer
1733   PktId       - Packet Identification of this Qtd
1734   Toggle      - Data Toggle of this Qtd
1735   QtdStatus   - Default value of status of this Qtd
1736   QtdPtrPtr   - A pointer of pointer to Qtd for return
1737
1738 Returns:
1739
1740   EFI_SUCCESS            Success
1741   EFI_OUT_OF_RESOURCES   Cannot allocate resources
1742
1743 --*/
1744 ;
1745
1746 EFI_STATUS
1747 CreateSetupQtd (
1748   IN  USB2_HC_DEV          *HcDev,
1749   IN  UINT8                *DevReqPtr,
1750   OUT EHCI_QTD_ENTITY      **QtdPtrPtr
1751   )
1752 /*++
1753
1754 Routine Description:
1755
1756   Create Qtd Structure for Setup
1757
1758 Arguments:
1759
1760   HcDev      - USB2_HC_DEV
1761   DevReqPtr  - A pointer to Device Request Data
1762   QtdPtrPtr  - A pointer of pointer to Qtd for return
1763
1764 Returns:
1765
1766   EFI_SUCCESS            Success
1767   EFI_OUT_OF_RESOURCES   Cannot allocate resources
1768
1769 --*/
1770 ;
1771
1772 EFI_STATUS
1773 CreateDataQtd (
1774   IN  USB2_HC_DEV           *HcDev,
1775   IN  UINT8                 *DataPtr,
1776   IN  UINTN                 DataLen,
1777   IN  UINT8                 PktId,
1778   IN  UINT8                 Toggle,
1779   OUT EHCI_QTD_ENTITY       **QtdPtrPtr
1780   )
1781 /*++
1782
1783 Routine Description:
1784
1785   Create Qtd Structure for data
1786
1787 Arguments:
1788
1789   HcDev       - USB2_HC_DEV
1790   DataPtr     - A pointer to user data buffer to transfer
1791   DataLen     - Length of user data to transfer
1792   PktId       - Packet Identification of this Qtd
1793   Toggle      - Data Toggle of this Qtd
1794   QtdPtrPtr   - A pointer of pointer to Qtd for return
1795
1796 Returns:
1797
1798   EFI_SUCCESS            Success
1799   EFI_OUT_OF_RESOURCES   Cannot allocate resources
1800
1801 --*/
1802 ;
1803
1804 EFI_STATUS
1805 CreateStatusQtd (
1806   IN  USB2_HC_DEV           *HcDev,
1807   IN  UINT8                 PktId,
1808   OUT EHCI_QTD_ENTITY       **QtdPtrPtr
1809   )
1810 /*++
1811
1812 Routine Description:
1813
1814   Create Qtd Structure for status
1815
1816 Arguments:
1817
1818   HcDev       - USB2_HC_DEV
1819   PktId       - Packet Identification of this Qtd
1820   QtdPtrPtr   - A pointer of pointer to Qtd for return
1821
1822 Returns:
1823
1824   EFI_SUCCESS            Success
1825   EFI_OUT_OF_RESOURCES   Cannot allocate resources
1826
1827 --*/
1828 ;
1829
1830 EFI_STATUS
1831 CreateAltQtd (
1832   IN  USB2_HC_DEV           *HcDev,
1833   IN  UINT8                 PktId,
1834   OUT EHCI_QTD_ENTITY       **QtdPtrPtr
1835   )
1836 /*++
1837
1838 Routine Description:
1839
1840   Create Qtd Structure for Alternative
1841
1842 Arguments:
1843
1844   HcDev      - USB2_HC_DEV
1845   PktId      - Packet Identification of this Qtd
1846   QtdPtrPtr  - A pointer of pointer to Qtd for return
1847
1848 Returns:
1849
1850   EFI_SUCCESS            Success
1851   EFI_OUT_OF_RESOURCES   Cannot allocate resources
1852
1853 --*/
1854 ;
1855
1856 EFI_STATUS
1857 CreateControlQtds (
1858   IN  USB2_HC_DEV                         *HcDev,
1859   IN UINT8                                DataPktId,
1860   IN UINT8                                *RequestCursor,
1861   IN UINT8                                *DataCursor,
1862   IN UINTN                                DataLen,
1863   IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
1864   OUT EHCI_QTD_ENTITY                     **ControlQtdsHead
1865   )
1866 /*++
1867
1868 Routine Description:
1869
1870   Create Qtds list for Control Transfer
1871
1872 Arguments:
1873
1874   HcDev           - USB2_HC_DEV
1875   DataPktId       - Packet Identification of Data Qtds
1876   RequestCursor   - A pointer to request structure buffer to transfer
1877   DataCursor      - A pointer to user data buffer to transfer
1878   DataLen         - Length of user data to transfer
1879   ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return
1880
1881 Returns:
1882
1883   EFI_SUCCESS       Success
1884   EFI_DEVICE_ERROR  Fail
1885
1886 --*/
1887 ;
1888
1889 EFI_STATUS
1890 CreateBulkOrInterruptQtds (
1891   IN  USB2_HC_DEV                          *HcDev,
1892   IN  UINT8                                PktId,
1893   IN  UINT8                                *DataCursor,
1894   IN  UINTN                                DataLen,
1895   IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR   *Translator,
1896   OUT EHCI_QTD_ENTITY                      **QtdsHead
1897   )
1898 /*++
1899
1900 Routine Description:
1901
1902   Create Qtds list for Bulk or Interrupt Transfer
1903
1904 Arguments:
1905
1906   HcDev        - USB2_HC_DEV
1907   PktId        - Packet Identification of Qtds
1908   DataCursor   - A pointer to user data buffer to transfer
1909   DataLen      - Length of user data to transfer
1910   DataToggle   - Data Toggle to start
1911   Translator   - Translator Transaction for SplitX
1912   QtdsHead     - A pointer of pointer to first Qtd for control tranfer for return
1913
1914 Returns:
1915
1916   EFI_SUCCESS       Success
1917   EFI_DEVICE_ERROR  Fail
1918
1919 --*/
1920 ;
1921
1922 VOID
1923 DestoryQtds (
1924   IN USB2_HC_DEV          *HcDev,
1925   IN EHCI_QTD_ENTITY      *FirstQtdPtr
1926   )
1927 /*++
1928
1929 Routine Description:
1930
1931   Destory all Qtds in the list
1932
1933 Arguments:
1934
1935   HcDev        - USB2_HC_DEV
1936   FirstQtdPtr  - A pointer to first Qtd in the list
1937
1938 Returns:
1939
1940   VOID
1941
1942 --*/
1943 ;
1944
1945 VOID
1946 LinkQtdToQtd (
1947   IN EHCI_QTD_ENTITY     *PreQtdPtr,
1948   IN EHCI_QTD_ENTITY     *QtdPtr
1949   )
1950 /*++
1951
1952 Routine Description:
1953
1954   Link Qtds together
1955
1956 Arguments:
1957
1958   PreQtdPtr  - A pointer to pre Qtd
1959   QtdPtr     - A pointer to next Qtd
1960
1961 Returns:
1962
1963   VOID
1964
1965 --*/
1966 ;
1967
1968 VOID
1969 LinkQtdsToAltQtd (
1970   IN EHCI_QTD_ENTITY     *FirstQtdPtr,
1971   IN EHCI_QTD_ENTITY     *AltQtdPtr
1972   )
1973 /*++
1974
1975 Routine Description:
1976
1977   Link AlterQtds together
1978
1979 Arguments:
1980
1981   FirstQtdPtr - A pointer to first Qtd in the list
1982   AltQtdPtr - A pointer to alternative Qtd
1983
1984 Returns:
1985   VOID
1986
1987 --*/
1988 ;
1989
1990 VOID
1991 LinkQtdToQh (
1992   IN EHCI_QH_ENTITY      *QhPtr,
1993   IN EHCI_QTD_ENTITY     *QtdEntryPtr
1994   )
1995 /*++
1996
1997 Routine Description:
1998
1999   Link Qtds list to Qh
2000
2001 Arguments:
2002
2003   QhPtr   - A pointer to Qh
2004   QtdPtr  - A pointer to first Qtd in the list
2005
2006 Returns:
2007
2008   VOID
2009
2010 --*/
2011 ;
2012
2013 EFI_STATUS
2014 LinkQhToAsyncList (
2015   IN  USB2_HC_DEV       *HcDev,
2016   IN EHCI_QH_ENTITY     *QhPtr
2017   )
2018 /*++
2019
2020 Routine Description:
2021
2022   Link Qh to Async Schedule List
2023
2024 Arguments:
2025
2026   HcDev - USB2_HC_DEV
2027   QhPtr - A pointer to Qh
2028
2029 Returns:
2030
2031   EFI_SUCCESS       Success
2032   EFI_DEVICE_ERROR  Fail
2033
2034 --*/
2035 ;
2036
2037 EFI_STATUS
2038 UnlinkQhFromAsyncList (
2039   IN USB2_HC_DEV         *HcDev,
2040   IN EHCI_QH_ENTITY      *QhPtr
2041   )
2042 /*++
2043
2044 Routine Description:
2045
2046   Unlink Qh from Async Schedule List
2047
2048 Arguments:
2049
2050   HcDev   - USB2_HC_DEV
2051   QhPtr   - A pointer to Qh
2052
2053 Returns:
2054
2055   EFI_SUCCESS       Success
2056   EFI_DEVICE_ERROR  Fail
2057
2058 --*/
2059 ;
2060
2061 VOID
2062 LinkQhToPeriodicList (
2063   IN USB2_HC_DEV        *HcDev,
2064   IN EHCI_QH_ENTITY     *QhPtr
2065   )
2066 /*++
2067
2068 Routine Description:
2069
2070   Link Qh to Periodic Schedule List
2071
2072 Arguments:
2073
2074   HcDev   - USB2_HC_DEV
2075   QhPtr   - A pointer to Qh
2076
2077 Returns:
2078
2079   VOID
2080
2081 --*/
2082 ;
2083
2084 VOID
2085 UnlinkQhFromPeriodicList (
2086   IN USB2_HC_DEV         *HcDev,
2087   IN EHCI_QH_ENTITY      *QhPtr,
2088   IN UINTN                Interval
2089   )
2090 /*++
2091
2092 Routine Description:
2093
2094   Unlink Qh from Periodic Schedule List
2095
2096 Arguments:
2097
2098   HcDev     - USB2_HC_DEV
2099   QhPtr     - A pointer to Qh
2100   Interval  - Interval of this periodic transfer
2101
2102 Returns:
2103
2104   VOID
2105
2106 --*/
2107 ;
2108
2109 VOID
2110 LinkToAsyncReqeust (
2111   IN  USB2_HC_DEV        *HcDev,
2112   IN  EHCI_ASYNC_REQUEST *AsyncRequestPtr
2113   )
2114 /*++
2115
2116 Routine Description:
2117
2118   Llink AsyncRequest Entry to Async Request List
2119
2120 Arguments:
2121
2122   HcDev           - USB2_HC_DEV
2123   AsyncRequestPtr - A pointer to Async Request Entry
2124
2125 Returns:
2126
2127   VOID
2128
2129 --*/
2130 ;
2131
2132 VOID
2133 UnlinkFromAsyncReqeust (
2134   IN  USB2_HC_DEV        *HcDev,
2135   IN  EHCI_ASYNC_REQUEST *AsyncRequestPtr
2136   )
2137 /*++
2138
2139 Routine Description:
2140
2141   Unlink AsyncRequest Entry from Async Request List
2142
2143 Arguments:
2144
2145   HcDev           - USB2_HC_DEV
2146   AsyncRequestPtr - A pointer to Async Request Entry
2147
2148 Returns:
2149
2150   VOID
2151
2152 --*/
2153 ;
2154
2155 UINTN
2156 GetNumberOfQtd (
2157   IN EHCI_QTD_ENTITY    *FirstQtdPtr
2158   )
2159 /*++
2160
2161 Routine Description:
2162
2163   Number of Qtds in the list
2164
2165 Arguments:
2166
2167   FirstQtdPtr - A pointer to first Qtd in the list
2168
2169 Returns:
2170
2171   Number of Qtds in the list
2172
2173 --*/
2174 ;
2175
2176 UINTN
2177 GetNumberOfTransaction (
2178   IN UINTN    SizeOfData,
2179   IN UINTN    SizeOfTransaction
2180   )
2181 /*++
2182
2183 Routine Description:
2184
2185   Number of Transactions in one Qtd
2186
2187 Arguments:
2188
2189   SizeOfData           - Size of one Qtd
2190   SizeOfTransaction    - Size of one Transaction
2191
2192 Returns:
2193
2194   Number of Transactions in this Qtd
2195
2196 --*/
2197 ;
2198
2199 UINTN
2200 GetCapacityOfQtd (
2201   IN UINT8    *BufferCursor
2202   )
2203 /*++
2204
2205 Routine Description:
2206
2207   Get Capacity of Qtd
2208
2209 Arguments:
2210
2211   BufferCursor  - BufferCursor of the Qtd
2212
2213 Returns:
2214
2215   Capacity of Qtd
2216
2217 --*/
2218 ;
2219
2220 UINTN
2221 GetApproxiOfInterval (
2222   IN UINTN  Interval
2223   )
2224 /*++
2225
2226 Routine Description:
2227
2228   Get the approximate value in the 2 index sequence
2229
2230 Arguments:
2231
2232   Interval - the value of interval
2233
2234 Returns:
2235
2236   approximate value of interval in the 2 index sequence
2237
2238 --*/
2239 ;
2240
2241 EHCI_QTD_HW *
2242 GetQtdNextPointer (
2243   IN EHCI_QTD_HW *HwQtdPtr
2244   )
2245 /*++
2246
2247 Routine Description:
2248
2249   Get Qtd next pointer field
2250
2251 Arguments:
2252
2253   HwQtdPtr - A pointer to hardware Qtd structure
2254
2255 Returns:
2256
2257   A pointer to next hardware Qtd structure
2258
2259 --*/
2260 ;
2261
2262 BOOLEAN
2263 IsQtdStatusActive (
2264   IN EHCI_QTD_HW *HwQtdPtr
2265   )
2266 /*++
2267
2268 Routine Description:
2269
2270   Whether Qtd status is active or not
2271
2272 Arguments:
2273
2274   HwQtdPtr - A pointer to hardware Qtd structure
2275
2276 Returns:
2277
2278   TRUE    Active
2279   FALSE   Inactive
2280
2281 --*/
2282 ;
2283
2284 BOOLEAN
2285 IsQtdStatusHalted (
2286   IN EHCI_QTD_HW *HwQtdPtr
2287   )
2288 /*++
2289
2290 Routine Description:
2291
2292   Whether Qtd status is halted or not
2293
2294 Arguments:
2295
2296   HwQtdPtr - A pointer to hardware Qtd structure
2297
2298 Returns:
2299
2300   TRUE    Halted
2301   FALSE   Not halted
2302
2303 --*/
2304 ;
2305
2306 BOOLEAN
2307 IsQtdStatusBufferError (
2308   IN EHCI_QTD_HW *HwQtdPtr
2309   )
2310 /*++
2311
2312 Routine Description:
2313
2314   Whether Qtd status is buffer error or not
2315
2316 Arguments:
2317
2318   HwQtdPtr - A pointer to hardware Qtd structure
2319
2320 Returns:
2321
2322   TRUE    Buffer error
2323   FALSE   No buffer error
2324
2325 --*/
2326 ;
2327
2328 BOOLEAN
2329 IsQtdStatusBabbleError (
2330   IN EHCI_QTD_HW *HwQtdPtr
2331   )
2332 /*++
2333
2334 Routine Description:
2335
2336   Whether Qtd status is babble error or not
2337
2338 Arguments:
2339
2340   HwQtdPtr - A pointer to hardware Qtd structure
2341
2342 Returns:
2343
2344   TRUE    Babble error
2345   FALSE   No babble error
2346
2347 --*/
2348 ;
2349
2350 BOOLEAN
2351 IsQtdStatusTransactionError (
2352   IN EHCI_QTD_HW *HwQtdPtr
2353   )
2354 /*++
2355
2356 Routine Description:
2357
2358   Whether Qtd status is transaction error or not
2359
2360 Arguments:
2361
2362   HwQtdPtr - A pointer to hardware Qtd structure
2363
2364 Returns:
2365
2366   TRUE    Transaction error
2367   FALSE   No transaction error
2368
2369 --*/
2370 ;
2371
2372 BOOLEAN
2373 IsDataInTransfer (
2374   IN  UINT8     EndPointAddress
2375   )
2376 /*++
2377
2378 Routine Description:
2379
2380   Whether is a DataIn direction transfer
2381
2382 Arguments:
2383
2384   EndPointAddress - address of the endpoint
2385
2386 Returns:
2387
2388   TRUE    DataIn
2389   FALSE   DataOut
2390
2391 --*/
2392 ;
2393
2394 EFI_STATUS
2395 MapDataBuffer (
2396   IN  USB2_HC_DEV             *HcDev,
2397   IN  EFI_USB_DATA_DIRECTION  TransferDirection,
2398   IN  OUT VOID                *Data,
2399   IN  OUT UINTN               *DataLength,
2400   OUT UINT8                   *PktId,
2401   OUT UINT8                   **DataCursor,
2402   OUT VOID                    **DataMap
2403   )
2404 /*++
2405
2406 Routine Description:
2407
2408   Map address of user data buffer
2409
2410 Arguments:
2411
2412   HcDev             - USB2_HC_DEV
2413   TransferDirection - direction of transfer
2414   Data              - A pointer to user data buffer
2415   DataLength        - length of user data
2416   PktId             - Packte Identificaion
2417   DataCursor        - mapped address to return
2418   DataMap           - identificaion of this mapping to return
2419
2420 Returns:
2421
2422   EFI_SUCCESS        Success
2423   EFI_DEVICE_ERROR   Fail
2424
2425 --*/
2426 ;
2427
2428 EFI_STATUS
2429 MapRequestBuffer (
2430   IN  USB2_HC_DEV             *HcDev,
2431   IN  OUT VOID                *Request,
2432   OUT UINT8                   **RequestCursor,
2433   OUT VOID                    **RequestMap
2434   )
2435 /*++
2436
2437 Routine Description:
2438
2439   Map address of request structure buffer
2440
2441 Arguments:
2442
2443   HcDev           - USB2_HC_DEV
2444   Request         - A pointer to request structure
2445   RequestCursor   - Mapped address of request structure to return
2446   RequestMap      - Identificaion of this mapping to return
2447
2448 Returns:
2449
2450   EFI_SUCCESS        Success
2451   EFI_DEVICE_ERROR   Fail
2452
2453 --*/
2454 ;
2455
2456 VOID
2457 SetQtdBufferPointer (
2458   IN EHCI_QTD_HW *QtdHwPtr,
2459   IN VOID        *DataPtr,
2460   IN UINTN       DataLen
2461   )
2462 /*++
2463
2464 Routine Description:
2465
2466   Set data buffer pointers in Qtd
2467
2468 Arguments:
2469
2470   QtdHwPtr  - A pointer to Qtd hardware structure
2471   DataPtr   - A pointer to user data buffer
2472   DataLen   - Length of the user data buffer
2473
2474 Returns:
2475
2476   VOID
2477
2478 --*/
2479 ;
2480
2481 EHCI_QTD_HW *
2482 GetQtdAlternateNextPointer (
2483   IN EHCI_QTD_HW *HwQtdPtr
2484   )
2485 /*++
2486
2487 Routine Description:
2488
2489   Get Qtd alternate next pointer field
2490
2491 Arguments:
2492
2493   HwQtdPtr - A pointer to hardware Qtd structure
2494
2495 Returns:
2496
2497   A pointer to hardware alternate Qtd
2498
2499 --*/
2500 ;
2501
2502 VOID
2503 ZeroOutQhOverlay (
2504   IN EHCI_QH_ENTITY *QhPtr
2505   )
2506 /*++
2507
2508 Routine Description:
2509
2510   Zero out the fields in Qh structure
2511
2512 Arguments:
2513
2514   QhPtr - A pointer to Qh structure
2515
2516 Returns:
2517
2518   VOID
2519
2520 --*/
2521 ;
2522
2523 VOID
2524 UpdateAsyncRequestTransfer (
2525   IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,
2526   IN UINT32             TransferResult,
2527   IN UINTN              ErrTDPos
2528   )
2529 /*++
2530
2531 Routine Description:
2532
2533   Update asynchronous request transfer
2534
2535 Arguments:
2536
2537   AsyncRequestPtr  - A pointer to async request
2538   TransferResult   - transfer result
2539   ErrQtdPos        - postion of error Qtd
2540
2541 Returns:
2542
2543   VOID
2544
2545 --*/
2546 ;
2547
2548
2549 EFI_STATUS
2550 DeleteAsyncRequestTransfer (
2551   IN  USB2_HC_DEV     *HcDev,
2552   IN  UINT8           DeviceAddress,
2553   IN  UINT8           EndPointAddress,
2554   OUT UINT8           *DataToggle
2555   )
2556 /*++
2557
2558 Routine Description:
2559
2560   Delete all asynchronous request transfer
2561
2562 Arguments:
2563
2564   HcDev           - USB2_HC_DEV
2565   DeviceAddress   - address of usb device
2566   EndPointAddress - address of endpoint
2567   DataToggle      - stored data toggle
2568
2569 Returns:
2570
2571   EFI_SUCCESS        Success
2572   EFI_DEVICE_ERROR   Fail
2573
2574 --*/
2575 ;
2576
2577 VOID
2578 CleanUpAllAsyncRequestTransfer (
2579   IN  USB2_HC_DEV *HcDev
2580   )
2581 /*++
2582
2583 Routine Description:
2584
2585   Clean up all asynchronous request transfer
2586
2587 Arguments:
2588
2589   HcDev - USB2_HC_DEV
2590
2591 Returns:
2592   VOID
2593
2594 --*/
2595 ;
2596
2597 EFI_STATUS
2598 ExecuteTransfer (
2599   IN  USB2_HC_DEV         *HcDev,
2600   IN BOOLEAN              IsControl,
2601   IN  EHCI_QH_ENTITY      *QhPtr,
2602   IN OUT UINTN            *ActualLen,
2603   OUT UINT8               *DataToggle,
2604   IN  UINTN               TimeOut,
2605   OUT UINT32              *TransferResult
2606   )
2607 /*++
2608
2609 Routine Description:
2610
2611   Execute Bulk or SyncInterrupt Transfer
2612
2613 Arguments:
2614
2615   HcDev            - USB2_HC_DEV
2616   IsControl        - Is control transfer or not
2617   QhPtr            - A pointer to Qh
2618   ActualLen        - Actual transfered Len
2619   DataToggle       - Data Toggle
2620   TimeOut          - TimeOut threshold
2621   TransferResult   - Transfer result
2622
2623 Returns:
2624
2625   EFI_SUCCESS        Sucess
2626   EFI_DEVICE_ERROR   Error
2627
2628 --*/
2629 ;
2630
2631 BOOLEAN
2632 CheckQtdsTransferResult (
2633   IN BOOLEAN             IsControl,
2634   IN  EHCI_QH_ENTITY     *QhPtr,
2635   OUT UINT32             *Result,
2636   OUT UINTN              *ErrQtdPos,
2637   OUT UINTN              *ActualLen
2638   )
2639 /*++
2640
2641 Routine Description:
2642
2643   Check transfer result of Qtds
2644
2645 Arguments:
2646
2647   IsControl     - Is control transfer or not
2648   QhPtr         - A pointer to Qh
2649   Result        - Transfer result
2650   ErrQtdPos     - Error TD Position
2651   ActualLen     - Actual Transfer Size
2652
2653 Returns:
2654
2655   TRUE    Qtds finished
2656   FALSE   Not finish
2657
2658 --*/
2659 ;
2660
2661 EFI_STATUS
2662 AsyncRequestMoniter (
2663   IN EFI_EVENT     Event,
2664   IN VOID          *Context
2665   )
2666 /*++
2667
2668 Routine Description:
2669
2670   Interrupt transfer periodic check handler
2671
2672 Arguments:
2673
2674   Event     - Interrupt event
2675   Context   - Pointer to USB2_HC_DEV
2676
2677 Returns:
2678
2679   EFI_SUCCESS        Success
2680   EFI_DEVICE_ERROR   Fail
2681
2682 --*/
2683 ;
2684
2685 VOID
2686 ClearLegacySupport (
2687   IN USB2_HC_DEV     *HcDev
2688   );
2689
2690 VOID
2691 HostReset (
2692   IN USB2_HC_DEV    *HcDev
2693   );
2694
2695 VOID
2696 DumpEHCIPortsStatus (
2697   IN USB2_HC_DEV    *HcDev
2698   );
2699 #endif