3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 PciEnumeratorSupport.c
25 #include "PciEnumeratorSupport.h"
26 #include "PciCommand.h"
31 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
41 This routine is used to check whether the pci device is present
50 // TODO: PciRootBridgeIo - add argument and description to function comment
51 // TODO: Pci - add argument and description to function comment
52 // TODO: Bus - add argument and description to function comment
53 // TODO: Device - add argument and description to function comment
54 // TODO: Func - add argument and description to function comment
55 // TODO: EFI_SUCCESS - add return value to function comment
56 // TODO: EFI_NOT_FOUND - add return value to function comment
62 // Create PCI address map in terms of Bus, Device and Func
64 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
67 // Read the Vendor Id register
69 Status
= PciRootBridgeIo
->Pci
.Read (
77 if (!EFI_ERROR (Status
) && (Pci
->Hdr
).VendorId
!= 0xffff) {
80 // Read the entire config header for the device
83 Status
= PciRootBridgeIo
->Pci
.Read (
87 sizeof (PCI_TYPE00
) / sizeof (UINT32
),
98 PciPciDeviceInfoCollector (
99 IN PCI_IO_DEVICE
*Bridge
,
113 // TODO: Bridge - add argument and description to function comment
114 // TODO: StartBusNumber - add argument and description to function comment
115 // TODO: EFI_SUCCESS - add return value to function comment
122 PCI_IO_DEVICE
*PciIoDevice
;
123 EFI_PCI_IO_PROTOCOL
*PciIo
;
125 Status
= EFI_SUCCESS
;
128 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
130 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
133 // Check to see whether PCI device is present
136 Status
= PciDevicePresent (
137 Bridge
->PciRootBridgeIo
,
139 (UINT8
) StartBusNumber
,
144 if (!EFI_ERROR (Status
)) {
147 // Call back to host bridge function
149 PreprocessController (Bridge
, (UINT8
) StartBusNumber
, Device
, Func
, EfiPciBeforeResourceCollection
);
152 // Collect all the information about the PCI device discovered
154 Status
= PciSearchDevice (
157 (UINT8
) StartBusNumber
,
164 // Recursively scan PCI busses on the other side of PCI-PCI bridges
168 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
171 // If it is PPB, we need to get the secondary bus to continue the enumeration
173 PciIo
= &(PciIoDevice
->PciIo
);
175 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x19, 1, &SecBus
);
177 if (EFI_ERROR (Status
)) {
182 // Get resource padding for PPB
184 GetResourcePaddingPpb (PciIoDevice
);
187 // Deep enumerate the next level bus
189 Status
= PciPciDeviceInfoCollector (
196 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
199 // Skip sub functions, this is not a multi function device
213 IN PCI_IO_DEVICE
*Bridge
,
218 OUT PCI_IO_DEVICE
**PciDevice
224 Search required device.
228 Bridge - A pointer to the PCI_IO_DEVICE.
229 Pci - A pointer to the PCI_TYPE00.
231 Device - Device number.
232 Func - Function number.
233 PciDevice - The Required pci device.
240 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
241 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
242 // TODO: EFI_SUCCESS - add return value to function comment
244 PCI_IO_DEVICE
*PciIoDevice
;
248 if (!IS_PCI_BRIDGE (Pci
)) {
250 if (IS_CARDBUS_BRIDGE (Pci
)) {
251 PciIoDevice
= GatherP2CInfo (
258 if (gFullEnumeration
) {
259 InitializeP2C (PciIoDevice
);
264 // Create private data for Pci Device
266 PciIoDevice
= GatherDeviceInfo (
279 // Create private data for PPB
281 PciIoDevice
= GatherPpbInfo (
290 // Special initialization for PPB including making the PPB quiet
292 if (gFullEnumeration
) {
293 InitializePpb (PciIoDevice
);
298 return EFI_OUT_OF_RESOURCES
;
302 // Update the bar information for this PCI device so as to support some specific device
304 UpdatePciInfo (PciIoDevice
);
306 if (PciIoDevice
->DevicePath
== NULL
) {
307 return EFI_OUT_OF_RESOURCES
;
311 // Detect this function has option rom
313 if (gFullEnumeration
) {
315 if (!IS_CARDBUS_BRIDGE (Pci
)) {
317 GetOpRomInfo (PciIoDevice
);
321 ResetPowerManagementFeature (PciIoDevice
);
326 // Insert it into a global tree for future reference
328 InsertPciDevice (Bridge
, PciIoDevice
);
331 // Determine PCI device attributes
334 if (PciDevice
!= NULL
) {
335 *PciDevice
= PciIoDevice
;
343 IN PCI_IO_DEVICE
*Bridge
,
360 // TODO: Bridge - add argument and description to function comment
361 // TODO: Pci - add argument and description to function comment
362 // TODO: Bus - add argument and description to function comment
363 // TODO: Device - add argument and description to function comment
364 // TODO: Func - add argument and description to function comment
368 PCI_IO_DEVICE
*PciIoDevice
;
369 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
371 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
372 PciIoDevice
= CreatePciIoDevice (
385 // Create a device path for this PCI device and store it into its private data
387 CreatePciDevicePath (
393 // If it is a full enumeration, disconnect the device in advance
395 if (gFullEnumeration
) {
397 PciDisableCommandRegister (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
402 // Start to parse the bars
404 for (Offset
= 0x10, BarIndex
= 0; Offset
<= 0x24; BarIndex
++) {
405 Offset
= PciParseBar (PciIoDevice
, Offset
, BarIndex
);
413 IN PCI_IO_DEVICE
*Bridge
,
430 // TODO: Bridge - add argument and description to function comment
431 // TODO: Pci - add argument and description to function comment
432 // TODO: Bus - add argument and description to function comment
433 // TODO: Device - add argument and description to function comment
434 // TODO: Func - add argument and description to function comment
436 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
437 PCI_IO_DEVICE
*PciIoDevice
;
440 EFI_PCI_IO_PROTOCOL
*PciIo
;
443 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
444 PciIoDevice
= CreatePciIoDevice (
457 // Create a device path for this PCI device and store it into its private data
459 CreatePciDevicePath (
464 if (gFullEnumeration
) {
465 PciDisableCommandRegister (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
468 // Initalize the bridge control register
470 PciDisableBridgeControlRegister (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED
);
475 // PPB can have two BARs
477 if (PciParseBar (PciIoDevice
, 0x10, PPB_BAR_0
) == 0x14) {
481 PciParseBar (PciIoDevice
, 0x14, PPB_BAR_1
);
484 PciIo
= &PciIoDevice
->PciIo
;
487 // Test whether it support 32 decode or not
489 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
490 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
491 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
492 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
496 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
498 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
502 Status
= BarExisted (
510 // test if it supports 64 memory or not
512 if (!EFI_ERROR (Status
)) {
514 Status
= BarExisted (
521 if (!EFI_ERROR (Status
)) {
522 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
523 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
525 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
530 // Memory 32 code is required for ppb
532 PciIoDevice
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
534 GetResourcePaddingPpb (PciIoDevice
);
541 IN PCI_IO_DEVICE
*Bridge
,
558 // TODO: Bridge - add argument and description to function comment
559 // TODO: Pci - add argument and description to function comment
560 // TODO: Bus - add argument and description to function comment
561 // TODO: Device - add argument and description to function comment
562 // TODO: Func - add argument and description to function comment
564 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
565 PCI_IO_DEVICE
*PciIoDevice
;
567 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
568 PciIoDevice
= CreatePciIoDevice (
581 // Create a device path for this PCI device and store it into its private data
583 CreatePciDevicePath (
588 if (gFullEnumeration
) {
589 PciDisableCommandRegister (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
592 // Initalize the bridge control register
594 PciDisableBridgeControlRegister (PciIoDevice
, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED
);
598 // P2C only has one bar that is in 0x10
600 PciParseBar (PciIoDevice
, 0x10, P2C_BAR_0
);
603 // Read PciBar information from the bar register
605 GetBackPcCardBar (PciIoDevice
);
606 PciIoDevice
->Decodes
= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
|
607 EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
|
608 EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
613 EFI_DEVICE_PATH_PROTOCOL
*
614 CreatePciDevicePath (
615 IN EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
,
616 IN PCI_IO_DEVICE
*PciIoDevice
629 // TODO: ParentDevicePath - add argument and description to function comment
630 // TODO: PciIoDevice - add argument and description to function comment
633 PCI_DEVICE_PATH PciNode
;
636 // Create PCI device path
638 PciNode
.Header
.Type
= HARDWARE_DEVICE_PATH
;
639 PciNode
.Header
.SubType
= HW_PCI_DP
;
640 SetDevicePathNodeLength (&PciNode
.Header
, sizeof (PciNode
));
642 PciNode
.Device
= PciIoDevice
->DeviceNumber
;
643 PciNode
.Function
= PciIoDevice
->FunctionNumber
;
644 PciIoDevice
->DevicePath
= AppendDevicePathNode (ParentDevicePath
, &PciNode
.Header
);
646 return PciIoDevice
->DevicePath
;
651 IN PCI_IO_DEVICE
*PciIoDevice
,
653 OUT UINT32
*BarLengthValue
,
654 OUT UINT32
*OriginalBarValue
660 Check the bar is existed or not.
664 PciIoDevice - A pointer to the PCI_IO_DEVICE.
666 BarLengthValue - The bar length value.
667 OriginalBarValue - The original bar value.
671 EFI_NOT_FOUND - The bar don't exist.
672 EFI_SUCCESS - The bar exist.
676 EFI_PCI_IO_PROTOCOL
*PciIo
;
677 UINT32 OriginalValue
;
681 PciIo
= &PciIoDevice
->PciIo
;
684 // Preserve the original value
687 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
690 // Raise TPL to high level to disable timer interrupt while the BAR is probed
692 OldTpl
= gBS
->RaiseTPL (EFI_TPL_HIGH_LEVEL
);
694 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &gAllOne
);
695 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &Value
);
698 // Write back the original value
700 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
703 // Restore TPL to its original level
705 gBS
->RestoreTPL (OldTpl
);
707 if (BarLengthValue
!= NULL
) {
708 *BarLengthValue
= Value
;
711 if (OriginalBarValue
!= NULL
) {
712 *OriginalBarValue
= OriginalValue
;
716 return EFI_NOT_FOUND
;
723 PciTestSupportedAttribute (
724 IN PCI_IO_DEVICE
*PciIoDevice
,
726 IN UINT16
*BridgeControl
,
727 IN UINT16
*OldCommand
,
728 IN UINT16
*OldBridgeControl
741 // TODO: PciIoDevice - add argument and description to function comment
742 // TODO: Command - add argument and description to function comment
743 // TODO: BridgeControl - add argument and description to function comment
744 // TODO: OldCommand - add argument and description to function comment
745 // TODO: OldBridgeControl - add argument and description to function comment
746 // TODO: EFI_SUCCESS - add return value to function comment
751 // Preserve the original value
753 PciReadCommandRegister (PciIoDevice
, OldCommand
);
756 // Raise TPL to high level to disable timer interrupt while the BAR is probed
758 OldTpl
= gBS
->RaiseTPL (EFI_TPL_HIGH_LEVEL
);
760 PciSetCommandRegister (PciIoDevice
, *Command
);
761 PciReadCommandRegister (PciIoDevice
, Command
);
764 // Write back the original value
766 PciSetCommandRegister (PciIoDevice
, *OldCommand
);
769 // Restore TPL to its original level
771 gBS
->RestoreTPL (OldTpl
);
773 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
776 // Preserve the original value
778 PciReadBridgeControlRegister (PciIoDevice
, OldBridgeControl
);
781 // Raise TPL to high level to disable timer interrupt while the BAR is probed
783 OldTpl
= gBS
->RaiseTPL (EFI_TPL_HIGH_LEVEL
);
785 PciSetBridgeControlRegister (PciIoDevice
, *BridgeControl
);
786 PciReadBridgeControlRegister (PciIoDevice
, BridgeControl
);
789 // Write back the original value
791 PciSetBridgeControlRegister (PciIoDevice
, *OldBridgeControl
);
794 // Restore TPL to its original level
796 gBS
->RestoreTPL (OldTpl
);
799 *OldBridgeControl
= 0;
807 PciSetDeviceAttribute (
808 IN PCI_IO_DEVICE
*PciIoDevice
,
810 IN UINT16 BridgeControl
,
816 Set the supported or current attributes of a PCI device
819 PciIoDevice - Structure pointer for PCI device.
820 Command - Command register value.
821 BridgeControl - Bridge control value for PPB or P2C.
822 Option - Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
839 EFI_SUCCESS Always success
848 if (Command
& EFI_PCI_COMMAND_IO_SPACE
) {
849 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IO
;
852 if (Command
& EFI_PCI_COMMAND_MEMORY_SPACE
) {
853 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY
;
856 if (Command
& EFI_PCI_COMMAND_BUS_MASTER
) {
857 Attributes
|= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
;
860 if (Command
& EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
) {
861 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
864 if (BridgeControl
& EFI_PCI_BRIDGE_CONTROL_ISA
) {
865 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
868 if (BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA
) {
869 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
870 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
871 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
874 if (BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA_16
) {
875 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
;
876 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
;
879 if (Option
== EFI_SET_SUPPORTS
) {
881 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE
|
882 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED
|
883 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE
|
884 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
885 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
886 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
;
888 if (Attributes
& EFI_PCI_IO_ATTRIBUTE_IO
) {
889 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO
;
890 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
893 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
895 // For bridge, it should support IDE attributes
897 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
898 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
901 if (IS_PCI_IDE (&PciIoDevice
->Pci
)) {
902 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
903 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
906 if (IS_PCI_VGA (&PciIoDevice
->Pci
)) {
907 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
908 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
912 PciIoDevice
->Supports
= Attributes
;
913 PciIoDevice
->Supports
&= ( (PciIoDevice
->Parent
->Supports
) | \
914 EFI_PCI_IO_ATTRIBUTE_IO
| EFI_PCI_IO_ATTRIBUTE_MEMORY
| \
915 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
);
918 PciIoDevice
->Attributes
= Attributes
;
925 GetFastBackToBackSupport (
926 IN PCI_IO_DEVICE
*PciIoDevice
,
933 Determine if the device can support Fast Back to Back attribute
942 // TODO: PciIoDevice - add argument and description to function comment
943 // TODO: StatusIndex - add argument and description to function comment
944 // TODO: EFI_UNSUPPORTED - add return value to function comment
945 // TODO: EFI_SUCCESS - add return value to function comment
946 // TODO: EFI_UNSUPPORTED - add return value to function comment
948 EFI_PCI_IO_PROTOCOL
*PciIo
;
950 UINT32 StatusRegister
;
953 // Read the status register
955 PciIo
= &PciIoDevice
->PciIo
;
956 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint16
, StatusIndex
, 1, &StatusRegister
);
957 if (EFI_ERROR (Status
)) {
958 return EFI_UNSUPPORTED
;
962 // Check the Fast B2B bit
964 if (StatusRegister
& EFI_PCI_FAST_BACK_TO_BACK_CAPABLE
) {
967 return EFI_UNSUPPORTED
;
973 ProcessOptionRomLight (
974 IN PCI_IO_DEVICE
*PciIoDevice
980 Process the option ROM for all the children of the specified parent PCI device.
981 It can only be used after the first full Option ROM process.
990 // TODO: PciIoDevice - add argument and description to function comment
991 // TODO: EFI_SUCCESS - add return value to function comment
994 LIST_ENTRY
*CurrentLink
;
997 // For RootBridge, PPB , P2C, go recursively to traverse all its children
999 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1000 while (CurrentLink
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1002 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1004 if (!IsListEmpty (&Temp
->ChildList
)) {
1005 ProcessOptionRomLight (Temp
);
1008 PciRomGetImageMapping (Temp
);
1009 CurrentLink
= CurrentLink
->ForwardLink
;
1016 DetermineDeviceAttribute (
1017 IN PCI_IO_DEVICE
*PciIoDevice
1021 Routine Description:
1023 Determine the related attributes of all devices under a Root Bridge
1032 // TODO: PciIoDevice - add argument and description to function comment
1033 // TODO: EFI_SUCCESS - add return value to function comment
1036 UINT16 BridgeControl
;
1038 UINT16 OldBridgeControl
;
1039 BOOLEAN FastB2BSupport
;
1043 EFI_PCI_IO_PROTOCOL *PciIo;
1045 PCI_IO_DEVICE
*Temp
;
1046 LIST_ENTRY
*CurrentLink
;
1050 // For Root Bridge, just copy it by RootBridgeIo proctocol
1051 // so as to keep consistent with the actual attribute
1053 if (!PciIoDevice
->Parent
) {
1054 Status
= PciIoDevice
->PciRootBridgeIo
->GetAttributes (
1055 PciIoDevice
->PciRootBridgeIo
,
1056 &PciIoDevice
->Supports
,
1057 &PciIoDevice
->Attributes
1059 if (EFI_ERROR (Status
)) {
1065 // Set the attributes to be checked for common PCI devices and PPB or P2C
1066 // Since some devices only support part of them, it is better to set the
1067 // attribute according to its command or bridge control register
1069 Command
= EFI_PCI_COMMAND_IO_SPACE
|
1070 EFI_PCI_COMMAND_MEMORY_SPACE
|
1071 EFI_PCI_COMMAND_BUS_MASTER
|
1072 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
;
1074 BridgeControl
= EFI_PCI_BRIDGE_CONTROL_ISA
| EFI_PCI_BRIDGE_CONTROL_VGA
| EFI_PCI_BRIDGE_CONTROL_VGA_16
;
1077 // Test whether the device can support attributes above
1079 PciTestSupportedAttribute (PciIoDevice
, &Command
, &BridgeControl
, &OldCommand
, &OldBridgeControl
);
1082 // Set the supported attributes for specified PCI device
1084 PciSetDeviceAttribute (PciIoDevice
, Command
, BridgeControl
, EFI_SET_SUPPORTS
);
1087 // Set the current attributes for specified PCI device
1089 PciSetDeviceAttribute (PciIoDevice
, OldCommand
, OldBridgeControl
, EFI_SET_ATTRIBUTES
);
1092 // Enable other supported attributes but not defined in PCI_IO_PROTOCOL
1094 PciEnableCommandRegister (PciIoDevice
, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE
);
1097 // Enable IDE native mode
1100 if (IS_PCI_IDE(&PciIoDevice->Pci)) {
1102 PciIo = &PciIoDevice->PciIo;
1113 // Set native mode if it can be supported
1115 IdePI |= (((IdePI & 0x0F) >> 1) & 0x05);
1129 FastB2BSupport
= TRUE
;
1132 // P2C can not support FB2B on the secondary side
1134 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1135 FastB2BSupport
= FALSE
;
1139 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1141 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1142 while (CurrentLink
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1144 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1145 Status
= DetermineDeviceAttribute (Temp
);
1146 if (EFI_ERROR (Status
)) {
1150 // Detect Fast Bact to Bact support for the device under the bridge
1152 Status
= GetFastBackToBackSupport (Temp
, PCI_PRIMARY_STATUS_OFFSET
);
1153 if (FastB2BSupport
&& EFI_ERROR (Status
)) {
1154 FastB2BSupport
= FALSE
;
1157 CurrentLink
= CurrentLink
->ForwardLink
;
1160 // Set or clear Fast Back to Back bit for the whole bridge
1162 if (!IsListEmpty (&PciIoDevice
->ChildList
)) {
1164 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
1166 Status
= GetFastBackToBackSupport (PciIoDevice
, PCI_BRIDGE_STATUS_REGISTER_OFFSET
);
1168 if (EFI_ERROR (Status
) || (!FastB2BSupport
)) {
1169 FastB2BSupport
= FALSE
;
1170 PciDisableBridgeControlRegister (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1172 PciEnableBridgeControlRegister (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1176 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1177 while (CurrentLink
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1178 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1179 if (FastB2BSupport
) {
1180 PciEnableCommandRegister (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1182 PciDisableCommandRegister (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1185 CurrentLink
= CurrentLink
->ForwardLink
;
1189 // End for IsListEmpty
1196 IN PCI_IO_DEVICE
*PciIoDevice
1200 Routine Description:
1202 This routine is used to update the bar information for those incompatible PCI device
1211 // TODO: PciIoDevice - add argument and description to function comment
1212 // TODO: EFI_UNSUPPORTED - add return value to function comment
1218 VOID
*Configuration
;
1219 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1221 Configuration
= NULL
;
1224 // It can only be supported after the Incompatible PCI Device
1225 // Support Protocol has been installed
1227 if (gEfiIncompatiblePciDeviceSupport
== NULL
) {
1229 Status
= gBS
->LocateProtocol (
1230 &gEfiIncompatiblePciDeviceSupportProtocolGuid
,
1232 (VOID
**) &gEfiIncompatiblePciDeviceSupport
1234 if (EFI_ERROR (Status
)) {
1235 return EFI_UNSUPPORTED
;
1240 // Check whether the device belongs to incompatible devices or not
1241 // If it is , then get its special requirement in the ACPI table
1243 Status
= gEfiIncompatiblePciDeviceSupport
->CheckDevice (
1244 gEfiIncompatiblePciDeviceSupport
,
1245 PciIoDevice
->Pci
.Hdr
.VendorId
,
1246 PciIoDevice
->Pci
.Hdr
.DeviceId
,
1247 PciIoDevice
->Pci
.Hdr
.RevisionID
,
1248 PciIoDevice
->Pci
.Device
.SubsystemVendorID
,
1249 PciIoDevice
->Pci
.Device
.SubsystemID
,
1253 if (EFI_ERROR (Status
)) {
1258 // Update PCI device information from the ACPI table
1260 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1262 while (Ptr
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
1264 if (Ptr
->Desc
!= ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1266 // The format is not support
1271 BarIndex
= (UINTN
) Ptr
->AddrTranslationOffset
;
1272 BarEndIndex
= BarIndex
;
1275 // Update all the bars in the device
1277 if (BarIndex
== PCI_BAR_ALL
) {
1279 BarEndIndex
= PCI_MAX_BAR
- 1;
1282 if (BarIndex
>= PCI_MAX_BAR
) {
1287 for (; BarIndex
<= BarEndIndex
; BarIndex
++) {
1289 switch (Ptr
->ResType
) {
1290 case ACPI_ADDRESS_SPACE_TYPE_MEM
:
1293 // Make sure the bar is memory type
1295 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeMem
)) {
1300 case ACPI_ADDRESS_SPACE_TYPE_IO
:
1303 // Make sure the bar is IO type
1305 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeIo
)) {
1314 // Update the new alignment for the device
1316 SetNewAlign (&(PciIoDevice
->PciBar
[BarIndex
].Alignment
), Ptr
->AddrRangeMax
);
1319 // Update the new length for the device
1321 if (Ptr
->AddrLen
!= PCI_BAR_NOCHANGE
) {
1322 PciIoDevice
->PciBar
[BarIndex
].Length
= Ptr
->AddrLen
;
1330 gBS
->FreePool (Configuration
);
1337 IN UINT64
*Alignment
,
1338 IN UINT64 NewAlignment
1342 Routine Description:
1344 This routine will update the alignment with the new alignment
1353 // TODO: Alignment - add argument and description to function comment
1354 // TODO: NewAlignment - add argument and description to function comment
1356 UINT64 OldAlignment
;
1360 // The new alignment is the same as the original,
1363 if (NewAlignment
== PCI_BAR_OLD_ALIGN
) {
1367 // Check the validity of the parameter
1369 if (NewAlignment
!= PCI_BAR_EVEN_ALIGN
&&
1370 NewAlignment
!= PCI_BAR_SQUAD_ALIGN
&&
1371 NewAlignment
!= PCI_BAR_DQUAD_ALIGN
) {
1372 *Alignment
= NewAlignment
;
1376 OldAlignment
= (*Alignment
) + 1;
1380 // Get the first non-zero hex value of the length
1382 while ((OldAlignment
& 0x0F) == 0x00) {
1383 OldAlignment
= RShiftU64 (OldAlignment
, 4);
1388 // Adjust the alignment to even, quad or double quad boundary
1390 if (NewAlignment
== PCI_BAR_EVEN_ALIGN
) {
1391 if (OldAlignment
& 0x01) {
1392 OldAlignment
= OldAlignment
+ 2 - (OldAlignment
& 0x01);
1394 } else if (NewAlignment
== PCI_BAR_SQUAD_ALIGN
) {
1395 if (OldAlignment
& 0x03) {
1396 OldAlignment
= OldAlignment
+ 4 - (OldAlignment
& 0x03);
1398 } else if (NewAlignment
== PCI_BAR_DQUAD_ALIGN
) {
1399 if (OldAlignment
& 0x07) {
1400 OldAlignment
= OldAlignment
+ 8 - (OldAlignment
& 0x07);
1405 // Update the old value
1407 NewAlignment
= LShiftU64 (OldAlignment
, ShiftBit
) - 1;
1408 *Alignment
= NewAlignment
;
1415 IN PCI_IO_DEVICE
*PciIoDevice
,
1421 Routine Description:
1430 // TODO: PciIoDevice - add argument and description to function comment
1431 // TODO: Offset - add argument and description to function comment
1432 // TODO: BarIndex - add argument and description to function comment
1436 UINT32 OriginalValue
;
1446 Status
= BarExisted (
1453 if (EFI_ERROR (Status
)) {
1454 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1455 PciIoDevice
->PciBar
[BarIndex
].Length
= 0;
1456 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1459 // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
1461 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1465 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1472 if (Value
& 0xFFFF0000) {
1476 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo32
;
1477 PciIoDevice
->PciBar
[BarIndex
].Length
= ((~(Value
& Mask
)) + 1);
1478 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1484 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo16
;
1485 PciIoDevice
->PciBar
[BarIndex
].Length
= 0x0000FFFF & ((~(Value
& Mask
)) + 1);
1486 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1490 // Workaround. Some platforms inplement IO bar with 0 length
1491 // Need to treat it as no-bar
1493 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1494 PciIoDevice
->PciBar
[BarIndex
].BarType
= 0;
1497 PciIoDevice
->PciBar
[BarIndex
].Prefetchable
= FALSE
;
1498 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1504 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1506 switch (Value
& 0x07) {
1509 //memory space; anywhere in 32 bit address space
1513 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1515 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1518 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1519 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1524 // memory space; anywhere in 64 bit address space
1528 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1530 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1534 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1535 // is regarded as an extension for the first bar. As a result
1536 // the sizing will be conducted on combined 64 bit value
1537 // Here just store the masked first 32bit value for future size
1540 PciIoDevice
->PciBar
[BarIndex
].Length
= Value
& Mask
;
1541 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1544 // Increment the offset to point to next DWORD
1548 Status
= BarExisted (
1555 if (EFI_ERROR (Status
)) {
1560 // Fix the length to support some spefic 64 bit BAR
1564 for (Data
= Value
; Data
!= 0; Data
>>= 1) {
1567 Value
|= ((UINT32
)(-1) << Index
);
1570 // Calculate the size of 64bit bar
1572 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1574 PciIoDevice
->PciBar
[BarIndex
].Length
= PciIoDevice
->PciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1575 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(PciIoDevice
->PciBar
[BarIndex
].Length
)) + 1;
1576 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1584 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1585 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1586 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1593 // Check the length again so as to keep compatible with some special bars
1595 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1596 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1597 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1598 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1602 // Increment number of bar
1608 InitializePciDevice (
1609 IN PCI_IO_DEVICE
*PciIoDevice
1613 Routine Description:
1615 This routine is used to initialize the bar of a PCI device
1616 It can be called typically when a device is going to be rejected
1625 // TODO: PciIoDevice - add argument and description to function comment
1626 // TODO: EFI_SUCCESS - add return value to function comment
1628 EFI_PCI_IO_PROTOCOL
*PciIo
;
1631 PciIo
= &(PciIoDevice
->PciIo
);
1634 // Put all the resource apertures
1635 // Resource base is set to all ones so as to indicate its resource
1636 // has not been alloacted
1638 for (Offset
= 0x10; Offset
<= 0x24; Offset
+= sizeof (UINT32
)) {
1639 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, Offset
, 1, &gAllOne
);
1647 IN PCI_IO_DEVICE
*PciIoDevice
1651 Routine Description:
1660 // TODO: PciIoDevice - add argument and description to function comment
1661 // TODO: EFI_SUCCESS - add return value to function comment
1663 EFI_PCI_IO_PROTOCOL
*PciIo
;
1665 PciIo
= &(PciIoDevice
->PciIo
);
1668 // Put all the resource apertures including IO16
1669 // Io32, pMem32, pMem64 to quiescent state
1670 // Resource base all ones, Resource limit all zeros
1672 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
1673 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1D, 1, &gAllZero
);
1675 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x20, 1, &gAllOne
);
1676 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x22, 1, &gAllZero
);
1678 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x24, 1, &gAllOne
);
1679 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x26, 1, &gAllZero
);
1681 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllOne
);
1682 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2C, 1, &gAllZero
);
1685 // don't support use io32 as for now
1687 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x30, 1, &gAllOne
);
1688 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x32, 1, &gAllZero
);
1691 // Force Interrupt line to zero for cards that come up randomly
1693 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
1700 IN PCI_IO_DEVICE
*PciIoDevice
1704 Routine Description:
1713 // TODO: PciIoDevice - add argument and description to function comment
1714 // TODO: EFI_SUCCESS - add return value to function comment
1716 EFI_PCI_IO_PROTOCOL
*PciIo
;
1718 PciIo
= &(PciIoDevice
->PciIo
);
1721 // Put all the resource apertures including IO16
1722 // Io32, pMem32, pMem64 to quiescent state(
1723 // Resource base all ones, Resource limit all zeros
1725 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x1c, 1, &gAllOne
);
1726 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x20, 1, &gAllZero
);
1728 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x24, 1, &gAllOne
);
1729 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllZero
);
1731 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2c, 1, &gAllOne
);
1732 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x30, 1, &gAllZero
);
1734 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x34, 1, &gAllOne
);
1735 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x38, 1, &gAllZero
);
1738 // Force Interrupt line to zero for cards that come up randomly
1740 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
1746 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
1754 Routine Description:
1763 // TODO: PciRootBridgeIo - add argument and description to function comment
1764 // TODO: Pci - add argument and description to function comment
1765 // TODO: Bus - add argument and description to function comment
1766 // TODO: Device - add argument and description to function comment
1767 // TODO: Func - add argument and description to function comment
1771 PCI_IO_DEVICE
*PciIoDevice
;
1775 Status
= gBS
->AllocatePool (
1776 EfiBootServicesData
,
1777 sizeof (PCI_IO_DEVICE
),
1778 (VOID
**) &PciIoDevice
1781 if (EFI_ERROR (Status
)) {
1785 ZeroMem (PciIoDevice
, sizeof (PCI_IO_DEVICE
));
1787 PciIoDevice
->Signature
= PCI_IO_DEVICE_SIGNATURE
;
1788 PciIoDevice
->Handle
= NULL
;
1789 PciIoDevice
->PciRootBridgeIo
= PciRootBridgeIo
;
1790 PciIoDevice
->DevicePath
= NULL
;
1791 PciIoDevice
->BusNumber
= Bus
;
1792 PciIoDevice
->DeviceNumber
= Device
;
1793 PciIoDevice
->FunctionNumber
= Func
;
1794 PciIoDevice
->Decodes
= 0;
1795 if (gFullEnumeration
) {
1796 PciIoDevice
->Allocated
= FALSE
;
1798 PciIoDevice
->Allocated
= TRUE
;
1801 PciIoDevice
->Registered
= FALSE
;
1802 PciIoDevice
->Attributes
= 0;
1803 PciIoDevice
->Supports
= 0;
1804 PciIoDevice
->BusOverride
= FALSE
;
1805 PciIoDevice
->AllOpRomProcessed
= FALSE
;
1807 PciIoDevice
->IsPciExp
= FALSE
;
1809 CopyMem (&(PciIoDevice
->Pci
), Pci
, sizeof (PCI_TYPE01
));
1812 // Initialize the PCI I/O instance structure
1815 Status
= InitializePciIoInstance (PciIoDevice
);
1816 Status
= InitializePciDriverOverrideInstance (PciIoDevice
);
1818 if (EFI_ERROR (Status
)) {
1819 gBS
->FreePool (PciIoDevice
);
1824 // Initialize the reserved resource list
1826 InitializeListHead (&PciIoDevice
->ReservedResourceList
);
1829 // Initialize the driver list
1831 InitializeListHead (&PciIoDevice
->OptionRomDriverList
);
1834 // Initialize the child list
1836 InitializeListHead (&PciIoDevice
->ChildList
);
1842 PciEnumeratorLight (
1843 IN EFI_HANDLE Controller
1847 Routine Description:
1849 This routine is used to enumerate entire pci bus system
1859 // TODO: Controller - add argument and description to function comment
1860 // TODO: EFI_SUCCESS - add return value to function comment
1861 // TODO: EFI_SUCCESS - add return value to function comment
1865 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
1866 PCI_IO_DEVICE
*RootBridgeDev
;
1869 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
1872 MaxBus
= PCI_MAX_BUS
;
1876 // If this host bridge has been already enumerated, then return successfully
1878 if (RootBridgeExisted (Controller
)) {
1883 // Open pci root bridge io protocol
1885 Status
= gBS
->OpenProtocol (
1887 &gEfiPciRootBridgeIoProtocolGuid
,
1888 (VOID
**) &PciRootBridgeIo
,
1889 gPciBusDriverBinding
.DriverBindingHandle
,
1891 EFI_OPEN_PROTOCOL_BY_DRIVER
1893 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
1897 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**) &Descriptors
);
1899 if (EFI_ERROR (Status
)) {
1903 while (PciGetBusRange (&Descriptors
, &MinBus
, &MaxBus
, NULL
) == EFI_SUCCESS
) {
1906 // Create a device node for root bridge device with a NULL host bridge controller handle
1908 RootBridgeDev
= CreateRootBridge (Controller
);
1910 if (!RootBridgeDev
) {
1916 // Record the root bridge io protocol
1918 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
1920 Status
= PciPciDeviceInfoCollector (
1925 if (!EFI_ERROR (Status
)) {
1928 // Remove those PCI devices which are rejected when full enumeration
1930 RemoveRejectedPciDevices (RootBridgeDev
->Handle
, RootBridgeDev
);
1933 // Process option rom light
1935 ProcessOptionRomLight (RootBridgeDev
);
1938 // Determine attributes for all devices under this root bridge
1940 DetermineDeviceAttribute (RootBridgeDev
);
1943 // If successfully, insert the node into device pool
1945 InsertRootBridge (RootBridgeDev
);
1949 // If unsuccessly, destroy the entire node
1951 DestroyRootBridge (RootBridgeDev
);
1962 IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1965 OUT UINT16
*BusRange
1969 Routine Description:
1975 Descriptors - A pointer to the address space descriptor.
1976 MinBus - The min bus.
1977 MaxBus - The max bus.
1978 BusRange - The bus range.
1985 // TODO: EFI_SUCCESS - add return value to function comment
1986 // TODO: EFI_NOT_FOUND - add return value to function comment
1989 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
1990 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
1991 if (MinBus
!= NULL
) {
1992 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
1995 if (MaxBus
!= NULL
) {
1996 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
1999 if (BusRange
!= NULL
) {
2000 *BusRange
= (UINT16
) (*Descriptors
)->AddrLen
;
2009 return EFI_NOT_FOUND
;
2013 StartManagingRootBridge (
2014 IN PCI_IO_DEVICE
*RootBridgeDev
2018 Routine Description:
2028 // TODO: RootBridgeDev - add argument and description to function comment
2029 // TODO: EFI_SUCCESS - add return value to function comment
2031 EFI_HANDLE RootBridgeHandle
;
2033 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2036 // Get the root bridge handle
2038 RootBridgeHandle
= RootBridgeDev
->Handle
;
2039 PciRootBridgeIo
= NULL
;
2042 // Get the pci root bridge io protocol
2044 Status
= gBS
->OpenProtocol (
2046 &gEfiPciRootBridgeIoProtocolGuid
,
2047 (VOID
**) &PciRootBridgeIo
,
2048 gPciBusDriverBinding
.DriverBindingHandle
,
2050 EFI_OPEN_PROTOCOL_BY_DRIVER
2053 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2058 // Store the PciRootBridgeIo protocol into root bridge private data
2060 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2067 IsPciDeviceRejected (
2068 IN PCI_IO_DEVICE
*PciIoDevice
2072 Routine Description:
2074 This routine can be used to check whether a PCI device should be rejected when light enumeration
2080 TRUE This device should be rejected
2081 FALSE This device shouldn't be rejected
2084 // TODO: PciIoDevice - add argument and description to function comment
2093 // PPB should be skip!
2095 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
2099 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
2101 // Only test base registers for P2C
2103 for (BarOffset
= 0x1C; BarOffset
<= 0x38; BarOffset
+= 2 * sizeof (UINT32
)) {
2105 Mask
= (BarOffset
< 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
2106 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2107 if (EFI_ERROR (Status
)) {
2111 TestValue
= TestValue
& Mask
;
2112 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2114 // The bar isn't programed, so it should be rejected
2123 for (BarOffset
= 0x14; BarOffset
<= 0x24; BarOffset
+= sizeof (UINT32
)) {
2127 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2128 if (EFI_ERROR (Status
)) {
2132 if (TestValue
& 0x01) {
2139 TestValue
= TestValue
& Mask
;
2140 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2151 TestValue
= TestValue
& Mask
;
2153 if ((TestValue
& 0x07) == 0x04) {
2158 BarOffset
+= sizeof (UINT32
);
2159 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2162 // Test its high 32-Bit BAR
2165 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2166 if (TestValue
== OldValue
) {
2176 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2188 IN PCI_IO_DEVICE
*Bridge
,
2189 IN UINT8 StartBusNumber
2193 Routine Description:
2195 TODO: Add function description
2199 Bridge - TODO: add argument description
2200 StartBusNumber - TODO: add argument description
2204 EFI_SUCCESS - TODO: Add description for return value
2214 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2216 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2218 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2219 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2222 // Check to see whether a pci device is present
2224 Status
= PciDevicePresent (
2232 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
))) {
2234 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
2235 Status
= PciRootBridgeIo
->Pci
.Read (
2243 // Reset register 18h, 19h, 1Ah on PCI Bridge
2245 Register
&= 0xFF000000;
2246 Status
= PciRootBridgeIo
->Pci
.Write (
2255 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
2257 // Skip sub functions, this is not a multi function device
2259 Func
= PCI_MAX_FUNC
;