3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
26 * Universal Host Controller Interface data structures and defines
29 #include <IndustryStandard/pci22.h>
31 #define EFI_D_UHCI EFI_D_INFO
36 #define STALL_1_MILLI_SECOND 1000
37 #define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND
39 #define FORCE_GLOBAL_RESUME_TIME 20 * STALL_1_MILLI_SECOND
41 #define ROOT_PORT_REST_TIME 50 * STALL_1_MILLI_SECOND
43 #define PORT_RESET_RECOVERY_TIME 10 * STALL_1_MILLI_SECOND
48 #define INTERRUPT_POLLING_TIME 50 * 1000 * 10
51 // UHCI IO Space Address Register Register locates at
52 // offset 20 ~ 23h of PCI Configuration Space (UHCI spec, Revision 1.1),
53 // so, its BAR Index is 4.
55 #define USB_BAR_INDEX 4
58 // One memory block uses 1 page (common buffer for QH,TD use.)
60 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1
62 #define bit(a) 1 << (a)
65 // ////////////////////////////////////////////////////////////////////////
67 // Universal Host Controller Registers Definitions
69 //////////////////////////////////////////////////////////////////////////
70 extern UINT16 USBBaseAddr
;
72 /* Command register */
73 #define USBCMD 0 /* Command Register Offset 00-01h */
74 #define USBCMD_RS bit (0) /* Run/Stop */
75 #define USBCMD_HCRESET bit (1) /* Host reset */
76 #define USBCMD_GRESET bit (2) /* Global reset */
77 #define USBCMD_EGSM bit (3) /* Global Suspend Mode */
78 #define USBCMD_FGR bit (4) /* Force Global Resume */
79 #define USBCMD_SWDBG bit (5) /* SW Debug mode */
80 #define USBCMD_CF bit (6) /* Config Flag (sw only) */
81 #define USBCMD_MAXP bit (7) /* Max Packet (0 = 32, 1 = 64) */
84 #define USBSTS 2 /* Status Register Offset 02-03h */
85 #define USBSTS_USBINT bit (0) /* Interrupt due to IOC */
86 #define USBSTS_ERROR bit (1) /* Interrupt due to error */
87 #define USBSTS_RD bit (2) /* Resume Detect */
88 #define USBSTS_HSE bit (3) /* Host System Error*/
89 #define USBSTS_HCPE bit (4) /* Host Controller Process Error*/
90 #define USBSTS_HCH bit (5) /* HC Halted */
92 /* Interrupt enable register */
93 #define USBINTR 4 /* Interrupt Enable Register 04-05h */
94 #define USBINTR_TIMEOUT bit (0) /* Timeout/CRC error enable */
95 #define USBINTR_RESUME bit (1) /* Resume interrupt enable */
96 #define USBINTR_IOC bit (2) /* Interrupt On Complete enable */
97 #define USBINTR_SP bit (3) /* Short packet interrupt enable */
99 /* Frame Number Register Offset 06-08h */
102 /* Frame List Base Address Register Offset 08-0Bh */
103 #define USBFLBASEADD 8
105 /* Start of Frame Modify Register Offset 0Ch */
108 /* USB port status and control registers */
109 #define USBPORTSC1 0x10 /*Port 1 offset 10-11h */
110 #define USBPORTSC2 0x12 /*Port 2 offset 12-13h */
112 #define USBPORTSC_CCS bit (0) /* Current Connect Status*/
113 #define USBPORTSC_CSC bit (1) /* Connect Status Change */
114 #define USBPORTSC_PED bit (2) /* Port Enable / Disable */
115 #define USBPORTSC_PEDC bit (3) /* Port Enable / Disable Change */
116 #define USBPORTSC_LSL bit (4) /* Line Status Low bit*/
117 #define USBPORTSC_LSH bit (5) /* Line Status High bit*/
118 #define USBPORTSC_RD bit (6) /* Resume Detect */
119 #define USBPORTSC_LSDA bit (8) /* Low Speed Device Attached */
120 #define USBPORTSC_PR bit (9) /* Port Reset */
121 #define USBPORTSC_SUSP bit (12) /* Suspend */
123 /* PCI Configuration Registers for USB */
126 // Class Code Register offset
130 // USB IO Space Base Address Register offset
135 // USB legacy Support
137 #define USB_EMULATION 0xc0
140 // USB Base Class Code,Sub-Class Code and Programming Interface.
142 #define PCI_CLASSC_PI_UHCI 0x00
144 #define SETUP_PACKET_ID 0x2D
145 #define INPUT_PACKET_ID 0x69
146 #define OUTPUT_PACKET_ID 0xE1
147 #define ERROR_PACKET_ID 0x55
150 // ////////////////////////////////////////////////////////////////////////
152 // USB Transfer Mechanism Data Structures
154 //////////////////////////////////////////////////////////////////////////
157 // USB Class Code structure
166 UINT32 QHHorizontalTerminate
: 1;
167 UINT32 QHHorizontalQSelect
: 1;
168 UINT32 QHHorizontalRsvd
: 2;
169 UINT32 QHHorizontalPtr
: 28;
170 UINT32 QHVerticalTerminate
: 1;
171 UINT32 QHVerticalQSelect
: 1;
172 UINT32 QHVerticalRsvd
: 2;
173 UINT32 QHVerticalPtr
: 28;
177 UINT32 TDLinkPtrTerminate
: 1;
178 UINT32 TDLinkPtrQSelect
: 1;
179 UINT32 TDLinkPtrDepthSelect
: 1;
180 UINT32 TDLinkPtrRsvd
: 1;
181 UINT32 TDLinkPtr
: 28;
182 UINT32 TDStatusActualLength
: 11;
183 UINT32 TDStatusRsvd
: 5;
185 UINT32 TDStatusIOC
: 1;
186 UINT32 TDStatusIOS
: 1;
187 UINT32 TDStatusLS
: 1;
188 UINT32 TDStatusErr
: 2;
189 UINT32 TDStatusSPD
: 1;
190 UINT32 TDStatusRsvd2
: 2;
191 UINT32 TDTokenPID
: 8;
192 UINT32 TDTokenDevAddr
: 7;
193 UINT32 TDTokenEndPt
: 4;
194 UINT32 TDTokenDataToggle
: 1;
195 UINT32 TDTokenRsvd
: 1;
196 UINT32 TDTokenMaxLen
: 11;
206 VOID
*ptrNextIntQH
; // for interrupt transfer's special use
215 UINT16 TDBufferLength
;
220 // ////////////////////////////////////////////////////////////////////////
222 // Universal Host Controller Device Data Structure
224 //////////////////////////////////////////////////////////////////////////
225 #define USB_HC_DEV_FROM_THIS(a) CR (a, USB_HC_DEV, UsbHc, USB_HC_DEV_SIGNATURE)
226 #define USB2_HC_DEV_FROM_THIS(a) CR (a, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)
228 #define USB_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')
229 #define INTERRUPT_LIST_SIGNATURE EFI_SIGNATURE_32 ('i', 'n', 't', 's')
238 TD_STRUCT
*PtrFirstTD
;
243 UINT8
*DataBuffer
; // allocated host memory, not mapped memory
244 EFI_ASYNC_USB_TRANSFER_CALLBACK InterruptCallBack
;
245 VOID
*InterruptContext
;
248 #define INTERRUPT_LIST_FROM_LINK(a) CR (a, INTERRUPT_LIST, Link, INTERRUPT_LIST_SIGNATURE)
251 UINT32 FrameListPtrTerminate
: 1;
252 UINT32 FrameListPtrQSelect
: 1;
253 UINT32 FrameListRsvd
: 2;
254 UINT32 FrameListPtr
: 28;
258 typedef struct _MEMORY_MANAGE_HEADER
{
260 UINTN BitArraySizeInBytes
;
261 UINT8
*MemoryBlockPtr
;
262 UINTN MemoryBlockSizeInBytes
;
264 struct _MEMORY_MANAGE_HEADER
*Next
;
265 } MEMORY_MANAGE_HEADER
;
269 EFI_USB_HC_PROTOCOL UsbHc
;
270 EFI_USB2_HC_PROTOCOL Usb2Hc
;
271 EFI_PCI_IO_PROTOCOL
*PciIo
;
276 LIST_ENTRY InterruptListHead
;
277 FRAMELIST_ENTRY
*FrameListEntry
;
278 VOID
*FrameListMapping
;
279 MEMORY_MANAGE_HEADER
*MemoryHeader
;
280 EFI_EVENT InterruptTransTimer
;
281 EFI_UNICODE_STRING_TABLE
*ControllerNameTable
;
285 extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding
;
286 extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName
;
290 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
291 IN UINT32 CmdAddrOffset
,
298 Write UHCI Command Register
302 PciIo - EFI_PCI_IO_PROTOCOL
303 CmdAddrOffset - Command address offset
304 UsbCmd - Data to write
315 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
316 IN UINT32 CmdAddrOffset
,
323 Read UHCI Command Register
327 PciIo - EFI_PCI_IO_PROTOCOL
328 CmdAddrOffset - Command address offset
329 Data - Data to return
340 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
341 IN UINT32 StatusAddrOffset
,
348 Write UHCI Staus Register
352 PciIo - EFI_PCI_IO_PROTOCOL
353 StatusAddrOffset - Status address offset
354 UsbSts - Data to write
365 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
366 IN UINT32 StatusAddrOffset
,
373 Read UHCI Staus Register
377 PciIo - EFI_PCI_IO_PROTOCOL
378 StatusAddrOffset - Status address offset
379 UsbSts - Data to return
390 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
391 IN UINT32 StatusAddrOffset
397 Clear the content of UHC's Status Register
401 PciIo - EFI_PCI_IO_PROTOCOL
402 StatusAddrOffset - Status address offset
412 ReadUHCFrameNumberReg (
413 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
414 IN UINT32 FrameNumAddrOffset
,
421 Read from UHC's Frame Number Register
425 PciIo - EFI_PCI_IO_PROTOCOL
426 FrameNumAddrOffset - Frame number register offset
427 Data - Data to return
436 WriteUHCFrameListBaseReg (
437 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
438 IN UINT32 FlBaseAddrOffset
,
439 IN UINT32 UsbFrameListBaseAddr
445 Write to UHC's Frame List Base Register
449 PciIo - EFI_PCI_IO_PROTOCOL
450 FlBaseAddrOffset - Frame Base address register
451 UsbFrameListBaseAddr - Address to write
462 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
463 IN UINT32 PortAddrOffset
,
470 Read from UHC's Root Port Register
474 PciIo - EFI_PCI_IO_PROTOCOL
475 PortAddrOffset - Port Addrress Offset,
476 Data - Data to return
486 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
487 IN UINT32 PortAddrOffset
,
488 IN UINT16 ControlBits
494 Write to UHC's Root Port Register
498 PciIo - EFI_PCI_IO_PROTOCOL
499 PortAddrOffset - Port Addrress Offset,
500 ControlBits - Data to write
510 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
511 IN UINT32 StatusRegAddr
,
518 Wait until UHCI halt or timeout
522 PciIo - EFI_PCI_IO_PROTOCOL
523 StatusRegAddr - Status Register Address
524 Timeout - Time out value in us
528 EFI_DEVICE_ERROR - Unable to read the status register
529 EFI_TIMEOUT - Time out
530 EFI_SUCCESS - Success
537 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
538 IN UINT32 StatusRegAddr
544 Judge whether the host controller operates well
548 PciIo - EFI_PCI_IO_PROTOCOL
549 StatusRegAddr - Status register address
553 TRUE - Status is good
554 FALSE - Status is bad
560 IsHostSysOrProcessErr (
561 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
562 IN UINT32 StatusRegAddr
568 Judge the status is HostSys,ProcessErr error or good
572 PciIo - EFI_PCI_IO_PROTOCOL
573 StatusRegAddr - Status register address
577 TRUE - Status is good
578 FALSE - Status is bad
584 GetCurrentFrameNumber (
585 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
586 IN UINT32 FrameNumAddrOffset
592 Get Current Frame Number
596 PciIo - EFI_PCI_IO_PROTOCOL
597 FrameNumAddrOffset - FrameNum register AddrOffset
607 SetFrameListBaseAddress (
608 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
609 IN UINT32 FLBASEADDRReg
,
616 Set FrameListBase Address
620 PciIo - EFI_PCI_IO_PROTOCOL
621 FlBaseAddrReg - FrameListBase register
622 Addr - Address to set
632 GetFrameListBaseAddress (
633 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
640 Get Current Frame Number
644 PciIo - EFI_PCI_IO_PROTOCOL
645 FrameNumAddrOffset - FrameNum register AddrOffset
656 IN USB_HC_DEV
*HcDev
,
657 IN UINT32 FLBASEADDRReg
668 FlBaseAddrReg - Frame List register
672 EFI_OUT_OF_RESOURCES - Can't allocate memory resources
673 EFI_UNSUPPORTED - Map memory fail
674 EFI_SUCCESS - Success
681 IN USB_HC_DEV
*UhcDev
687 Free FrameList buffer
695 EFI_SUCCESS - success
722 IN USB_HC_DEV
*HcDev
,
723 OUT QH_STRUCT
**pptrQH
734 pptrQH - QH_STRUCT content to return
737 EFI_SUCCESS - Success
738 EFI_OUT_OF_RESOURCES - Can't allocate memory
744 SetQHHorizontalLinkPtr (
752 Set QH Horizontal Link Pointer
757 ptrNext - Data to write
767 GetQHHorizontalLinkPtr (
774 Get QH Horizontal Link Pointer
789 SetQHHorizontalQHorTDSelect (
797 Set QH Horizontal QH or TD
802 bQH - TRUE is QH FALSE is TD
811 SetQHHorizontalValidorInvalid (
819 Set QH Horizontal Valid or Invalid
824 bValid - TRUE is Valid FALSE is Invalid
833 SetQHVerticalLinkPtr (
841 Set QH Vertical Link Pointer
846 ptrNext - Data to write
855 GetQHVerticalLinkPtr (
862 Get QH Vertical Link Pointer
876 SetQHVerticalQHorTDSelect (
884 Set QH Vertical QH or TD
889 bQH - TRUE is QH FALSE is TD
899 IsQHHorizontalQHSelect (
906 Is QH Horizontal QH Select
921 SetQHVerticalValidorInvalid (
929 Set QH Vertical Valid or Invalid
934 IsValid - TRUE is valid FALSE is invalid
944 GetQHVerticalValidorInvalid (
951 Get QH Vertical Valid or Invalid
967 IN USB_HC_DEV
*HcDev
,
968 OUT TD_STRUCT
**ppTDStruct
979 ppTDStruct - place to store TD_STRUCT pointer
989 IN USB_HC_DEV
*HcDev
,
990 OUT TD_STRUCT
**pptrTD
1001 pptrTD - TD_STRUCT pointer to store
1005 EFI_OUT_OF_RESOURCES - Can't allocate resources
1006 EFI_SUCCESS - Success
1014 IN USB_HC_DEV
*HcDev
,
1019 IN UINT8 RequestLen
,
1020 OUT TD_STRUCT
**ppTD
1024 Routine Description:
1026 Generate Setup Stage TD
1031 DevAddr - Device address
1032 Endpoint - Endpoint number
1033 bSlow - Full speed or low speed
1034 pDevReq - Device request
1035 RequestLen - Request length
1036 ppTD - TD_STRUCT to return
1039 EFI_OUT_OF_RESOURCES - Can't allocate memory
1040 EFI_SUCCESS - Success
1047 IN USB_HC_DEV
*HcDev
,
1055 OUT TD_STRUCT
**ppTD
1059 Routine Description:
1061 Generate Data Stage TD
1066 DevAddr - Device address
1067 Endpoint - Endpoint number
1071 Toggle - Data toggle value
1072 bSlow - Full speed or low speed
1073 ppTD - TD_STRUCT to return
1076 EFI_OUT_OF_RESOURCES - Can't allocate memory
1077 EFI_SUCCESS - Success
1084 IN USB_HC_DEV
*HcDev
,
1089 OUT TD_STRUCT
**ppTD
1093 Routine Description:
1095 Generate Setup Stage TD
1100 DevAddr - Device address
1101 Endpoint - Endpoint number
1102 bSlow - Full speed or low speed
1103 pDevReq - Device request
1104 RequestLen - Request length
1105 ppTD - TD_STRUCT to return
1108 EFI_OUT_OF_RESOURCES - Can't allocate memory
1109 EFI_SUCCESS - Success
1115 SetTDLinkPtrValidorInvalid (
1116 IN TD_STRUCT
*ptrTDStruct
,
1121 Routine Description:
1123 Set TD Link Pointer Valid or Invalid
1127 ptrTDStruct - TD_STRUCT
1128 bValid - TRUE is valid FALSE is invalid
1138 SetTDLinkPtrQHorTDSelect (
1139 IN TD_STRUCT
*ptrTDStruct
,
1144 Routine Description:
1146 Set TD Link Pointer QH or TD Select
1150 ptrTDStruct - TD_STRUCT
1151 bQH - TRUE is QH FALSE is TD
1161 SetTDLinkPtrDepthorBreadth (
1162 IN TD_STRUCT
*ptrTDStruct
,
1167 Routine Description:
1169 Set TD Link Pointer depth or bread priority
1173 ptrTDStruct - TD_STRUCT
1174 bDepth - TRUE is Depth FALSE is Breadth
1185 IN TD_STRUCT
*ptrTDStruct
,
1190 Routine Description:
1196 ptrTDStruct - TD_STRUCT
1197 ptrNext - Pointer to set
1208 IN TD_STRUCT
*ptrTDStruct
1212 Routine Description:
1218 ptrTDStruct - TD_STRUCT
1228 EnableorDisableTDShortPacket (
1229 IN TD_STRUCT
*ptrTDStruct
,
1234 Routine Description:
1236 Enable or Disable TD ShortPacket
1240 ptrTDStruct - TD_STRUCT
1241 bEnable - TRUE is Enanble FALSE is Disable
1251 SetTDControlErrorCounter (
1252 IN TD_STRUCT
*ptrTDStruct
,
1257 Routine Description:
1259 Set TD Control ErrorCounter
1263 ptrTDStruct - TD_STRUCT
1264 nMaxErrors - Error counter number
1274 SetTDLoworFullSpeedDevice (
1275 IN TD_STRUCT
*ptrTDStruct
,
1276 IN BOOLEAN bLowSpeedDevice
1280 Routine Description:
1282 Set TD status low speed or full speed
1286 ptrTDStruct - A point to TD_STRUCT
1287 bLowSpeedDevice - Show low speed or full speed
1297 SetTDControlIsochronousorNot (
1298 IN TD_STRUCT
*ptrTDStruct
,
1299 IN BOOLEAN bIsochronous
1303 Routine Description:
1305 Set TD status Isochronous or not
1309 ptrTDStruct - A point to TD_STRUCT
1310 IsIsochronous - Show Isochronous or not
1320 SetorClearTDControlIOC (
1321 IN TD_STRUCT
*ptrTDStruct
,
1326 Routine Description:
1328 Set TD status IOC IsSet
1332 ptrTDStruct - A point to TD_STRUCT
1333 IsSet - Show IOC set or not
1343 SetTDStatusActiveorInactive (
1344 IN TD_STRUCT
*ptrTDStruct
,
1349 Routine Description:
1351 Set TD status active or not
1354 ptrTDStruct - A point to TD_STRUCT
1355 IsActive - Active or not
1365 SetTDTokenMaxLength (
1366 IN TD_STRUCT
*ptrTDStruct
,
1371 Routine Description:
1373 Set TD Token maxlength
1377 ptrTDStruct - A point to TD_STRUCT
1378 MaximumLength - Maximum length of TD Token
1382 Real maximum length set to TD Token
1388 SetTDTokenDataToggle1 (
1389 IN TD_STRUCT
*ptrTDStruct
1393 Routine Description:
1395 Set TD Token data toggle1
1399 ptrTDStruct - A point to TD_STRUCT
1409 SetTDTokenDataToggle0 (
1410 IN TD_STRUCT
*ptrTDStruct
1414 Routine Description:
1416 Set TD Token data toggle0
1420 ptrTDStruct - A point to TD_STRUCT
1430 GetTDTokenDataToggle (
1431 IN TD_STRUCT
*ptrTDStruct
1435 Routine Description:
1437 Get TD Token data toggle
1441 ptrTDStruct - A point to TD_STRUCT
1451 SetTDTokenEndPoint (
1452 IN TD_STRUCT
*ptrTDStruct
,
1457 Routine Description:
1459 Set Data Token endpoint number
1463 ptrTDStruct - A point to TD_STRUCT
1464 EndPoint - End point number
1474 SetTDTokenDeviceAddress (
1475 IN TD_STRUCT
*ptrTDStruct
,
1480 Routine Description:
1482 Set TD Token device address
1486 ptrTDStruct - A point to TD_STRUCT
1487 DeviceAddress - Device address
1497 SetTDTokenPacketID (
1498 IN TD_STRUCT
*ptrTDStruct
,
1503 Routine Description:
1505 Set TD Token packet ID
1509 ptrTDStruct - A point to TD_STRUCT
1521 IN TD_STRUCT
*ptrTDStruct
1525 Routine Description:
1531 ptrTDStruct - A point to TD_STRUCT
1542 IN TD_STRUCT
*ptrTDStruct
1546 Routine Description:
1548 Indicate whether TD status active or not
1552 ptrTDStruct - A point to TD_STRUCT
1564 IN TD_STRUCT
*ptrTDStruct
1568 Routine Description:
1570 Indicate whether TD status stalled or not
1574 ptrTDStruct - A point to TD_STRUCT
1585 IsTDStatusBufferError (
1586 IN TD_STRUCT
*ptrTDStruct
1590 Routine Description:
1592 Indicate whether TD status buffer error or not
1596 ptrTDStruct - A point to TD_STRUCT
1607 IsTDStatusBabbleError (
1608 IN TD_STRUCT
*ptrTDStruct
1612 Routine Description:
1614 Indicate whether TD status babble error or not
1618 ptrTDStruct - A point to TD_STRUCT
1629 IsTDStatusNAKReceived (
1630 IN TD_STRUCT
*ptrTDStruct
1634 Routine Description:
1636 Indicate whether TD status NAK received
1639 ptrTDStruct - A point to TD_STRUCT
1644 FALSE - NAK not received
1650 IsTDStatusCRCTimeOutError (
1651 IN TD_STRUCT
*ptrTDStruct
1655 Routine Description:
1657 Indicate whether TD status CRC timeout error or not
1661 ptrTDStruct - A point to TD_STRUCT
1665 TRUE - CRC timeout error
1666 FALSE - CRC timeout no error
1672 IsTDStatusBitStuffError (
1673 IN TD_STRUCT
*ptrTDStruct
1677 Routine Description:
1679 Indicate whether TD status bit stuff error or not
1683 ptrTDStruct - A point to TD_STRUCT
1687 TRUE - Bit stuff error
1688 FALSE - Bit stuff no error
1694 GetTDStatusActualLength (
1695 IN TD_STRUCT
*ptrTDStruct
1699 Routine Description:
1701 Get TD status length
1705 ptrTDStruct - A point to TD_STRUCT
1709 Return Td status length
1715 GetTDTokenMaxLength (
1716 IN TD_STRUCT
*ptrTDStruct
1720 Routine Description:
1722 Get TD Token maximum length
1726 ptrTDStruct - A point to TD_STRUCT
1730 Return TD token maximum length
1736 GetTDTokenEndPoint (
1737 IN TD_STRUCT
*ptrTDStruct
1741 Routine Description:
1743 Get TD Token endpoint number
1747 ptrTDStruct - A point to TD_STRUCT
1751 Return TD Token endpoint number
1757 GetTDTokenDeviceAddress (
1758 IN TD_STRUCT
*ptrTDStruct
1762 Routine Description:
1764 Get TD Token device address
1768 ptrTDStruct - A point to TD_STRUCT
1772 Return TD Token device address
1778 GetTDTokenPacketID (
1779 IN TD_STRUCT
*ptrTDStruct
1783 Routine Description:
1785 Get TD Token packet ID
1789 ptrTDStruct - A point to TD_STRUCT
1793 Return TD Token packet ID
1800 IN TD_STRUCT
*ptrTDStruct
1804 Routine Description:
1806 Get the point to TD data buffer
1810 ptrTDStruct - A point to TD_STRUCT
1814 Return a point to TD data buffer
1820 GetTDLinkPtrValidorInvalid (
1821 IN TD_STRUCT
*ptrTDStruct
1825 Routine Description:
1827 Get TD LinkPtr valid or not
1831 ptrTDStruct - A point to TD_STRUCT
1843 IN TD_STRUCT
*ptrFirstTD
1847 Routine Description:
1849 Get the number of TDs
1853 PtrFirstTD - A point to the first TD_STRUCT
1857 Return the number of TDs
1864 IN QH_STRUCT
*ptrQH
,
1869 Routine Description:
1886 IN TD_STRUCT
*ptrPreTD
,
1891 Routine Description:
1897 ptrPreTD - Previous TD_STRUCT to be linked
1898 PtrTD - TD_STRUCT to link
1907 SetorClearCurFrameListTerminate (
1908 IN FRAMELIST_ENTRY
*pCurEntry
,
1913 Routine Description:
1915 Set or clear current framelist terminate
1919 pCurEntry - A point to FRAMELIST_ENTITY
1920 IsSet - TRUE to empty the frame and indicate the Pointer field is valid
1930 SetCurFrameListQHorTD (
1931 IN FRAMELIST_ENTRY
*pCurEntry
,
1936 Routine Description:
1938 Set current framelist QH or TD
1942 pCurEntry - A point to FRAMELIST_ENTITY
1943 IsQH - TRUE to set QH and FALSE to set TD
1953 GetCurFrameListTerminate (
1954 IN FRAMELIST_ENTRY
*pCurEntry
1958 Routine Description:
1960 Get current framelist terminate
1964 pCurEntry - A point to FRAMELIST_ENTITY
1969 FALSE - Not terminate
1975 SetCurFrameListPointer (
1976 IN FRAMELIST_ENTRY
*pCurEntry
,
1981 Routine Description:
1983 Set current framelist pointer
1987 pCurEntry - A point to FRAMELIST_ENTITY
1988 ptr - A point to FrameListPtr point to
1998 GetCurFrameListPointer (
1999 IN FRAMELIST_ENTRY
*pCurEntry
2003 Routine Description:
2005 Get current framelist pointer
2009 pCurEntry - A point to FRAMELIST_ENTITY
2013 A point FrameListPtr point to
2020 IN FRAMELIST_ENTRY
*pEntry
,
2021 IN UINT16 FrameListIndex
,
2026 Routine Description:
2028 Link QH To Frame List
2032 pEntry - FRAMELIST_ENTRY
2033 FrameListIndex - Frame List Index
2044 IN USB_HC_DEV
*HcDev
,
2045 IN QH_STRUCT
*ptrQH
,
2046 IN UINT16 FrameListIndex
,
2047 IN BOOLEAN SearchOther
,
2052 Routine Description:
2054 Unlink from frame list and delete single QH
2060 FrameListIndex - Frame List Index
2061 SearchOther - Search Other QH
2062 Delete - TRUE is to delete the QH
2073 IN USB_HC_DEV
*HcDev
,
2074 IN TD_STRUCT
*ptrFirstTD
2078 Routine Description:
2085 PtrFirstTD - TD link list head
2095 InsertQHTDToINTList (
2096 IN USB_HC_DEV
*HcDev
,
2097 IN QH_STRUCT
*ptrQH
,
2098 IN TD_STRUCT
*ptrFirstTD
,
2099 IN UINT8 DeviceAddress
,
2100 IN UINT8 EndPointAddress
,
2101 IN UINT8 DataToggle
,
2102 IN UINTN DataLength
,
2103 IN UINTN PollingInterval
,
2105 IN UINT8
*DataBuffer
,
2106 IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction
,
2110 Routine Description:
2112 Insert QH and TD To Interrupt List
2118 PtrFirstTD - First TD_STRUCT
2119 DeviceAddress - Device Address
2120 EndPointAddress - EndPoint Address
2121 DataToggle - Data Toggle
2122 DataLength - Data length
2123 PollingInterval - Polling Interval when inserted to frame list
2124 Mapping - Mapping alue
2125 DataBuffer - Data buffer
2126 CallBackFunction- CallBackFunction after interrupt transfeer
2127 Context - CallBackFunction Context passed as function parameter
2131 EFI_SUCCESS - Sucess
2132 EFI_INVALID_PARAMETER - Paremeter is error
2138 DeleteAsyncINTQHTDs (
2139 IN USB_HC_DEV
*HcDev
,
2140 IN UINT8 DeviceAddress
,
2141 IN UINT8 EndPointAddress
,
2142 OUT UINT8
*DataToggle
2145 Routine Description:
2147 Delete Async INT QH and TDs
2152 DeviceAddress - Device Address
2153 EndPointAddress - EndPoint Address
2154 DataToggle - Data Toggle
2158 EFI_SUCCESS - Sucess
2159 EFI_INVALID_PARAMETER - Paremeter is error
2166 IN TD_STRUCT
*ptrTD
,
2167 IN UINTN RequiredLen
,
2169 OUT UINTN
*ErrTDPos
,
2170 OUT UINTN
*ActualTransferSize
2174 Routine Description:
2180 PtrTD - TD_STRUCT to check
2181 RequiredLen - Required Len
2182 Result - Transfer result
2183 ErrTDPos - Error TD Position
2184 ActualTransferSize - Actual Transfer Size
2195 ExecuteAsyncINTTDs (
2196 IN USB_HC_DEV
*HcDev
,
2197 IN INTERRUPT_LIST
*ptrList
,
2199 OUT UINTN
*ErrTDPos
,
2200 OUT UINTN
*ActualLen
2204 Routine Description:
2206 Execute Async Interrupt TDs
2211 PtrList - INTERRUPT_LIST
2212 Result - Transfer result
2213 ErrTDPos - Error TD Position
2214 ActualTransferSize - Actual Transfer Size
2224 UpdateAsyncINTQHTDs (
2225 IN INTERRUPT_LIST
*ptrList
,
2231 Routine Description:
2233 Update Async Interrupt QH and TDs
2237 PtrList - INTERRUPT_LIST
2238 Result - Transfer reslut
2239 ErrTDPos - Error TD Position
2249 ReleaseInterruptList (
2250 IN USB_HC_DEV
*HcDev
,
2251 IN LIST_ENTRY
*ListHead
2255 Routine Description:
2257 Release Interrupt List
2262 ListHead - List head
2272 ExecuteControlTransfer (
2273 IN USB_HC_DEV
*HcDev
,
2274 IN TD_STRUCT
*ptrTD
,
2276 OUT UINTN
*ActualLen
,
2278 OUT UINT32
*TransferResult
2282 Routine Description:
2284 Execute Control Transfer
2291 ActualLen - Actual transfered Len
2292 TimeOut - TimeOut value in milliseconds
2293 TransferResult - Transfer result
2296 EFI_SUCCESS - Sucess
2297 EFI_DEVICE_ERROR - Error
2304 ExecBulkorSyncInterruptTransfer (
2305 IN USB_HC_DEV
*HcDev
,
2306 IN TD_STRUCT
*ptrTD
,
2308 OUT UINTN
*ActualLen
,
2309 OUT UINT8
*DataToggle
,
2311 OUT UINT32
*TransferResult
2315 Routine Description:
2317 Execute Bulk or SyncInterrupt Transfer
2324 ActualLen - Actual transfered Len
2325 DataToggle - Data Toggle
2326 TimeOut - TimeOut value in milliseconds
2327 TransferResult - Transfer result
2330 EFI_SUCCESS - Sucess
2331 EFI_DEVICE_ERROR - Error
2336 InitializeMemoryManagement (
2337 IN USB_HC_DEV
*HcDev
2341 Routine Description:
2343 Initialize Memory Management
2351 EFI_SUCCESS - Success
2358 IN USB_HC_DEV
*HcDev
,
2359 IN MEMORY_MANAGE_HEADER
**MemoryHeader
,
2360 IN UINTN MemoryBlockSizeInPages
2364 Routine Description:
2366 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,
2367 and use PciIo->Map to map the common buffer for Bus Master Read/Write.
2373 MemoryHeader - MEMORY_MANAGE_HEADER to output
2374 MemoryBlockSizeInPages - MemoryBlockSizeInPages
2378 EFI_SUCCESS - Success
2379 EFI_OUT_OF_RESOURCES - Out of resources
2380 EFI_UNSUPPORTED - Unsupported
2387 IN USB_HC_DEV
*HcDev
,
2388 IN MEMORY_MANAGE_HEADER
*MemoryHeader
2392 Routine Description:
2399 MemoryHeader - MemoryHeader to be freed
2403 EFI_INVALID_PARAMETER - Parameter is error
2404 EFI_SUCCESS - Success
2411 IN USB_HC_DEV
*UhcDev
,
2417 Routine Description:
2424 Pool - Place to store pointer to the memory buffer
2425 AllocSize - Alloc Size
2429 EFI_SUCCESS - Success
2436 IN USB_HC_DEV
*HcDev
,
2442 Routine Description:
2450 AllocSize - Pool size
2460 InsertMemoryHeaderToList (
2461 IN MEMORY_MANAGE_HEADER
*MemoryHeader
,
2462 IN MEMORY_MANAGE_HEADER
*NewMemoryHeader
2466 Routine Description:
2468 Insert Memory Header To List
2472 MemoryHeader - MEMORY_MANAGE_HEADER
2473 NewMemoryHeader - MEMORY_MANAGE_HEADER
2483 AllocMemInMemoryBlock (
2484 IN MEMORY_MANAGE_HEADER
*MemoryHeader
,
2486 IN UINTN NumberOfMemoryUnit
2490 Routine Description:
2492 Alloc Memory In MemoryBlock
2496 MemoryHeader - MEMORY_MANAGE_HEADER
2497 Pool - Place to store pointer to memory
2498 NumberOfMemoryUnit - Number Of Memory Unit
2502 EFI_NOT_FOUND - Can't find the free memory
2503 EFI_SUCCESS - Success
2509 IsMemoryBlockEmptied (
2510 IN MEMORY_MANAGE_HEADER
*MemoryHeaderPtr
2514 Routine Description:
2516 Is Memory Block Emptied
2520 MemoryHeaderPtr - MEMORY_MANAGE_HEADER
2532 IN MEMORY_MANAGE_HEADER
*FirstMemoryHeader
,
2533 IN MEMORY_MANAGE_HEADER
*FreeMemoryHeader
2537 Routine Description:
2543 FirstMemoryHeader - MEMORY_MANAGE_HEADER
2544 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER
2554 DelMemoryManagement (
2555 IN USB_HC_DEV
*HcDev
2559 Routine Description:
2561 Delete Memory Management
2569 EFI_SUCCESS - Success
2575 EnableMaxPacketSize (
2576 IN USB_HC_DEV
*HcDev
2580 Routine Description:
2582 Enable Max Packet Size
2596 CleanUsbTransactions (
2597 IN USB_HC_DEV
*HcDev
2601 Routine Description:
2603 Clean USB Transactions
2607 HcDev - A point to USB_HC_DEV
2617 TurnOffUSBEmulation (
2618 IN EFI_PCI_IO_PROTOCOL
*PciIo
2622 Routine Description:
2624 Set current framelist QH or TD
2628 pCurEntry - A point to FRAMELIST_ENTITY
2629 IsQH - TRUE to set QH and FALSE to set TD