EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2012-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include "Lan9118Dxe.h"
  16
  17 STATIC EFI_MAC_ADDRESS mZeroMac = { { 0 } };
  18
  19 /**
  20   This internal function reverses bits for 32bit data.
  21
  22   @param  Value                 The data to be reversed.
  23
  24   @return                       Data reversed.
  25
  26 **/
  27 UINT32
  28 ReverseBits (
  29   UINT32  Value
  30   )
  31 {
  32   UINTN   Index;
  33   UINT32  NewValue;
  34
  35   NewValue = 0;
  36   for (Index = 0; Index < 32; Index++) {
  37     if ((Value & (1 << Index)) != 0) {
  38       NewValue = NewValue | (1 << (31 - Index));
  39     }
  40   }
  41
  42   return NewValue;
  43 }
  44
  45 /*
  46 **  Create Ethernet CRC
  47 **
  48 **  INFO USED:
  49 **    1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check
  50 **
  51 **    2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html
  52 **
  53 **    3: http://en.wikipedia.org/wiki/Computation_of_CRC
  54 */
  55 UINT32
  56 GenEtherCrc32 (
  57   IN    EFI_MAC_ADDRESS *Mac,
  58   IN    UINT32 AddrLen
  59   )
  60 {
  61   INT32 Iter;
  62   UINT32 Remainder;
  63   UINT8 *Ptr;
  64
  65   Iter = 0;
  66   Remainder = 0xFFFFFFFF;    // 0xFFFFFFFF is standard seed for Ethernet
  67
  68   // Convert Mac Address to array of bytes
  69   Ptr = (UINT8*)Mac;
  70
  71   // Generate the Crc bit-by-bit (LSB first)
  72   while (AddrLen--) {
  73     Remainder ^= *Ptr++;
  74     for (Iter = 0;Iter < 8;Iter++) {
  75       // Check if exponent is set
  76       if (Remainder & 1) {
  77         Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;
  78       } else {
  79         Remainder = (Remainder >> 1) ^ 0;
  80       }
  81     }
  82   }
  83
  84   // Reverse the bits before returning (to Big Endian)
  85   //TODO: Need to be reviewed. Do we want to do a bit reverse or a byte reverse (in this case use SwapBytes32())
  86   return ReverseBits (Remainder);
  87 }
  88
  89 // Function to read from MAC indirect registers
  90 UINT32
  91 IndirectMACRead32 (
  92   UINT32 Index
  93   )
  94 {
  95   UINT32 MacCSR;
  96
  97   // Check index is in the range
  98   ASSERT(Index <= 12);
  99
 100   // Wait until CSR busy bit is cleared
 101   while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 102
 103   // Set CSR busy bit to ensure read will occur
 104   // Set the R/W bit to indicate we are reading
 105   // Set the index of CSR Address to access desired register
 106   MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index);
 107
 108   // Write to the register
 109   Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);
 110
 111   // Wait until CSR busy bit is cleared
 112   while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 113
 114   // Now read from data register to get read value
 115   return Lan9118MmioRead32 (LAN9118_MAC_CSR_DATA);
 116 }
 117
 118 /*
 119  * LAN9118 chips have special restrictions on some back-to-back Write/Read or
 120  * Read/Read pairs of accesses. After a read or write that changes the state of
 121  * the device, there is a period in which stale values may be returned in
 122  * response to a read. This period is dependent on the registers accessed.
 123  *
 124  * We must delay prior reads by this period. This can either be achieved by
 125  * timer-based delays, or by performing dummy reads of the BYTE_TEST register,
 126  * for which the recommended number of reads is described in the LAN9118 data
 127  * sheet. This is required in addition to any memory barriers.
 128  *
 129  * This function performs a number of dummy reads of the BYTE_TEST register, as
 130  * a building block for the above.
 131  */
 132 VOID
 133 WaitDummyReads (
 134   UINTN Count
 135   )
 136 {
 137   while (Count--)
 138     MmioRead32(LAN9118_BYTE_TEST);
 139 }
 140
 141 UINT32
 142 Lan9118RawMmioRead32(
 143   UINTN Address,
 144   UINTN Delay
 145   )
 146 {
 147   UINT32 Value;
 148
 149   Value = MmioRead32(Address);
 150   WaitDummyReads(Delay);
 151   return Value;
 152 }
 153
 154 UINT32
 155 Lan9118RawMmioWrite32(
 156   UINTN Address,
 157   UINT32 Value,
 158   UINTN Delay
 159   )
 160 {
 161   MmioWrite32(Address, Value);
 162   WaitDummyReads(Delay);
 163   return Value;
 164 }
 165
 166 // Function to write to MAC indirect registers
 167 UINT32
 168 IndirectMACWrite32 (
 169   UINT32 Index,
 170   UINT32 Value
 171   )
 172 {
 173   UINT32 ValueWritten;
 174   UINT32 MacCSR;
 175
 176   // Check index is in the range
 177   ASSERT(Index <= 12);
 178
 179   // Wait until CSR busy bit is cleared
 180   while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 181
 182   // Set CSR busy bit to ensure read will occur
 183   // Set the R/W bit to indicate we are writing
 184   // Set the index of CSR Address to access desired register
 185   MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index);
 186
 187   // Now write the value to the register before issuing the write command
 188   ValueWritten = Lan9118MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);
 189
 190   // Write the config to the register
 191   Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);
 192
 193   // Wait until CSR busy bit is cleared
 194   while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 195
 196   return ValueWritten;
 197 }
 198
 199 // Function to read from MII register (PHY Access)
 200 UINT32
 201 IndirectPHYRead32 (
 202   UINT32 Index
 203   )
 204 {
 205   UINT32 ValueRead;
 206   UINT32 MiiAcc;
 207
 208   // Check it is a valid index
 209   ASSERT(Index < 31);
 210
 211   // Wait for busy bit to clear
 212   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 213
 214   // Clear the R/W bit to indicate we are reading
 215   // Set the index of the MII register
 216   // Set the PHY Address
 217   // Set the MII busy bit to allow read
 218   MiiAcc = MII_ACC_MII_READ | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;
 219
 220   // Now write this config to register
 221   IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);
 222
 223   // Wait for busy bit to clear
 224   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 225
 226   // Now read the value of the register
 227   ValueRead = (IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_DATA) & 0xFFFF); // only lower 16 bits are valid for any PHY register
 228
 229   return ValueRead;
 230 }
 231
 232
 233 // Function to write to the MII register (PHY Access)
 234 UINT32
 235 IndirectPHYWrite32 (
 236   UINT32 Index,
 237   UINT32 Value
 238   )
 239 {
 240   UINT32 MiiAcc;
 241   UINT32 ValueWritten;
 242
 243   // Check it is a valid index
 244   ASSERT(Index < 31);
 245
 246   // Wait for busy bit to clear
 247   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 248
 249   // Clear the R/W bit to indicate we are reading
 250   // Set the index of the MII register
 251   // Set the PHY Address
 252   // Set the MII busy bit to allow read
 253   MiiAcc = MII_ACC_MII_WRITE | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;
 254
 255   // Write the desired value to the register first
 256   ValueWritten = IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_DATA, (Value & 0xFFFF));
 257
 258   // Now write the config to register
 259   IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);
 260
 261   // Wait for operation to terminate
 262   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 263
 264   return ValueWritten;
 265 }
 266
 267
 268 /* ---------------- EEPROM Operations ------------------ */
 269
 270
 271 // Function to read from EEPROM memory
 272 UINT32
 273 IndirectEEPROMRead32 (
 274   UINT32 Index
 275   )
 276 {
 277   UINT32 EepromCmd;
 278
 279   // Set the busy bit to ensure read will occur
 280   EepromCmd = E2P_EPC_BUSY | E2P_EPC_CMD_READ;
 281
 282   // Set the index to access desired EEPROM memory location
 283   EepromCmd |= E2P_EPC_ADDRESS(Index);
 284
 285   // Write to Eeprom command register
 286   Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);
 287   gBS->Stall (LAN9118_STALL);
 288
 289   // Wait until operation has completed
 290   while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 291
 292   // Check that operation didn't time out
 293   if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {
 294     DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index));
 295     return 0;
 296   }
 297
 298   // Wait until operation has completed
 299   while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 300
 301   // Finally read the value
 302   return Lan9118MmioRead32 (LAN9118_E2P_DATA);
 303 }
 304
 305 // Function to write to EEPROM memory
 306 UINT32
 307 IndirectEEPROMWrite32 (
 308   UINT32 Index,
 309   UINT32 Value
 310   )
 311 {
 312   UINT32 ValueWritten;
 313   UINT32 EepromCmd;
 314
 315   ValueWritten = 0;
 316
 317   // Read the EEPROM Command register
 318   EepromCmd = Lan9118MmioRead32 (LAN9118_E2P_CMD);
 319
 320   // Set the busy bit to ensure read will occur
 321   EepromCmd |= ((UINT32)1 << 31);
 322
 323   // Set the EEPROM command to write(0b011)
 324   EepromCmd &= ~(7 << 28);    // Clear the command first
 325   EepromCmd |= (3 << 28);     // Write 011
 326
 327   // Set the index to access desired EEPROM memory location
 328   EepromCmd |= (Index & 0xF);
 329
 330   // Write the value to the data register first
 331   ValueWritten = Lan9118MmioWrite32 (LAN9118_E2P_DATA, Value);
 332
 333   // Write to Eeprom command register
 334   Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);
 335   gBS->Stall (LAN9118_STALL);
 336
 337   // Wait until operation has completed
 338   while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 339
 340   // Check that operation didn't time out
 341   if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {
 342     DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value));
 343     return 0;
 344   }
 345
 346   // Wait until operation has completed
 347   while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 348
 349   return ValueWritten;
 350 }
 351
 352 /* ---------------- General Operations ----------------- */
 353
 354 VOID
 355 Lan9118SetMacAddress (
 356   EFI_MAC_ADDRESS             *Mac,
 357   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 358   )
 359 {
 360   IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRL,
 361                       (Mac->Addr[0] & 0xFF) |
 362                       ((Mac->Addr[1] & 0xFF) << 8) |
 363                       ((Mac->Addr[2] & 0xFF) << 16) |
 364                       ((Mac->Addr[3] & 0xFF) << 24)
 365                     );
 366
 367   IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRH,
 368                       (UINT32)(Mac->Addr[4] & 0xFF) |
 369                       ((Mac->Addr[5] & 0xFF) << 8)
 370                     );
 371 }
 372
 373 VOID
 374 Lan9118ReadMacAddress (
 375   OUT EFI_MAC_ADDRESS *MacAddress
 376   )
 377 {
 378   UINT32          MacAddrHighValue;
 379   UINT32          MacAddrLowValue;
 380
 381   // Read the Mac Addr high register
 382   MacAddrHighValue = (IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRH) & 0xFFFF);
 383   // Read the Mac Addr low register
 384   MacAddrLowValue = IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRL);
 385
 386   SetMem (MacAddress, sizeof(*MacAddress), 0);
 387   MacAddress->Addr[0] = (MacAddrLowValue & 0xFF);
 388   MacAddress->Addr[1] = (MacAddrLowValue & 0xFF00) >> 8;
 389   MacAddress->Addr[2] = (MacAddrLowValue & 0xFF0000) >> 16;
 390   MacAddress->Addr[3] = (MacAddrLowValue & 0xFF000000) >> 24;
 391   MacAddress->Addr[4] = (MacAddrHighValue & 0xFF);
 392   MacAddress->Addr[5] = (MacAddrHighValue & 0xFF00) >> 8;
 393 }
 394
 395 /*
 396  *  Power up the 9118 and find its MAC address.
 397  *
 398  *  This operation can be carried out when the LAN9118 is in any power state
 399  *
 400  */
 401 EFI_STATUS
 402 Lan9118Initialize (
 403   IN  EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 404   )
 405 {
 406   UINTN  Retries;
 407   UINT64 DefaultMacAddress;
 408
 409   // Attempt to wake-up the device if it is in a lower power state
 410   if (((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {
 411     DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));
 412     Lan9118MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);
 413     gBS->Stall (LAN9118_STALL);
 414   }
 415
 416   // Check that device is active
 417   Retries = 20;
 418   while ((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) {
 419     gBS->Stall (LAN9118_STALL);
 420   }
 421   if (!Retries) {
 422     return EFI_TIMEOUT;
 423   }
 424
 425   // Check that EEPROM isn't active
 426   Retries = 20;
 427   while ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){
 428     gBS->Stall (LAN9118_STALL);
 429   }
 430   if (!Retries) {
 431     return EFI_TIMEOUT;
 432   }
 433
 434   // Check if a MAC address was loaded from EEPROM, and if it was, set it as the
 435   // current address.
 436   if ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {
 437     DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n"));
 438
 439     // If we had an address before (set by StationAddess), continue to use it
 440     if (CompareMem (&Snp->Mode->CurrentAddress, &mZeroMac, NET_ETHER_ADDR_LEN)) {
 441       Lan9118SetMacAddress (&Snp->Mode->CurrentAddress, Snp);
 442     } else {
 443       // If there are no cached addresses, then fall back to a default
 444       DEBUG ((EFI_D_WARN, "Warning: using driver-default MAC address\n"));
 445       DefaultMacAddress = FixedPcdGet64 (PcdLan9118DefaultMacAddress);
 446       Lan9118SetMacAddress((EFI_MAC_ADDRESS *) &DefaultMacAddress, Snp);
 447       CopyMem (&Snp->Mode->CurrentAddress, &DefaultMacAddress, NET_ETHER_ADDR_LEN);
 448     }
 449   } else {
 450     // Store the MAC address that was loaded from EEPROM
 451     Lan9118ReadMacAddress (&Snp->Mode->CurrentAddress);
 452     CopyMem (&Snp->Mode->PermanentAddress, &Snp->Mode->CurrentAddress, NET_ETHER_ADDR_LEN);
 453   }
 454
 455   // Clear and acknowledge interrupts
 456   Lan9118MmioWrite32 (LAN9118_INT_EN, 0);
 457   Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);
 458   Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);
 459
 460   // Do self tests here?
 461
 462   return EFI_SUCCESS;
 463 }
 464
 465
 466 // Perform software reset on the LAN9118
 467 // Return 0 on success, -1 on error
 468 EFI_STATUS
 469 SoftReset (
 470   UINT32 Flags,
 471   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 472   )
 473 {
 474   UINT32 HwConf;
 475   UINT32 ResetTime;
 476
 477   // Initialize variable
 478   ResetTime = 0;
 479
 480   // Stop Rx and Tx
 481   StopTx (STOP_TX_MAC | STOP_TX_CFG | STOP_TX_CLEAR, Snp);
 482   StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO
 483
 484   // Issue the reset
 485   HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);
 486   HwConf |= 1;
 487
 488   // Set the Must Be One (MBO) bit
 489   if (((HwConf & HWCFG_MBO) >> 20) == 0) {
 490     HwConf |= HWCFG_MBO;
 491   }
 492
 493   // Check that EEPROM isn't active
 494   while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 495
 496   // Write the configuration
 497   Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);
 498   gBS->Stall (LAN9118_STALL);
 499
 500   // Wait for reset to complete
 501   while (Lan9118MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {
 502
 503     gBS->Stall (LAN9118_STALL);
 504     ResetTime += 1;
 505
 506     // If time taken exceeds 100us, then there was an error condition
 507     if (ResetTime > 1000) {
 508       Snp->Mode->State = EfiSimpleNetworkStopped;
 509       return EFI_TIMEOUT;
 510     }
 511   }
 512
 513   // Check that EEPROM isn't active
 514   while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 515
 516   // TODO we probably need to re-set the mac address here.
 517
 518   // Clear and acknowledge all interrupts
 519   if (Flags & SOFT_RESET_CLEAR_INT) {
 520     Lan9118MmioWrite32 (LAN9118_INT_EN, 0);
 521     Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);
 522     Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);
 523   }
 524
 525   // Do self tests here?
 526   if (Flags & SOFT_RESET_SELF_TEST) {
 527
 528   }
 529
 530   return EFI_SUCCESS;
 531 }
 532
 533
 534 // Perform PHY software reset
 535 EFI_STATUS
 536 PhySoftReset (
 537   UINT32 Flags,
 538   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 539   )
 540 {
 541   UINT32 PmtCtrl = 0;
 542
 543   // PMT PHY reset takes precedence over BCR
 544   if (Flags & PHY_RESET_PMT) {
 545     PmtCtrl = Lan9118MmioRead32 (LAN9118_PMT_CTRL);
 546     PmtCtrl |= MPTCTRL_PHY_RST;
 547     Lan9118MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);
 548
 549     // Wait for completion
 550     while (Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {
 551       gBS->Stall (LAN9118_STALL);
 552     }
 553   // PHY Basic Control Register reset
 554   } else if (Flags & PHY_RESET_BCR) {
 555     IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PHYCR_RESET);
 556
 557     // Wait for completion
 558     while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {
 559       gBS->Stall (LAN9118_STALL);
 560     }
 561   }
 562
 563   // Clear and acknowledge all interrupts
 564   if (Flags & PHY_SOFT_RESET_CLEAR_INT) {
 565     Lan9118MmioWrite32 (LAN9118_INT_EN, 0);
 566     Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);
 567     Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);
 568   }
 569
 570   return EFI_SUCCESS;
 571 }
 572
 573
 574 // Configure hardware for LAN9118
 575 EFI_STATUS
 576 ConfigureHardware (
 577   UINT32 Flags,
 578   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 579   )
 580 {
 581   UINT32 GpioConf;
 582
 583   // Check if we want to use LEDs on GPIO
 584   if (Flags & HW_CONF_USE_LEDS) {
 585     GpioConf = Lan9118MmioRead32 (LAN9118_GPIO_CFG);
 586
 587     // Enable GPIO as LEDs and Config as Push-Pull driver
 588     GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL |
 589                 GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE;
 590
 591     // Write the configuration
 592     Lan9118MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);
 593     gBS->Stall (LAN9118_STALL);
 594   }
 595
 596   return EFI_SUCCESS;
 597 }
 598
 599 // Configure flow control
 600 EFI_STATUS
 601 ConfigureFlow (
 602   UINT32 Flags,
 603   UINT32 HighTrig,
 604   UINT32 LowTrig,
 605   UINT32 BPDuration,
 606   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 607   )
 608 {
 609   return EFI_SUCCESS;
 610 }
 611
 612 // Do auto-negotiation
 613 EFI_STATUS
 614 AutoNegotiate (
 615   UINT32 Flags,
 616   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 617   )
 618 {
 619   UINT32 PhyControl;
 620   UINT32 PhyStatus;
 621   UINT32 Features;
 622   UINT32 Retries;
 623
 624   // First check that auto-negotiation is supported
 625   PhyStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);
 626   if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) {
 627     DEBUG ((EFI_D_ERROR, "Auto-negotiation not supported.\n"));
 628     return EFI_DEVICE_ERROR;
 629   }
 630
 631   // Check that link is up first
 632   if ((PhyStatus & PHYSTS_LINK_STS) == 0) {
 633     // Wait until it is up or until Time Out
 634     Retries = FixedPcdGet32 (PcdLan9118DefaultNegotiationTimeout) / LAN9118_STALL;
 635     while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {
 636       gBS->Stall (LAN9118_STALL);
 637       Retries--;
 638       if (!Retries) {
 639         DEBUG ((EFI_D_ERROR, "Link timeout in auto-negotiation.\n"));
 640         return EFI_TIMEOUT;
 641       }
 642     }
 643   }
 644
 645   // Configure features to advertise
 646   Features = IndirectPHYRead32 (PHY_INDEX_AUTO_NEG_ADVERT);
 647
 648   if ((Flags & AUTO_NEGOTIATE_ADVERTISE_ALL) > 0) {
 649     // Link speed capabilities
 650     Features |= (PHYANA_10BASET | PHYANA_10BASETFD | PHYANA_100BASETX | PHYANA_100BASETXFD);
 651
 652     // Pause frame capabilities
 653     Features &= ~(PHYANA_PAUSE_OP_MASK);
 654     Features |= 3 << 10;
 655   }
 656
 657   // Write the features
 658   IndirectPHYWrite32 (PHY_INDEX_AUTO_NEG_ADVERT, Features);
 659
 660   // Read control register
 661   PhyControl = IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL);
 662
 663   // Enable Auto-Negotiation
 664   if ((PhyControl & PHYCR_AUTO_EN) == 0) {
 665     PhyControl |= PHYCR_AUTO_EN;
 666   }
 667
 668   // Restart auto-negotiation
 669   PhyControl |= PHYCR_RST_AUTO;
 670
 671   // Enable collision test if required to do so
 672   if (Flags & AUTO_NEGOTIATE_COLLISION_TEST) {
 673     PhyControl |= PHYCR_COLL_TEST;
 674   } else {
 675     PhyControl &= ~ PHYCR_COLL_TEST;
 676   }
 677
 678   // Write this configuration
 679   IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PhyControl);
 680
 681   // Wait until process has completed
 682   while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0);
 683
 684   return EFI_SUCCESS;
 685 }
 686
 687 // Check the Link Status and take appropriate action
 688 EFI_STATUS
 689 CheckLinkStatus (
 690   UINT32 Flags,
 691   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 692   )
 693 {
 694   // Get the PHY Status
 695   UINT32 PhyBStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);
 696
 697   if (PhyBStatus & PHYSTS_LINK_STS) {
 698     return EFI_SUCCESS;
 699   } else {
 700     return EFI_DEVICE_ERROR;
 701   }
 702 }
 703
 704 // Stop the transmitter
 705 EFI_STATUS
 706 StopTx (
 707   UINT32 Flags,
 708   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 709   )
 710 {
 711   UINT32 MacCsr;
 712   UINT32 TxCfg;
 713
 714   MacCsr = 0;
 715   TxCfg = 0;
 716
 717   // Check if we want to clear tx
 718   if (Flags & STOP_TX_CLEAR) {
 719     TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);
 720     TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;
 721     Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 722     gBS->Stall (LAN9118_STALL);
 723   }
 724
 725   // Check if already stopped
 726   if (Flags & STOP_TX_MAC) {
 727     MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 728
 729     if (MacCsr & MACCR_TX_EN) {
 730       MacCsr &= ~MACCR_TX_EN;
 731       IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 732     }
 733   }
 734
 735   if (Flags & STOP_TX_CFG) {
 736     TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);
 737
 738     if (TxCfg & TXCFG_TX_ON) {
 739       TxCfg |= TXCFG_STOP_TX;
 740       Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 741       gBS->Stall (LAN9118_STALL);
 742
 743       // Wait for Tx to finish transmitting
 744       while (Lan9118MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);
 745     }
 746   }
 747
 748   return EFI_SUCCESS;
 749 }
 750
 751 // Stop the receiver
 752 EFI_STATUS
 753 StopRx (
 754   UINT32 Flags,
 755   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 756   )
 757 {
 758   UINT32 MacCsr;
 759   UINT32 RxCfg;
 760
 761   RxCfg = 0;
 762
 763   // Check if already stopped
 764   MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 765
 766   if (MacCsr & MACCR_RX_EN) {
 767     MacCsr &= ~ MACCR_RX_EN;
 768     IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 769   }
 770
 771   // Check if we want to clear receiver FIFOs
 772   if (Flags & STOP_RX_CLEAR) {
 773     RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);
 774     RxCfg |= RXCFG_RX_DUMP;
 775     Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);
 776     gBS->Stall (LAN9118_STALL);
 777
 778     while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);
 779   }
 780
 781   return EFI_SUCCESS;
 782 }
 783
 784 // Start the transmitter
 785 EFI_STATUS
 786 StartTx (
 787   UINT32 Flags,
 788   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 789   )
 790 {
 791   UINT32 MacCsr;
 792   UINT32 TxCfg;
 793
 794   MacCsr = 0;
 795   TxCfg = 0;
 796
 797   // Check if we want to clear tx
 798   if (Flags & START_TX_CLEAR) {
 799     TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);
 800     TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;
 801     Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 802     gBS->Stall (LAN9118_STALL);
 803   }
 804
 805   // Check if tx was started from MAC and enable if not
 806   if (Flags & START_TX_MAC) {
 807     MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 808     gBS->Stall (LAN9118_STALL);
 809     if ((MacCsr & MACCR_TX_EN) == 0) {
 810       MacCsr |= MACCR_TX_EN;
 811       IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 812       gBS->Stall (LAN9118_STALL);
 813     }
 814   }
 815
 816   // Check if tx was started from TX_CFG and enable if not
 817   if (Flags & START_TX_CFG) {
 818     TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);
 819     gBS->Stall (LAN9118_STALL);
 820     if ((TxCfg & TXCFG_TX_ON) == 0) {
 821       TxCfg |= TXCFG_TX_ON;
 822       Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 823       gBS->Stall (LAN9118_STALL);
 824     }
 825   }
 826
 827   // Set the tx data trigger level
 828
 829   return EFI_SUCCESS;
 830 }
 831
 832 // Start the receiver
 833 EFI_STATUS
 834 StartRx (
 835   UINT32 Flags,
 836   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 837   )
 838 {
 839   UINT32 MacCsr;
 840   UINT32 RxCfg;
 841
 842   RxCfg = 0;
 843
 844   // Check if already started
 845   MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 846
 847   if ((MacCsr & MACCR_RX_EN) == 0) {
 848     // Check if we want to clear receiver FIFOs before starting
 849     if (Flags & START_RX_CLEAR) {
 850       RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);
 851       RxCfg |= RXCFG_RX_DUMP;
 852       Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);
 853       gBS->Stall (LAN9118_STALL);
 854
 855       while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);
 856     }
 857
 858     MacCsr |= MACCR_RX_EN;
 859     IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 860     gBS->Stall (LAN9118_STALL);
 861   }
 862
 863   return EFI_SUCCESS;
 864 }
 865
 866 // Check Tx Data available space
 867 UINT32
 868 TxDataFreeSpace (
 869   UINT32 Flags,
 870   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 871   )
 872 {
 873   UINT32 TxInf;
 874   UINT32 FreeSpace;
 875
 876   // Get the amount of free space from information register
 877   TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);
 878   FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK);
 879
 880   return FreeSpace; // Value in bytes
 881 }
 882
 883 // Check Tx Status used space
 884 UINT32
 885 TxStatusUsedSpace (
 886   UINT32 Flags,
 887   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 888   )
 889 {
 890   UINT32 TxInf;
 891   UINT32 UsedSpace;
 892
 893   // Get the amount of used space from information register
 894   TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);
 895   UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16;
 896
 897   return UsedSpace << 2; // Value in bytes
 898 }
 899
 900 // Check Rx Data used space
 901 UINT32
 902 RxDataUsedSpace (
 903   UINT32 Flags,
 904   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 905   )
 906 {
 907   UINT32 RxInf;
 908   UINT32 UsedSpace;
 909
 910   // Get the amount of used space from information register
 911   RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);
 912   UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK);
 913
 914   return UsedSpace; // Value in bytes (rounded up to nearest DWORD)
 915 }
 916
 917 // Check Rx Status used space
 918 UINT32
 919 RxStatusUsedSpace (
 920   UINT32 Flags,
 921   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 922   )
 923 {
 924   UINT32 RxInf;
 925   UINT32 UsedSpace;
 926
 927   // Get the amount of used space from information register
 928   RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);
 929   UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16;
 930
 931   return UsedSpace << 2; // Value in bytes
 932 }
 933
 934
 935 // Change the allocation of FIFOs
 936 EFI_STATUS
 937 ChangeFifoAllocation (
 938   IN      UINT32 Flags,
 939   IN  OUT UINTN  *TxDataSize    OPTIONAL,
 940   IN  OUT UINTN  *RxDataSize    OPTIONAL,
 941   IN  OUT UINT32 *TxStatusSize  OPTIONAL,
 942   IN  OUT UINT32 *RxStatusSize  OPTIONAL,
 943   IN  OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 944   )
 945 {
 946   UINT32 HwConf;
 947   UINT32 TxFifoOption;
 948
 949   // Check that desired sizes don't exceed limits
 950   if (*TxDataSize > TX_FIFO_MAX_SIZE)
 951     return EFI_INVALID_PARAMETER;
 952
 953 #if defined(RX_FIFO_MIN_SIZE) && defined(RX_FIFO_MAX_SIZE)
 954   if (*RxDataSize > RX_FIFO_MAX_SIZE) {
 955     return EFI_INVALID_PARAMETER;
 956   }
 957 #endif
 958
 959   if (Flags & ALLOC_USE_DEFAULT) {
 960     return EFI_SUCCESS;
 961   }
 962
 963   // If we use the FIFOs (always use this first)
 964   if (Flags & ALLOC_USE_FIFOS) {
 965     // Read the current value of allocation
 966     HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);
 967     TxFifoOption = (HwConf >> 16) & 0xF;
 968
 969     // Choose the correct size (always use larger than requested if possible)
 970     if (*TxDataSize < TX_FIFO_MIN_SIZE) {
 971       *TxDataSize = TX_FIFO_MIN_SIZE;
 972       *RxDataSize = 13440;
 973       *RxStatusSize = 896;
 974       TxFifoOption = 2;
 975     } else if ((*TxDataSize > TX_FIFO_MIN_SIZE) && (*TxDataSize <= 2560)) {
 976       *TxDataSize = 2560;
 977       *RxDataSize = 12480;
 978       *RxStatusSize = 832;
 979       TxFifoOption = 3;
 980     } else if ((*TxDataSize > 2560) && (*TxDataSize <= 3584)) {
 981       *TxDataSize = 3584;
 982       *RxDataSize = 11520;
 983       *RxStatusSize = 768;
 984       TxFifoOption = 4;
 985     } else if ((*TxDataSize > 3584) && (*TxDataSize <= 4608)) { // default option
 986       *TxDataSize = 4608;
 987       *RxDataSize = 10560;
 988       *RxStatusSize = 704;
 989       TxFifoOption = 5;
 990     } else if ((*TxDataSize > 4608) && (*TxDataSize <= 5632)) {
 991       *TxDataSize = 5632;
 992       *RxDataSize = 9600;
 993       *RxStatusSize = 640;
 994       TxFifoOption = 6;
 995     } else if ((*TxDataSize > 5632) && (*TxDataSize <= 6656)) {
 996       *TxDataSize = 6656;
 997       *RxDataSize = 8640;
 998       *RxStatusSize = 576;
 999       TxFifoOption = 7;
1000     } else if ((*TxDataSize > 6656) && (*TxDataSize <= 7680)) {
1001       *TxDataSize = 7680;
1002       *RxDataSize = 7680;
1003       *RxStatusSize = 512;
1004       TxFifoOption = 8;
1005     } else if ((*TxDataSize > 7680) && (*TxDataSize <= 8704)) {
1006       *TxDataSize = 8704;
1007       *RxDataSize = 6720;
1008       *RxStatusSize = 448;
1009       TxFifoOption = 9;
1010     } else if ((*TxDataSize > 8704) && (*TxDataSize <= 9728)) {
1011       *TxDataSize = 9728;
1012       *RxDataSize = 5760;
1013       *RxStatusSize = 384;
1014       TxFifoOption = 10;
1015     } else if ((*TxDataSize > 9728) && (*TxDataSize <= 10752)) {
1016       *TxDataSize = 10752;
1017       *RxDataSize = 4800;
1018       *RxStatusSize = 320;
1019       TxFifoOption = 11;
1020     } else if ((*TxDataSize > 10752) && (*TxDataSize <= 11776)) {
1021       *TxDataSize = 11776;
1022       *RxDataSize = 3840;
1023       *RxStatusSize = 256;
1024       TxFifoOption = 12;
1025     } else if ((*TxDataSize > 11776) && (*TxDataSize <= 12800)) {
1026       *TxDataSize = 12800;
1027       *RxDataSize = 2880;
1028       *RxStatusSize = 192;
1029       TxFifoOption = 13;
1030     } else if ((*TxDataSize > 12800) && (*TxDataSize <= 13824)) {
1031       *TxDataSize = 13824;
1032       *RxDataSize = 1920;
1033       *RxStatusSize = 128;
1034       TxFifoOption = 14;
1035     }
1036   } else {
1037     ASSERT(0); // Untested code path
1038     HwConf = 0;
1039     TxFifoOption = 0;
1040   }
1041
1042   // Do we need DMA?
1043   if (Flags & ALLOC_USE_DMA) {
1044     return EFI_UNSUPPORTED; // Unsupported as of now
1045   }
1046   // Clear and assign the new size option
1047   HwConf &= ~(0xF0000);
1048   HwConf |= ((TxFifoOption & 0xF) << 16);
1049   Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);
1050   gBS->Stall (LAN9118_STALL);
1051
1052   return EFI_SUCCESS;
1053 }