IntelFrameworkPkg/Include/Protocol/SmmCpuSaveState.h

   1 /** @file
   2   This file declares the SMM CPU Save State protocol, which provides the processor
   3   save-state information for IA-32 and Itanium processors.
   4
   5 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8   @par Revision Reference:
   9   This Protocol is defined in Framework of EFI SMM Core Interface Spec
  10   Version 0.91.
  11 **/
  12
  13 #ifndef _SMM_CPU_SAVE_STATE_H_
  14 #define _SMM_CPU_SAVE_STATE_H_
  15
  16 #define EFI_SMM_CPU_SAVE_STATE_PROTOCOL_GUID \
  17   { \
  18     0x21f302ad, 0x6e94, 0x471b, {0x84, 0xbc, 0xb1, 0x48, 0x0, 0x40, 0x3a, 0x1d} \
  19   }
  20
  21 typedef struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL  EFI_SMM_CPU_SAVE_STATE_PROTOCOL;
  22
  23 #define EFI_SMM_MIN_REV_ID_x64  0x30006
  24
  25 #pragma pack (1)
  26
  27 ///
  28 /// CPU save-state strcuture for IA32 and X64.
  29 ///
  30 /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because the
  31 /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build
  32 /// breaks on many compilers with high warning levels.  Instead, the UINT8 Reserved[0x200]
  33 /// field has been moved into EFI_SMM_CPU_STATE32.  This maintains binary compatibility for
  34 /// the layout and also maintains source comaptibility for access of all fields in this
  35 /// union.
  36 ///
  37 /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because
  38 /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure.  These
  39 /// have been changed to use the base types defined in the UEFI Specification.
  40 ///
  41 typedef struct {
  42   UINT8   Reserved[0x200];
  43   UINT8   Reserved1[0xf8];  // fe00h
  44   UINT32  SMBASE;           // fef8h
  45   UINT32  SMMRevId;         // fefch
  46   UINT16  IORestart;        // ff00h
  47   UINT16  AutoHALTRestart;  // ff02h
  48   UINT32  IEDBASE;          // ff04h
  49   UINT8   Reserved2[0x98];  // ff08h
  50   UINT32  IOMemAddr;        // ffa0h
  51   UINT32  IOMisc;           // ffa4h
  52   UINT32  _ES;
  53   UINT32  _CS;
  54   UINT32  _SS;
  55   UINT32  _DS;
  56   UINT32  _FS;
  57   UINT32  _GS;
  58   UINT32  _LDTBase;
  59   UINT32  _TR;
  60   UINT32  _DR7;
  61   UINT32  _DR6;
  62   UINT32  _EAX;
  63   UINT32  _ECX;
  64   UINT32  _EDX;
  65   UINT32  _EBX;
  66   UINT32  _ESP;
  67   UINT32  _EBP;
  68   UINT32  _ESI;
  69   UINT32  _EDI;
  70   UINT32  _EIP;
  71   UINT32  _EFLAGS;
  72   UINT32  _CR3;
  73   UINT32  _CR0;
  74 } EFI_SMM_CPU_STATE32;
  75
  76 ///
  77 /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because
  78 /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure.  These
  79 /// have been changed to use the base types defined in the UEFI Specification.
  80 ///
  81 typedef struct {
  82   UINT8   Reserved1[0x1d0];  // fc00h
  83   UINT32  GdtBaseHiDword;    // fdd0h
  84   UINT32  LdtBaseHiDword;    // fdd4h
  85   UINT32  IdtBaseHiDword;    // fdd8h
  86   UINT8   Reserved2[0xc];    // fddch
  87   UINT64  IO_EIP;            // fde8h
  88   UINT8   Reserved3[0x50];   // fdf0h
  89   UINT32  _CR4;              // fe40h
  90   UINT8   Reserved4[0x48];   // fe44h
  91   UINT32  GdtBaseLoDword;    // fe8ch
  92   UINT32  GdtLimit;          // fe90h
  93   UINT32  IdtBaseLoDword;    // fe94h
  94   UINT32  IdtLimit;          // fe98h
  95   UINT32  LdtBaseLoDword;    // fe9ch
  96   UINT32  LdtLimit;          // fea0h
  97   UINT32  LdtInfo;           // fea4h
  98   UINT8   Reserved5[0x50];   // fea8h
  99   UINT32  SMBASE;            // fef8h
 100   UINT32  SMMRevId;          // fefch
 101   UINT16  AutoHALTRestart;   // ff00h
 102   UINT16  IORestart;         // ff02h
 103   UINT32  IEDBASE;           // ff04h
 104   UINT8   Reserved6[0x14];   // ff08h
 105   UINT64  _R15;              // ff1ch
 106   UINT64  _R14;
 107   UINT64  _R13;
 108   UINT64  _R12;
 109   UINT64  _R11;
 110   UINT64  _R10;
 111   UINT64  _R9;
 112   UINT64  _R8;
 113   UINT64  _RAX;              // ff5ch
 114   UINT64  _RCX;
 115   UINT64  _RDX;
 116   UINT64  _RBX;
 117   UINT64  _RSP;
 118   UINT64  _RBP;
 119   UINT64  _RSI;
 120   UINT64  _RDI;
 121   UINT64  IOMemAddr;         // ff9ch
 122   UINT32  IOMisc;            // ffa4h
 123   UINT32  _ES;               // ffa8h
 124   UINT32  _CS;
 125   UINT32  _SS;
 126   UINT32  _DS;
 127   UINT32  _FS;
 128   UINT32  _GS;
 129   UINT32  _LDTR;             // ffc0h
 130   UINT32  _TR;
 131   UINT64  _DR7;              // ffc8h
 132   UINT64  _DR6;
 133   UINT64  _RIP;              // ffd8h
 134   UINT64  IA32_EFER;         // ffe0h
 135   UINT64  _RFLAGS;           // ffe8h
 136   UINT64  _CR3;              // fff0h
 137   UINT64  _CR0;              // fff8h
 138 } EFI_SMM_CPU_STATE64;
 139
 140 ///
 141 /// Union of CPU save-state strcutures for IA32 and X64.
 142 ///
 143 /// This union declaration does not exctly match the Framework SMM CIS 0.91 because the
 144 /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build
 145 /// breaks on many compilers with high warning levels.  Instead, the UINT8 Reserved[0x200]
 146 /// field has been moved into EFI_SMM_CPU_STATE32.  This maintains binary compatibility for
 147 /// the layout and also maintains source comaptibility for access of all fields in this
 148 /// union.
 149 ///
 150 typedef union  {
 151   EFI_SMM_CPU_STATE32  x86;
 152   EFI_SMM_CPU_STATE64  x64;
 153 } EFI_SMM_CPU_STATE;
 154
 155 #pragma pack ()
 156
 157 ///
 158 /// Provides a programatic means to access SMM save state.
 159 ///
 160 struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL {
 161   ///
 162   /// Reference to a list of save states.
 163   ///
 164   EFI_SMM_CPU_STATE  **CpuSaveState;
 165 };
 166
 167 extern EFI_GUID gEfiSmmCpuSaveStateProtocolGuid;
 168
 169 #endif