IntelFsp2Pkg/IntelFsp2Pkg.dec

   1 ## @file
   2 # Provides driver and definitions to build fsp in EDKII bios.
   3 #
   4 # Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
   5 # SPDX-License-Identifier: BSD-2-Clause-Patent
   6 #
   7 ##
   8
   9 [Defines]
  10   DEC_SPECIFICATION              = 0x00010005
  11   PACKAGE_NAME                   = IntelFsp2Pkg
  12   PACKAGE_GUID                   = A8C53B5E-D556-4F3E-874D-0D6FA2CDC7BF
  13   PACKAGE_VERSION                = 0.1
  14
  15 [Includes]
  16   Include
  17
  18 [LibraryClasses]
  19   ##  @libraryclass  Provides cache-as-ram support.
  20   CacheAsRamLib|Include/Library/CacheAsRamLib.h
  21
  22   ##  @libraryclass  Provides cache setting on MTRR.
  23   CacheLib|Include/Library/CacheLib.h
  24
  25   ##  @libraryclass  Provides debug device abstraction.
  26   DebugDeviceLib|Include/Library/DebugDeviceLib.h
  27
  28   ##  @libraryclass  Provides FSP related services.
  29   FspCommonLib|Include/Library/FspCommonLib.h
  30
  31   ##  @libraryclass  Provides FSP platform related actions.
  32   FspPlatformLib|Include/Library/FspPlatformLib.h
  33
  34   ##  @libraryclass  Provides FSP switch stack function.
  35   FspSwitchStackLib|Include/Library/FspSwitchStackLib.h
  36
  37   ##  @libraryclass  Provides FSP platform sec related actions.
  38   FspSecPlatformLib|Include/Library/FspSecPlatformLib.h
  39
  40 [Ppis]
  41   #
  42   # PPI to indicate FSP is ready to enter notify phase
  43   # This provides flexibility for any late initialization that must be done right before entering notify phase.
  44   #
  45   gFspReadyForNotifyPhasePpiGuid        = { 0xcd167c1e, 0x6e0b, 0x42b3, {0x82, 0xf6, 0xe3, 0xe9, 0x06, 0x19, 0x98, 0x10}}
  46
  47   #
  48   # PPI as dependency on some modules which only required for API mode
  49   #
  50   gFspInApiModePpiGuid                  = { 0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5, 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}}
  51
  52   #
  53   # PPI for Architectural configuration data for FSP-M
  54   #
  55   gFspmArchConfigPpiGuid                = { 0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}
  56
  57   #
  58   # PPI to tear down the temporary memory set up by TempRamInit ().
  59   #
  60   gFspTempRamExitPpiGuid                = { 0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
  61
  62   #
  63   # PPI for Variable Services
  64   #
  65   gEdkiiPeiVariablePpiGuid              = { 0xe7b2cd04, 0x4b14, 0x44c2, {0xb7, 0x48, 0xce, 0xaf, 0x2b, 0x66, 0x4a, 0xb0}}
  66
  67
  68 [Guids]
  69   #
  70   # GUID defined in package
  71   #
  72   gIntelFsp2PkgTokenSpaceGuid           = { 0xed6e0531, 0xf715, 0x4a3d, { 0x9b, 0x12, 0xc1, 0xca, 0x5e, 0xf6, 0x98, 0xa2 } }
  73
  74   # Guid define in FSP EAS
  75   gFspHeaderFileGuid                    = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }
  76   gFspReservedMemoryResourceHobGuid     = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }
  77   gFspNonVolatileStorageHob2Guid        = { 0x4866788f, 0x6ba8, 0x47d8, { 0x83, 0x06, 0xac, 0xf7, 0x7f, 0x55, 0x10, 0x46 } }
  78   gFspNonVolatileStorageHobGuid         = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
  79   gFspBootLoaderTolumHobGuid            = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1
  80
  81   gFspPerformanceDataGuid               = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }
  82   gFspEventEndOfFirmwareGuid            = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
  83
  84 [PcdsFixedAtBuild]
  85   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001
  86   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase         |0xFEF00000|UINT32|0x10001001
  87   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize         |    0x2000|UINT32|0x10001002
  88   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize      |    0x1000|UINT32|0x10001003
  89   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize    |     0x100|UINT32|0x10001004
  90   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry          |        32|UINT32|0x00002001
  91   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry         |         6|UINT32|0x00002002
  92   gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaBaseAddress       |0xFFF80000|UINT32|0x10000001
  93   gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaSize              |0x00040000|UINT32|0x10000002
  94   gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003
  95   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion     |      0x20| UINT8|0x00000002
  96
  97   #
  98   # x % of FSP temporary memory will be used for heap
  99   # (100 - x) % of FSP temporary memory will be used for stack
 100   # 0 means FSP will share the stack with boot loader and FSP temporary memory is heap
 101   #   Note: This mode assumes boot loader stack is large enough for FSP to use.
 102   #
 103   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage    |        50| UINT8|0x10000004
 104   #
 105   # Maximal Interrupt supported in IDT table.
 106   #
 107   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported |        34| UINT8|0x10000005
 108   #
 109   # Allows FSP-M to reserve a section of Temporary RAM for implementation specific use.
 110   # Reduces the amount of memory available for the PeiCore heap.
 111   #
 112   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize |0x00000000|UINT32|0x10000006
 113
 114 [PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]
 115   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000
 116   gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry         |0xFFFFFFE4|UINT32|0x46530100