IntelSiliconPkg/IgdOpRegion: Add definition for Intel IGD
[mirror_edk2.git] / IntelSiliconPkg / Include / IndustryStandard / IgdOpRegion.h
1 /** @file
2 IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
3 Specification.
4
5 https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf
6
7 There are some mismatch between the specification and the implementation.
8 The definition follows the latest implementation.
9 1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]
10 2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]
11 3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]
12 4) INTEL_IGD_OPREGION_VBT.RVBT[0x1C00]
13
14 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
15 This program and the accompanying materials
16 are licensed and made available under the terms and conditions of the BSD License
17 which accompanies this distribution. The full text of the license may be found at
18 http://opensource.org/licenses/bsd-license.php
19
20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
21 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22
23 **/
24 #ifndef _IGD_OPREGION_H_
25 #define _IGD_OPREGION_H_
26
27 /**
28 OpRegion structures:
29 Sub-structures define the different parts of the OpRegion followed by the
30 main structure representing the entire OpRegion.
31
32 Note: These structures are packed to 1 byte offsets because the exact
33 data location is requred by the supporting design specification due to
34 the fact that the data is used by ASL and Graphics driver code compiled
35 separatly.
36 **/
37 #pragma pack(1)
38 ///
39 /// OpRegion header (mailbox 0) structure and defines.
40 ///
41 typedef struct {
42 CHAR8 SIGN[0x10]; ///< Offset 0 OpRegion Signature
43 UINT32 SIZE; ///< Offset 16 OpRegion Size
44 UINT32 OVER; ///< Offset 20 OpRegion Structure Version
45 UINT8 SVER[0x20]; ///< Offset 24 System BIOS Build Version
46 UINT8 VVER[0x10]; ///< Offset 56 Video BIOS Build Version
47 UINT8 GVER[0x10]; ///< Offset 72 Graphic Driver Build Version
48 UINT32 MBOX; ///< Offset 88 Supported Mailboxes
49 UINT32 DMOD; ///< Offset 92 Driver Model
50 UINT8 RSV1[0xA0]; ///< Offset 96 Reserved
51 } INTEL_IGD_OPREGION_HEADER;
52
53 ///
54 /// OpRegion mailbox 1 (public ACPI Methods).
55 ///
56 typedef struct {
57 UINT32 DRDY; ///< Offset 0 Driver Readiness
58 UINT32 CSTS; ///< Offset 4 Status
59 UINT32 CEVT; ///< Offset 8 Current Event
60 UINT8 RSV2[0x14]; ///< Offset 12 Reserved
61 UINT32 DIDL[8]; ///< Offset 32 Supported Display Devices ID List
62 UINT32 CPDL[8]; ///< Offset 64 Currently Attached Display Devices List
63 UINT32 CADL[8]; ///< Offset 96 Currently Active Display Devices List
64 UINT32 NADL[8]; ///< Offset 128 Next Active Devices List
65 UINT32 ASLP; ///< Offset 160 ASL Sleep Time Out
66 UINT32 TIDX; ///< Offset 164 Toggle Table Index
67 UINT32 CHPD; ///< Offset 168 Current Hotplug Enable Indicator
68 UINT32 CLID; ///< Offset 172 Current Lid State Indicator
69 UINT32 CDCK; ///< Offset 176 Current Docking State Indicator
70 UINT32 SXSW; ///< Offset 180 Display Switch Notification on Sx State Resume
71 UINT32 EVTS; ///< Offset 184 Events supported by ASL
72 UINT32 CNOT; ///< Offset 188 Current OS Notification
73 UINT32 NRDY; ///< Offset 192 Driver Status
74 UINT8 RSV3[0x3C]; ///< Offset 196 Reserved
75 } INTEL_IGD_OPREGION_MBOX1;
76
77 ///
78 /// OpRegion mailbox 2 (Software SCI Interface).
79 ///
80 typedef struct {
81 UINT32 SCIC; ///< Offset 0 Software SCI Command / Status / Data
82 UINT32 PARM; ///< Offset 4 Software SCI Parameters
83 UINT32 DSLP; ///< Offset 8 Driver Sleep Time Out
84 UINT8 RSV4[0xF4]; ///< Offset 12 Reserved
85 } INTEL_IGD_OPREGION_MBOX2;
86
87 ///
88 /// OpRegion mailbox 3 (BIOS/Driver Communication - ASLE Support).
89 ///
90 typedef struct {
91 UINT32 ARDY; ///< Offset 0 Driver Readiness
92 UINT32 ASLC; ///< Offset 4 ASLE Interrupt Command / Status
93 UINT32 TCHE; ///< Offset 8 Technology Enabled Indicator
94 UINT32 ALSI; ///< Offset 12 Current ALS Luminance Reading
95 UINT32 BCLP; ///< Offset 16 Requested Backlight Britness
96 UINT32 PFIT; ///< Offset 20 Panel Fitting State or Request
97 UINT32 CBLV; ///< Offset 24 Current Brightness Level
98 UINT16 BCLM[0x14]; ///< Offset 28 Backlight Brightness Levels Duty Cycle Mapping Table
99 UINT32 CPFM; ///< Offset 68 Current Panel Fitting Mode
100 UINT32 EPFM; ///< Offset 72 Enabled Panel Fitting Modes
101 UINT8 PLUT[0x4A]; ///< Offset 76 Panel Look Up Table & Identifier
102 UINT32 PFMB; ///< Offset 150 PWM Frequency and Minimum Brightness
103 UINT32 CCDV; ///< Offset 154 Color Correction Default Values
104 UINT8 RSV5[0x62]; ///< Offset 158 Reserved
105 } INTEL_IGD_OPREGION_MBOX3;
106
107 ///
108 /// OpRegion mailbox 4 (VBT).
109 ///
110 typedef struct {
111 UINT8 RVBT[0x1C00]; ///< Offset 0 Raw VBT Data
112 } INTEL_IGD_OPREGION_VBT;
113
114 ///
115 /// IGD OpRegion Structure
116 ///
117 typedef struct {
118 INTEL_IGD_OPREGION_HEADER Header; ///< OpRegion header
119 INTEL_IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods
120 INTEL_IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Inteface
121 INTEL_IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS/Driver Communication
122 INTEL_IGD_OPREGION_VBT VBT; ///< VBT: Video BIOS Table (OEM customizable data)
123 } IGD_IGD_OPREGION_STRUCTURE;
124 #pragma pack()
125
126 #endif