IntelSiliconPkg/dec: Add VTd policy PCD
[mirror_edk2.git] / IntelSiliconPkg / Include / IndustryStandard / Vtd.h
1 /** @file
2 The definition for VTD register.
3 It is defined in "Intel VT for Direct IO Architecture Specification".
4
5 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef __VTD_REG_H__
17 #define __VTD_REG_H__
18
19 #pragma pack(1)
20
21 //
22 // Translation Structure Formats
23 //
24 #define VTD_ROOT_ENTRY_NUMBER 256
25 #define VTD_CONTEXT_ENTRY_NUMBER 256
26
27 typedef union {
28 struct {
29 UINT32 Present:1;
30 UINT32 Reserved_1:11;
31 UINT32 ContextTablePointerLo:20;
32 UINT32 ContextTablePointerHi:32;
33
34 UINT64 Reserved_64;
35 } Bits;
36 struct {
37 UINT64 Uint64Lo;
38 UINT64 Uint64Hi;
39 } Uint128;
40 } VTD_ROOT_ENTRY;
41
42 typedef union {
43 struct {
44 UINT32 LowerPresent:1;
45 UINT32 Reserved_1:11;
46 UINT32 LowerContextTablePointerLo:20;
47 UINT32 LowerContextTablePointerHi:32;
48
49 UINT32 UpperPresent:1;
50 UINT32 Reserved_65:11;
51 UINT32 UpperContextTablePointerLo:20;
52 UINT32 UpperContextTablePointerHi:32;
53 } Bits;
54 struct {
55 UINT64 Uint64Lo;
56 UINT64 Uint64Hi;
57 } Uint128;
58 } VTD_EXT_ROOT_ENTRY;
59
60 typedef union {
61 struct {
62 UINT32 Present:1;
63 UINT32 FaultProcessingDisable:1;
64 UINT32 TranslationType:2;
65 UINT32 Reserved_4:8;
66 UINT32 SecondLevelPageTranslationPointerLo:20;
67 UINT32 SecondLevelPageTranslationPointerHi:32;
68
69 UINT32 AddressWidth:3;
70 UINT32 Ignored_67:4;
71 UINT32 Reserved_71:1;
72 UINT32 DomainIdentifier:16;
73 UINT32 Reserved_88:8;
74 UINT32 Reserved_96:32;
75 } Bits;
76 struct {
77 UINT64 Uint64Lo;
78 UINT64 Uint64Hi;
79 } Uint128;
80 } VTD_CONTEXT_ENTRY;
81
82 typedef union {
83 struct {
84 UINT32 Present:1;
85 UINT32 FaultProcessingDisable:1;
86 UINT32 TranslationType:3;
87 UINT32 ExtendedMemoryType:3;
88 UINT32 DeferredInvalidateEnable:1;
89 UINT32 PageRequestEnable:1;
90 UINT32 NestedTranslationEnable:1;
91 UINT32 PASIDEnable:1;
92 UINT32 SecondLevelPageTranslationPointerLo:20;
93 UINT32 SecondLevelPageTranslationPointerHi:32;
94
95 UINT32 AddressWidth:3;
96 UINT32 PageGlobalEnable:1;
97 UINT32 NoExecuteEnable:1;
98 UINT32 WriteProtectEnable:1;
99 UINT32 CacheDisable:1;
100 UINT32 ExtendedMemoryTypeEnable:1;
101 UINT32 DomainIdentifier:16;
102 UINT32 SupervisorModeExecuteProtection:1;
103 UINT32 ExtendedAccessedFlagEnable:1;
104 UINT32 ExecuteRequestsEnable:1;
105 UINT32 SecondLevelExecuteEnable:1;
106 UINT32 Reserved_92:4;
107 UINT32 PageAttributeTable0:3;
108 UINT32 Reserved_Pat0:1;
109 UINT32 PageAttributeTable1:3;
110 UINT32 Reserved_Pat1:1;
111 UINT32 PageAttributeTable2:3;
112 UINT32 Reserved_Pat2:1;
113 UINT32 PageAttributeTable3:3;
114 UINT32 Reserved_Pat3:1;
115 UINT32 PageAttributeTable4:3;
116 UINT32 Reserved_Pat4:1;
117 UINT32 PageAttributeTable5:3;
118 UINT32 Reserved_Pat5:1;
119 UINT32 PageAttributeTable6:3;
120 UINT32 Reserved_Pat6:1;
121 UINT32 PageAttributeTable7:3;
122 UINT32 Reserved_Pat7:1;
123
124 UINT32 PASIDTableSize:4;
125 UINT32 Reserved_132:8;
126 UINT32 PASIDTablePointerLo:20;
127 UINT32 PASIDTablePointerHi:32;
128
129 UINT32 Reserved_192:12;
130 UINT32 PASIDStateTablePointerLo:20;
131 UINT32 PASIDStateTablePointerHi:32;
132 } Bits;
133 struct {
134 UINT64 Uint64_1;
135 UINT64 Uint64_2;
136 UINT64 Uint64_3;
137 UINT64 Uint64_4;
138 } Uint256;
139 } VTD_EXT_CONTEXT_ENTRY;
140
141 typedef union {
142 struct {
143 UINT32 Present:1;
144 UINT32 Reserved_1:2;
145 UINT32 PageLevelCacheDisable:1;
146 UINT32 PageLevelWriteThrough:1;
147 UINT32 Reserved_5:6;
148 UINT32 SupervisorRequestsEnable:1;
149 UINT32 FirstLevelPageTranslationPointerLo:20;
150 UINT32 FirstLevelPageTranslationPointerHi:32;
151 } Bits;
152 UINT64 Uint64;
153 } VTD_PASID_ENTRY;
154
155 typedef union {
156 struct {
157 UINT32 Reserved_0:32;
158 UINT32 ActiveReferenceCount:16;
159 UINT32 Reserved_48:15;
160 UINT32 DeferredInvalidate:1;
161 } Bits;
162 UINT64 Uint64;
163 } VTD_PASID_STATE_ENTRY;
164
165 typedef union {
166 struct {
167 UINT32 Present:1;
168 UINT32 ReadWrite:1;
169 UINT32 UserSupervisor:1;
170 UINT32 PageLevelWriteThrough:1;
171 UINT32 PageLevelCacheDisable:1;
172 UINT32 Accessed:1;
173 UINT32 Dirty:1;
174 UINT32 PageSize:1; // It is PageAttribute:1 for 4K page entry
175 UINT32 Global:1;
176 UINT32 Ignored_9:1;
177 UINT32 ExtendedAccessed:1;
178 UINT32 Ignored_11:1;
179 // NOTE: There is PageAttribute:1 as bit12 for 1G page entry and 2M page entry
180 UINT32 AddressLo:20;
181 UINT32 AddressHi:20;
182 UINT32 Ignored_52:11;
183 UINT32 ExecuteDisable:1;
184 } Bits;
185 UINT64 Uint64;
186 } VTD_FIRST_LEVEL_PAGING_ENTRY;
187
188 typedef union {
189 struct {
190 UINT32 Read:1;
191 UINT32 Write:1;
192 UINT32 Execute:1;
193 UINT32 ExtendedMemoryType:3;
194 UINT32 IgnorePAT:1;
195 UINT32 PageSize:1;
196 UINT32 Ignored_8:3;
197 UINT32 Snoop:1;
198 UINT32 AddressLo:20;
199 UINT32 AddressHi:20;
200 UINT32 Ignored_52:10;
201 UINT32 TransientMapping:1;
202 UINT32 Ignored_63:1;
203 } Bits;
204 UINT64 Uint64;
205 } VTD_SECOND_LEVEL_PAGING_ENTRY;
206
207 //
208 // Register Descriptions
209 //
210 #define R_VER_REG 0x00
211 #define R_CAP_REG 0x08
212 #define B_CAP_REG_RWBF BIT4
213 #define R_ECAP_REG 0x10
214 #define R_GCMD_REG 0x18
215 #define B_GMCD_REG_WBF BIT27
216 #define B_GMCD_REG_SRTP BIT30
217 #define B_GMCD_REG_TE BIT31
218 #define R_GSTS_REG 0x1C
219 #define B_GSTS_REG_WBF BIT27
220 #define B_GSTS_REG_RTPS BIT30
221 #define B_GSTS_REG_TE BIT31
222 #define R_RTADDR_REG 0x20
223 #define R_CCMD_REG 0x28
224 #define B_CCMD_REG_CIRG_MASK (BIT62|BIT61)
225 #define V_CCMD_REG_CIRG_GLOBAL BIT61
226 #define V_CCMD_REG_CIRG_DOMAIN BIT62
227 #define V_CCMD_REG_CIRG_DEVICE (BIT62|BIT61)
228 #define B_CCMD_REG_ICC BIT63
229 #define R_FSTS_REG 0x34
230 #define R_FECTL_REG 0x38
231 #define R_FEDATA_REG 0x3C
232 #define R_FEADDR_REG 0x40
233 #define R_FEUADDR_REG 0x44
234 #define R_AFLOG_REG 0x58
235
236 #define R_IVA_REG 0x00 // + IRO
237 #define B_IVA_REG_AM_MASK (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5)
238 #define B_IVA_REG_AM_4K 0 // 1 page
239 #define B_IVA_REG_AM_2M 9 // 2M page
240 #define B_IVA_REG_IH BIT6
241 #define R_IOTLB_REG 0x08 // + IRO
242 #define B_IOTLB_REG_IIRG_MASK (BIT61|BIT60)
243 #define V_IOTLB_REG_IIRG_GLOBAL BIT60
244 #define V_IOTLB_REG_IIRG_DOMAIN BIT61
245 #define V_IOTLB_REG_IIRG_PAGE (BIT61|BIT60)
246 #define B_IOTLB_REG_IVT BIT63
247
248 #define R_FRCD_REG 0x00 // + FRO
249
250 typedef union {
251 struct {
252 UINT8 ND:3; // Number of domains supported
253 UINT8 AFL:1; // Advanced Fault Logging
254 UINT8 RWBF:1; // Required Write-Buffer Flushing
255 UINT8 PLMR:1; // Protected Low-Memory Region
256 UINT8 PHMR:1; // Protected High-Memory Region
257 UINT8 CM:1; // Caching Mode
258
259 UINT8 SAGAW:5; // Supported Adjusted Guest Address Widths
260 UINT8 Rsvd_13:3;
261
262 UINT8 MGAW:6; // Maximum Guest Address Width
263 UINT8 ZLR:1; // Zero Length Read
264 UINT8 Rsvd_23:1;
265
266 UINT16 FRO:10; // Fault-recording Register offset
267 UINT16 SLLPS:4; // Second Level Large Page Support
268 UINT16 Rsvd_38:1;
269 UINT16 PSI:1; // Page Selective Invalidation
270
271 UINT8 NFR:8; // Number of Fault-recording Registers
272
273 UINT8 MAMV:6; // Maximum Address Mask Value
274 UINT8 DWD:1; // Write Draining
275 UINT8 DRD:1; // Read Draining
276
277 UINT8 FL1GP:1; // First Level 1-GByte Page Support
278 UINT8 Rsvd_57:2;
279 UINT8 PI:1; // Posted Interrupts Support
280 UINT8 Rsvd_60:4;
281 } Bits;
282 UINT64 Uint64;
283 } VTD_CAP_REG;
284
285 typedef union {
286 struct {
287 UINT8 C:1; // Page-walk Coherency
288 UINT8 QI:1; // Queued Invalidation support
289 UINT8 DT:1; // Device-TLB support
290 UINT8 IR:1; // Interrupt Remapping support
291 UINT8 EIM:1; // Extended Interrupt Mode
292 UINT8 Rsvd_5:1;
293 UINT8 PT:1; // Pass Through
294 UINT8 SC:1; // Snoop Control
295
296 UINT16 IRO:10; // IOTLB Register Offset
297 UINT16 Rsvd_18:2;
298 UINT16 MHMV:4; // Maximum Handle Mask Value
299
300 UINT8 ECS:1; // Extended Context Support
301 UINT8 MTS:1; // Memory Type Support
302 UINT8 NEST:1; // Nested Translation Support
303 UINT8 DIS:1; // Deferred Invalidate Support
304 UINT8 PASID:1; // Process Address Space ID Support
305 UINT8 PRS:1; // Page Request Support
306 UINT8 ERS:1; // Execute Request Support
307 UINT8 SRS:1; // Supervisor Request Support
308
309 UINT32 Rsvd_32:1;
310 UINT32 NWFS:1; // No Write Flag Support
311 UINT32 EAFS:1; // Extended Accessed Flag Support
312 UINT32 PSS:5; // PASID Size Supported
313 UINT32 Rsvd_40:24;
314 } Bits;
315 UINT64 Uint64;
316 } VTD_ECAP_REG;
317
318 typedef union {
319 struct {
320 UINT32 Rsvd_0:12;
321 UINT32 FILo:20; // FaultInfo
322 UINT32 FIHi:32; // FaultInfo
323
324 UINT32 SID:16; // Source Identifier
325 UINT32 Rsvd_80:13;
326 UINT32 PRIV:1; // Privilege Mode Requested
327 UINT32 EXE:1; // Execute Permission Requested
328 UINT32 PP:1; // PASID Present
329
330 UINT32 FR:8; // Fault Reason
331 UINT32 PV:20; // PASID Value
332 UINT32 AT:2; // Address Type
333 UINT32 T:1; // Type (0: Write, 1: Read)
334 UINT32 F:1; // Fault
335 } Bits;
336 UINT64 Uint64[2];
337 } VTD_FRCD_REG;
338
339 typedef union {
340 struct {
341 UINT8 Function:3;
342 UINT8 Device:5;
343 UINT8 Bus;
344 } Bits;
345 struct {
346 UINT8 ContextIndex;
347 UINT8 RootIndex;
348 } Index;
349 UINT16 Uint16;
350 } VTD_SOURCE_ID;
351
352 #pragma pack()
353
354 #endif
355