2 Private Header file for Usb Host Controller PEIM
4 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions
8 of the BSD License which accompanies this distribution. The
9 full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #ifndef _RECOVERY_EHC_H_
18 #define _RECOVERY_EHC_H_
22 #include <Ppi/UsbController.h>
23 #include <Ppi/Usb2HostController.h>
24 #include <Ppi/IoMmu.h>
25 #include <Ppi/EndOfPeiPhase.h>
27 #include <Library/DebugLib.h>
28 #include <Library/PeimEntryPoint.h>
29 #include <Library/PeiServicesLib.h>
30 #include <Library/BaseMemoryLib.h>
31 #include <Library/TimerLib.h>
32 #include <Library/IoLib.h>
34 typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV
;
36 #define EFI_LIST_ENTRY LIST_ENTRY
41 #include "EhciSched.h"
43 #define EFI_USB_SPEED_FULL 0x0000
44 #define EFI_USB_SPEED_LOW 0x0001
45 #define EFI_USB_SPEED_HIGH 0x0002
49 #define EHC_1_MICROSECOND 1
50 #define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
51 #define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
54 // EHCI register operation timeout, set by experience
56 #define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
57 #define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
61 // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
63 #define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
66 // Sync transfer polling interval, set by experience.
68 #define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)
71 //Iterate through the double linked list. NOT delete safe
73 #define EFI_LIST_FOR_EACH(Entry, ListHead) \
74 for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)
77 //Iterate through the double linked list. This is delete-safe.
78 //Don't touch NextEntry
80 #define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \
81 for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\
82 Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)
84 #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
87 #define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
88 #define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
89 #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
91 #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
92 (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
94 #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')
96 struct _PEI_USB2_HC_DEV
{
98 PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi
;
99 EDKII_IOMMU_PPI
*IoMmu
;
100 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor
;
102 // EndOfPei callback is used to stop the EHC DMA operation
103 // after exit PEI phase.
105 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList
;
106 UINT32 UsbHostControllerBaseAddress
;
108 USBHC_MEM_POOL
*MemPool
;
111 // Schedule data shared between asynchronous and periodic
113 // ShortReadStop, as its name indicates, is used to terminate
114 // the short read except the control transfer. EHCI follows
115 // the alternative next QTD point when a short read happens.
116 // For control transfer, even the short read happens, try the
119 PEI_EHC_QTD
*ShortReadStop
;
123 // Asynchronous(bulk and control) transfer schedule data:
124 // ReclaimHead is used as the head of the asynchronous transfer
125 // list. It acts as the reclamation header.
127 PEI_EHC_QH
*ReclaimHead
;
130 // Periodic (interrupt) transfer schedule data:
132 VOID
*PeriodFrame
; // Mapped as common buffer
133 VOID
*PeriodFrameMap
;
135 PEI_EHC_QH
*PeriodOne
;
136 EFI_LIST_ENTRY AsyncIntTransfers
;
139 // EHCI configuration data
141 UINT32 HcStructParams
; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
142 UINT32 HcCapParams
; // Cache of HC capability parameter, HCCPARAMS
143 UINT32 CapLen
; // Capability length
144 UINT32 High32bitAddr
;
147 #define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
148 #define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)
151 @param EhcDev EHCI Device.
153 @retval EFI_SUCCESS EHCI successfully initialized.
154 @retval EFI_ABORTED EHCI was failed to be initialized.
159 IN PEI_USB2_HC_DEV
*EhcDev
163 Initialize the memory management pool for the host controller.
165 @param Ehc The EHCI device.
166 @param Check4G Whether the host controller requires allocated memory
167 from one 4G address space.
168 @param Which4G The 4G memory area each memory allocated should be from.
170 @retval EFI_SUCCESS The memory pool is initialized.
171 @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.
176 IN PEI_USB2_HC_DEV
*Ehc
,
183 Release the memory management pool.
185 @param Ehc The EHCI device.
186 @param Pool The USB memory pool to free.
188 @retval EFI_DEVICE_ERROR Fail to free the memory pool.
189 @retval EFI_SUCCESS The memory pool is freed.
194 IN PEI_USB2_HC_DEV
*Ehc
,
195 IN USBHC_MEM_POOL
*Pool
200 Allocate some memory from the host controller's memory pool
201 which can be used to communicate with host controller.
203 @param Ehc The EHCI device.
204 @param Pool The host controller's memory pool.
205 @param Size Size of the memory to allocate.
207 @return The allocated memory or NULL.
212 IN PEI_USB2_HC_DEV
*Ehc
,
213 IN USBHC_MEM_POOL
*Pool
,
219 Free the allocated memory back to the memory pool.
221 @param Ehc The EHCI device.
222 @param Pool The memory pool of the host controller.
223 @param Mem The memory to free.
224 @param Size The size of the memory to free.
229 IN PEI_USB2_HC_DEV
*Ehc
,
230 IN USBHC_MEM_POOL
*Pool
,
237 Provides the controller-specific addresses required to access system memory from a
240 @param IoMmu Pointer to IOMMU PPI.
241 @param Operation Indicates if the bus master is going to read or write to system memory.
242 @param HostAddress The system memory address to map to the PCI controller.
243 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
245 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
246 access the hosts HostAddress.
247 @param Mapping A resulting value to pass to Unmap().
249 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
250 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
251 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
252 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
253 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
258 IN EDKII_IOMMU_PPI
*IoMmu
,
259 IN EDKII_IOMMU_OPERATION Operation
,
260 IN VOID
*HostAddress
,
261 IN OUT UINTN
*NumberOfBytes
,
262 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
267 Completes the Map() operation and releases any corresponding resources.
269 @param IoMmu Pointer to IOMMU PPI.
270 @param Mapping The mapping value returned from Map().
275 IN EDKII_IOMMU_PPI
*IoMmu
,
280 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
281 OperationBusMasterCommonBuffer64 mapping.
283 @param IoMmu Pointer to IOMMU PPI.
284 @param Pages The number of pages to allocate.
285 @param HostAddress A pointer to store the base system memory address of the
287 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
288 access the hosts HostAddress.
289 @param Mapping A resulting value to pass to Unmap().
291 @retval EFI_SUCCESS The requested memory pages were allocated.
292 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
293 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
294 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
295 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
299 IoMmuAllocateBuffer (
300 IN EDKII_IOMMU_PPI
*IoMmu
,
302 OUT VOID
**HostAddress
,
303 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
308 Frees memory that was allocated with AllocateBuffer().
310 @param IoMmu Pointer to IOMMU PPI.
311 @param Pages The number of pages to free.
312 @param HostAddress The base system memory address of the allocated range.
313 @param Mapping The mapping value returned from Map().
318 IN EDKII_IOMMU_PPI
*IoMmu
,
320 IN VOID
*HostAddress
,
327 @param IoMmu Pointer to pointer to IOMMU PPI.
332 OUT EDKII_IOMMU_PPI
**IoMmu