MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c

   1 /** @file
   2   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
   3   NVM Express specification.
   4
   5   (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
   6   Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php.
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include "NvmExpress.h"
  18
  19 /**
  20   Dump the execution status from a given completion queue entry.
  21
  22   @param[in]     Cq               A pointer to the NVME_CQ item.
  23
  24 **/
  25 VOID
  26 NvmeDumpStatus (
  27   IN NVME_CQ             *Cq
  28   )
  29 {
  30   DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
  31
  32   DEBUG ((EFI_D_VERBOSE, "  SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));
  33
  34   DEBUG ((EFI_D_VERBOSE, "  NVMe Cmd Execution Result - "));
  35
  36   switch (Cq->Sct) {
  37     case 0x0:
  38       switch (Cq->Sc) {
  39         case 0x0:
  40           DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));
  41           break;
  42         case 0x1:
  43           DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));
  44           break;
  45         case 0x2:
  46           DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));
  47           break;
  48         case 0x3:
  49           DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));
  50           break;
  51         case 0x4:
  52           DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));
  53           break;
  54         case 0x5:
  55           DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));
  56           break;
  57         case 0x6:
  58           DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));
  59           break;
  60         case 0x7:
  61           DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));
  62           break;
  63         case 0x8:
  64           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));
  65           break;
  66         case 0x9:
  67           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));
  68           break;
  69         case 0xA:
  70           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));
  71           break;
  72         case 0xB:
  73           DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));
  74           break;
  75         case 0xC:
  76           DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));
  77           break;
  78         case 0xD:
  79           DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));
  80           break;
  81         case 0xE:
  82           DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));
  83           break;
  84         case 0xF:
  85           DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));
  86           break;
  87         case 0x10:
  88           DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));
  89           break;
  90         case 0x11:
  91           DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));
  92           break;
  93         case 0x80:
  94           DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));
  95           break;
  96         case 0x81:
  97           DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));
  98           break;
  99         case 0x82:
 100           DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));
 101           break;
 102         case 0x83:
 103           DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));
 104           break;
 105       }
 106       break;
 107
 108     case 0x1:
 109       switch (Cq->Sc) {
 110         case 0x0:
 111           DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));
 112           break;
 113         case 0x1:
 114           DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));
 115           break;
 116         case 0x2:
 117           DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));
 118           break;
 119         case 0x3:
 120           DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));
 121           break;
 122         case 0x5:
 123           DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));
 124           break;
 125         case 0x6:
 126           DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));
 127           break;
 128         case 0x7:
 129           DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));
 130           break;
 131         case 0x8:
 132           DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));
 133           break;
 134         case 0x9:
 135           DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));
 136           break;
 137         case 0xA:
 138           DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));
 139           break;
 140         case 0xB:
 141           DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));
 142           break;
 143         case 0xC:
 144           DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));
 145           break;
 146         case 0xD:
 147           DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));
 148           break;
 149         case 0xE:
 150           DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));
 151           break;
 152         case 0xF:
 153           DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));
 154           break;
 155         case 0x10:
 156           DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));
 157           break;
 158         case 0x80:
 159           DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));
 160           break;
 161         case 0x81:
 162           DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));
 163           break;
 164         case 0x82:
 165           DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));
 166           break;
 167       }
 168       break;
 169
 170     case 0x2:
 171       switch (Cq->Sc) {
 172         case 0x80:
 173           DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));
 174           break;
 175         case 0x81:
 176           DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));
 177           break;
 178         case 0x82:
 179           DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));
 180           break;
 181         case 0x83:
 182           DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));
 183           break;
 184         case 0x84:
 185           DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));
 186           break;
 187         case 0x85:
 188           DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));
 189           break;
 190         case 0x86:
 191           DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));
 192           break;
 193       }
 194       break;
 195
 196     default:
 197       break;
 198   }
 199 }
 200
 201 /**
 202   Create PRP lists for data transfer which is larger than 2 memory pages.
 203   Note here we calcuate the number of required PRP lists and allocate them at one time.
 204
 205   @param[in]     PciIo               A pointer to the EFI_PCI_IO_PROTOCOL instance.
 206   @param[in]     PhysicalAddr        The physical base address of data buffer.
 207   @param[in]     Pages               The number of pages to be transfered.
 208   @param[out]    PrpListHost         The host base address of PRP lists.
 209   @param[in,out] PrpListNo           The number of PRP List.
 210   @param[out]    Mapping             The mapping value returned from PciIo.Map().
 211
 212   @retval The pointer to the first PRP List of the PRP lists.
 213
 214 **/
 215 VOID*
 216 NvmeCreatePrpList (
 217   IN     EFI_PCI_IO_PROTOCOL          *PciIo,
 218   IN     EFI_PHYSICAL_ADDRESS         PhysicalAddr,
 219   IN     UINTN                        Pages,
 220      OUT VOID                         **PrpListHost,
 221   IN OUT UINTN                        *PrpListNo,
 222      OUT VOID                         **Mapping
 223   )
 224 {
 225   UINTN                       PrpEntryNo;
 226   UINT64                      PrpListBase;
 227   UINTN                       PrpListIndex;
 228   UINTN                       PrpEntryIndex;
 229   UINT64                      Remainder;
 230   EFI_PHYSICAL_ADDRESS        PrpListPhyAddr;
 231   UINTN                       Bytes;
 232   EFI_STATUS                  Status;
 233
 234   //
 235   // The number of Prp Entry in a memory page.
 236   //
 237   PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);
 238
 239   //
 240   // Calculate total PrpList number.
 241   //
 242   *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);
 243   if (*PrpListNo == 0) {
 244     *PrpListNo = 1;
 245   } else if ((Remainder != 0) && (Remainder != 1)) {
 246     *PrpListNo += 1;
 247   } else if (Remainder == 1) {
 248     Remainder = PrpEntryNo;
 249   } else if (Remainder == 0) {
 250     Remainder = PrpEntryNo - 1;
 251   }
 252
 253   Status = PciIo->AllocateBuffer (
 254                     PciIo,
 255                     AllocateAnyPages,
 256                     EfiBootServicesData,
 257                     *PrpListNo,
 258                     PrpListHost,
 259                     0
 260                     );
 261
 262   if (EFI_ERROR (Status)) {
 263     return NULL;
 264   }
 265
 266   Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
 267   Status = PciIo->Map (
 268                     PciIo,
 269                     EfiPciIoOperationBusMasterCommonBuffer,
 270                     *PrpListHost,
 271                     &Bytes,
 272                     &PrpListPhyAddr,
 273                     Mapping
 274                     );
 275
 276   if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {
 277     DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
 278     goto EXIT;
 279   }
 280   //
 281   // Fill all PRP lists except of last one.
 282   //
 283   ZeroMem (*PrpListHost, Bytes);
 284   for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {
 285     PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
 286
 287     for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
 288       if (PrpEntryIndex != PrpEntryNo - 1) {
 289         //
 290         // Fill all PRP entries except of last one.
 291         //
 292         *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
 293         PhysicalAddr += EFI_PAGE_SIZE;
 294       } else {
 295         //
 296         // Fill last PRP entries with next PRP List pointer.
 297         //
 298         *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
 299       }
 300     }
 301   }
 302   //
 303   // Fill last PRP list.
 304   //
 305   PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
 306   for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {
 307     *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
 308     PhysicalAddr += EFI_PAGE_SIZE;
 309   }
 310
 311   return (VOID*)(UINTN)PrpListPhyAddr;
 312
 313 EXIT:
 314   PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);
 315   return NULL;
 316 }
 317
 318
 319 /**
 320   Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
 321   both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking
 322   I/O functionality is optional.
 323
 324
 325   @param[in]     This                A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 326   @param[in]     NamespaceId         A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command
 327                                      Packet will be sent.  A value of 0 denotes the NVM Express controller, a value of all 0xFF's
 328                                      (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to
 329                                      all valid namespaces.
 330   @param[in,out] Packet              A pointer to the NVM Express Command Packet.
 331   @param[in]     Event               If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.
 332                                      If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O
 333                                      is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM
 334                                      Express Command Packet completes.
 335
 336   @retval EFI_SUCCESS                The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred
 337                                      to, or from DataBuffer.
 338   @retval EFI_BAD_BUFFER_SIZE        The NVM Express Command Packet was not executed. The number of bytes that could be transferred
 339                                      is returned in TransferLength.
 340   @retval EFI_NOT_READY              The NVM Express Command Packet could not be sent because the controller is not ready. The caller
 341                                      may retry again later.
 342   @retval EFI_DEVICE_ERROR           A device error occurred while attempting to send the NVM Express Command Packet.
 343   @retval EFI_INVALID_PARAMETER      NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM
 344                                      Express Command Packet was not sent, so no additional status information is available.
 345   @retval EFI_UNSUPPORTED            The command described by the NVM Express Command Packet is not supported by the NVM Express
 346                                      controller. The NVM Express Command Packet was not sent so no additional status information
 347                                      is available.
 348   @retval EFI_TIMEOUT                A timeout occurred while waiting for the NVM Express Command Packet to execute.
 349
 350 **/
 351 EFI_STATUS
 352 EFIAPI
 353 NvmExpressPassThru (
 354   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
 355   IN     UINT32                                      NamespaceId,
 356   IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET    *Packet,
 357   IN     EFI_EVENT                                   Event OPTIONAL
 358   )
 359 {
 360   NVME_CONTROLLER_PRIVATE_DATA   *Private;
 361   EFI_STATUS                     Status;
 362   EFI_PCI_IO_PROTOCOL            *PciIo;
 363   NVME_SQ                        *Sq;
 364   NVME_CQ                        *Cq;
 365   UINT16                         QueueId;
 366   UINT32                         Bytes;
 367   UINT16                         Offset;
 368   EFI_EVENT                      TimerEvent;
 369   EFI_PCI_IO_PROTOCOL_OPERATION  Flag;
 370   EFI_PHYSICAL_ADDRESS           PhyAddr;
 371   VOID                           *MapData;
 372   VOID                           *MapMeta;
 373   VOID                           *MapPrpList;
 374   UINTN                          MapLength;
 375   UINT64                         *Prp;
 376   VOID                           *PrpListHost;
 377   UINTN                          PrpListNo;
 378   UINT32                         Attributes;
 379   UINT32                         IoAlign;
 380   UINT32                         Data;
 381   NVME_PASS_THRU_ASYNC_REQ       *AsyncRequest;
 382   EFI_TPL                        OldTpl;
 383
 384   //
 385   // check the data fields in Packet parameter.
 386   //
 387   if ((This == NULL) || (Packet == NULL)) {
 388     return EFI_INVALID_PARAMETER;
 389   }
 390
 391   if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {
 392     return EFI_INVALID_PARAMETER;
 393   }
 394
 395   if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {
 396     return EFI_INVALID_PARAMETER;
 397   }
 398
 399   //
 400   // 'Attributes' with neither EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL nor
 401   // EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal
 402   // configuration.
 403   //
 404   Attributes  = This->Mode->Attributes;
 405   if ((Attributes & (EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
 406     EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0) {
 407     return EFI_INVALID_PARAMETER;
 408   }
 409
 410   //
 411   // Buffer alignment check for TransferBuffer & MetadataBuffer.
 412   //
 413   IoAlign     = This->Mode->IoAlign;
 414   if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {
 415     return EFI_INVALID_PARAMETER;
 416   }
 417
 418   if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {
 419     return EFI_INVALID_PARAMETER;
 420   }
 421
 422   Private     = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 423   PciIo       = Private->PciIo;
 424   MapData     = NULL;
 425   MapMeta     = NULL;
 426   MapPrpList  = NULL;
 427   PrpListHost = NULL;
 428   PrpListNo   = 0;
 429   Prp         = NULL;
 430   TimerEvent  = NULL;
 431   Status      = EFI_SUCCESS;
 432
 433   if (Packet->QueueType == NVME_ADMIN_QUEUE) {
 434     QueueId = 0;
 435   } else {
 436     if (Event == NULL) {
 437       QueueId = 1;
 438     } else {
 439       QueueId = 2;
 440
 441       //
 442       // Submission queue full check.
 443       //
 444       if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==
 445           Private->AsyncSqHead) {
 446         return EFI_NOT_READY;
 447       }
 448     }
 449   }
 450   Sq  = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;
 451   Cq  = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
 452
 453   if (Packet->NvmeCmd->Nsid != NamespaceId) {
 454     return EFI_INVALID_PARAMETER;
 455   }
 456
 457   ZeroMem (Sq, sizeof (NVME_SQ));
 458   Sq->Opc  = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;
 459   Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;
 460   Sq->Cid  = Private->Cid[QueueId]++;
 461   Sq->Nsid = Packet->NvmeCmd->Nsid;
 462
 463   //
 464   // Currently we only support PRP for data transfer, SGL is NOT supported.
 465   //
 466   ASSERT (Sq->Psdt == 0);
 467   if (Sq->Psdt != 0) {
 468     DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
 469     return EFI_UNSUPPORTED;
 470   }
 471
 472   Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;
 473   //
 474   // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.
 475   // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because
 476   // these two cmds are special which requires their data buffer must support simultaneous access by both the
 477   // processor and a PCI Bus Master. It's caller's responsbility to ensure this.
 478   //
 479   if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {
 480     if ((Sq->Opc & BIT0) != 0) {
 481       Flag = EfiPciIoOperationBusMasterRead;
 482     } else {
 483       Flag = EfiPciIoOperationBusMasterWrite;
 484     }
 485
 486     MapLength = Packet->TransferLength;
 487     Status = PciIo->Map (
 488                       PciIo,
 489                       Flag,
 490                       Packet->TransferBuffer,
 491                       &MapLength,
 492                       &PhyAddr,
 493                       &MapData
 494                       );
 495     if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {
 496       return EFI_OUT_OF_RESOURCES;
 497     }
 498
 499     Sq->Prp[0] = PhyAddr;
 500     Sq->Prp[1] = 0;
 501
 502     MapLength = Packet->MetadataLength;
 503     if(Packet->MetadataBuffer != NULL) {
 504       MapLength = Packet->MetadataLength;
 505       Status = PciIo->Map (
 506                         PciIo,
 507                         Flag,
 508                         Packet->MetadataBuffer,
 509                         &MapLength,
 510                         &PhyAddr,
 511                         &MapMeta
 512                         );
 513       if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {
 514         PciIo->Unmap (
 515                  PciIo,
 516                  MapData
 517                  );
 518
 519         return EFI_OUT_OF_RESOURCES;
 520       }
 521       Sq->Mptr = PhyAddr;
 522     }
 523   }
 524   //
 525   // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),
 526   // then build a PRP list in the second PRP submission queue entry.
 527   //
 528   Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);
 529   Bytes  = Packet->TransferLength;
 530
 531   if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {
 532     //
 533     // Create PrpList for remaining data buffer.
 534     //
 535     PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
 536     Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
 537     if (Prp == NULL) {
 538       goto EXIT;
 539     }
 540
 541     Sq->Prp[1] = (UINT64)(UINTN)Prp;
 542   } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {
 543     Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
 544   }
 545
 546   if(Packet->NvmeCmd->Flags & CDW2_VALID) {
 547     Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;
 548   }
 549   if(Packet->NvmeCmd->Flags & CDW3_VALID) {
 550     Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);
 551   }
 552   if(Packet->NvmeCmd->Flags & CDW10_VALID) {
 553     Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
 554   }
 555   if(Packet->NvmeCmd->Flags & CDW11_VALID) {
 556     Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
 557   }
 558   if(Packet->NvmeCmd->Flags & CDW12_VALID) {
 559     Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
 560   }
 561   if(Packet->NvmeCmd->Flags & CDW13_VALID) {
 562     Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
 563   }
 564   if(Packet->NvmeCmd->Flags & CDW14_VALID) {
 565     Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
 566   }
 567   if(Packet->NvmeCmd->Flags & CDW15_VALID) {
 568     Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
 569   }
 570
 571   //
 572   // Ring the submission queue doorbell.
 573   //
 574   if (Event != NULL) {
 575     Private->SqTdbl[QueueId].Sqt =
 576       (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);
 577   } else {
 578     Private->SqTdbl[QueueId].Sqt ^= 1;
 579   }
 580   Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);
 581   PciIo->Mem.Write (
 582                PciIo,
 583                EfiPciIoWidthUint32,
 584                NVME_BAR,
 585                NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),
 586                1,
 587                &Data
 588                );
 589
 590   //
 591   // For non-blocking requests, return directly if the command is placed
 592   // in the submission queue.
 593   //
 594   if (Event != NULL) {
 595     AsyncRequest = AllocateZeroPool (sizeof (NVME_PASS_THRU_ASYNC_REQ));
 596     if (AsyncRequest == NULL) {
 597       Status = EFI_DEVICE_ERROR;
 598       goto EXIT;
 599     }
 600
 601     AsyncRequest->Signature     = NVME_PASS_THRU_ASYNC_REQ_SIG;
 602     AsyncRequest->Packet        = Packet;
 603     AsyncRequest->CommandId     = Sq->Cid;
 604     AsyncRequest->CallerEvent   = Event;
 605
 606     OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
 607     InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);
 608     gBS->RestoreTPL (OldTpl);
 609
 610     return EFI_SUCCESS;
 611   }
 612
 613   Status = gBS->CreateEvent (
 614                   EVT_TIMER,
 615                   TPL_CALLBACK,
 616                   NULL,
 617                   NULL,
 618                   &TimerEvent
 619                   );
 620   if (EFI_ERROR (Status)) {
 621     goto EXIT;
 622   }
 623
 624   Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);
 625
 626   if (EFI_ERROR(Status)) {
 627     goto EXIT;
 628   }
 629
 630   //
 631   // Wait for completion queue to get filled in.
 632   //
 633   Status = EFI_TIMEOUT;
 634   while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {
 635     if (Cq->Pt != Private->Pt[QueueId]) {
 636       Status = EFI_SUCCESS;
 637       break;
 638     }
 639   }
 640
 641   //
 642   // Check the NVMe cmd execution result
 643   //
 644   if (Status != EFI_TIMEOUT) {
 645     if ((Cq->Sct == 0) && (Cq->Sc == 0)) {
 646       Status = EFI_SUCCESS;
 647     } else {
 648       Status = EFI_DEVICE_ERROR;
 649       //
 650       // Copy the Respose Queue entry for this command to the callers response buffer
 651       //
 652       CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));
 653
 654       //
 655       // Dump every completion entry status for debugging.
 656       //
 657       DEBUG_CODE_BEGIN();
 658         NvmeDumpStatus(Cq);
 659       DEBUG_CODE_END();
 660     }
 661   }
 662
 663   if ((Private->CqHdbl[QueueId].Cqh ^= 1) == 0) {
 664     Private->Pt[QueueId] ^= 1;
 665   }
 666
 667   Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
 668   PciIo->Mem.Write (
 669                PciIo,
 670                EfiPciIoWidthUint32,
 671                NVME_BAR,
 672                NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),
 673                1,
 674                &Data
 675                );
 676
 677 EXIT:
 678   if (MapData != NULL) {
 679     PciIo->Unmap (
 680              PciIo,
 681              MapData
 682              );
 683   }
 684
 685   if (MapMeta != NULL) {
 686     PciIo->Unmap (
 687              PciIo,
 688              MapMeta
 689              );
 690   }
 691
 692   if (MapPrpList != NULL) {
 693     PciIo->Unmap (
 694              PciIo,
 695              MapPrpList
 696              );
 697   }
 698
 699   if (Prp != NULL) {
 700     PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);
 701   }
 702
 703   if (TimerEvent != NULL) {
 704     gBS->CloseEvent (TimerEvent);
 705   }
 706   return Status;
 707 }
 708
 709 /**
 710   Used to retrieve the next namespace ID for this NVM Express controller.
 711
 712   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid
 713   namespace ID on this NVM Express controller.
 714
 715   If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace
 716   ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId
 717   and a status of EFI_SUCCESS is returned.
 718
 719   If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,
 720   then EFI_INVALID_PARAMETER is returned.
 721
 722   If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid
 723   namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,
 724   and EFI_SUCCESS is returned.
 725
 726   If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM
 727   Express controller, then EFI_NOT_FOUND is returned.
 728
 729   @param[in]     This           A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 730   @param[in,out] NamespaceId    On input, a pointer to a legal NamespaceId for an NVM Express
 731                                 namespace present on the NVM Express controller. On output, a
 732                                 pointer to the next NamespaceId of an NVM Express namespace on
 733                                 an NVM Express controller. An input value of 0xFFFFFFFF retrieves
 734                                 the first NamespaceId for an NVM Express namespace present on an
 735                                 NVM Express controller.
 736
 737   @retval EFI_SUCCESS           The Namespace ID of the next Namespace was returned.
 738   @retval EFI_NOT_FOUND         There are no more namespaces defined on this controller.
 739   @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.
 740
 741 **/
 742 EFI_STATUS
 743 EFIAPI
 744 NvmExpressGetNextNamespace (
 745   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
 746   IN OUT UINT32                                      *NamespaceId
 747   )
 748 {
 749   NVME_CONTROLLER_PRIVATE_DATA     *Private;
 750   NVME_ADMIN_NAMESPACE_DATA        *NamespaceData;
 751   UINT32                           NextNamespaceId;
 752   EFI_STATUS                       Status;
 753
 754   if ((This == NULL) || (NamespaceId == NULL)) {
 755     return EFI_INVALID_PARAMETER;
 756   }
 757
 758   NamespaceData = NULL;
 759   Status        = EFI_NOT_FOUND;
 760
 761   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 762   //
 763   // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID
 764   //
 765   if (*NamespaceId == 0xFFFFFFFF) {
 766     //
 767     // Start with the first namespace ID
 768     //
 769     NextNamespaceId = 1;
 770     //
 771     // Allocate buffer for Identify Namespace data.
 772     //
 773     NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
 774
 775     if (NamespaceData == NULL) {
 776       return EFI_NOT_FOUND;
 777     }
 778
 779     Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
 780     if (EFI_ERROR(Status)) {
 781       goto Done;
 782     }
 783
 784     *NamespaceId = NextNamespaceId;
 785   } else {
 786     if (*NamespaceId > Private->ControllerData->Nn) {
 787       return EFI_INVALID_PARAMETER;
 788     }
 789
 790     NextNamespaceId = *NamespaceId + 1;
 791     if (NextNamespaceId > Private->ControllerData->Nn) {
 792       return EFI_NOT_FOUND;
 793     }
 794
 795     //
 796     // Allocate buffer for Identify Namespace data.
 797     //
 798     NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
 799     if (NamespaceData == NULL) {
 800       return EFI_NOT_FOUND;
 801     }
 802
 803     Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
 804     if (EFI_ERROR(Status)) {
 805       goto Done;
 806     }
 807
 808     *NamespaceId = NextNamespaceId;
 809   }
 810
 811 Done:
 812   if (NamespaceData != NULL) {
 813     FreePool(NamespaceData);
 814   }
 815
 816   return Status;
 817 }
 818
 819 /**
 820   Used to translate a device path node to a namespace ID.
 821
 822   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the
 823   namespace described by DevicePath.
 824
 825   If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express
 826   Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.
 827
 828   If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned
 829
 830   @param[in]  This                A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 831   @param[in]  DevicePath          A pointer to the device path node that describes an NVM Express namespace on
 832                                   the NVM Express controller.
 833   @param[out] NamespaceId         The NVM Express namespace ID contained in the device path node.
 834
 835   @retval EFI_SUCCESS             DevicePath was successfully translated to NamespaceId.
 836   @retval EFI_INVALID_PARAMETER   If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.
 837   @retval EFI_UNSUPPORTED         If DevicePath is not a device path node type that the NVM Express Pass Thru driver
 838                                   supports, then EFI_UNSUPPORTED is returned.
 839   @retval EFI_NOT_FOUND           If DevicePath is a device path node type that the NVM Express Pass Thru driver
 840                                   supports, but there is not a valid translation from DevicePath to a namespace ID,
 841                                   then EFI_NOT_FOUND is returned.
 842 **/
 843 EFI_STATUS
 844 EFIAPI
 845 NvmExpressGetNamespace (
 846   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
 847   IN     EFI_DEVICE_PATH_PROTOCOL                    *DevicePath,
 848      OUT UINT32                                      *NamespaceId
 849   )
 850 {
 851   NVME_NAMESPACE_DEVICE_PATH       *Node;
 852   NVME_CONTROLLER_PRIVATE_DATA     *Private;
 853
 854   if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {
 855     return EFI_INVALID_PARAMETER;
 856   }
 857
 858   if (DevicePath->Type != MESSAGING_DEVICE_PATH) {
 859     return EFI_UNSUPPORTED;
 860   }
 861
 862   Node    = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;
 863   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 864
 865   if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {
 866     if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {
 867       return EFI_NOT_FOUND;
 868     }
 869
 870     //
 871     // Check NamespaceId in the device path node is valid or not.
 872     //
 873     if ((Node->NamespaceId == 0) ||
 874       (Node->NamespaceId > Private->ControllerData->Nn)) {
 875       return EFI_NOT_FOUND;
 876     }
 877
 878     *NamespaceId = Node->NamespaceId;
 879
 880     return EFI_SUCCESS;
 881   } else {
 882     return EFI_UNSUPPORTED;
 883   }
 884 }
 885
 886 /**
 887   Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.
 888
 889   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device
 890   path node for the NVM Express namespace specified by NamespaceId.
 891
 892   If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.
 893
 894   If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
 895
 896   If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
 897
 898   Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are
 899   initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.
 900
 901   @param[in]     This                A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 902   @param[in]     NamespaceId         The NVM Express namespace ID  for which a device path node is to be
 903                                      allocated and built. Caller must set the NamespaceId to zero if the
 904                                      device path node will contain a valid UUID.
 905   @param[in,out] DevicePath          A pointer to a single device path node that describes the NVM Express
 906                                      namespace specified by NamespaceId. This function is responsible for
 907                                      allocating the buffer DevicePath with the boot service AllocatePool().
 908                                      It is the caller's responsibility to free DevicePath when the caller
 909                                      is finished with DevicePath.
 910   @retval EFI_SUCCESS                The device path node that describes the NVM Express namespace specified
 911                                      by NamespaceId was allocated and returned in DevicePath.
 912   @retval EFI_NOT_FOUND              The NamespaceId is not valid.
 913   @retval EFI_INVALID_PARAMETER      DevicePath is NULL.
 914   @retval EFI_OUT_OF_RESOURCES       There are not enough resources to allocate the DevicePath node.
 915
 916 **/
 917 EFI_STATUS
 918 EFIAPI
 919 NvmExpressBuildDevicePath (
 920   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
 921   IN     UINT32                                      NamespaceId,
 922   IN OUT EFI_DEVICE_PATH_PROTOCOL                    **DevicePath
 923   )
 924 {
 925   NVME_NAMESPACE_DEVICE_PATH     *Node;
 926   NVME_CONTROLLER_PRIVATE_DATA   *Private;
 927   EFI_STATUS                     Status;
 928   NVME_ADMIN_NAMESPACE_DATA      *NamespaceData;
 929
 930   //
 931   // Validate parameters
 932   //
 933   if ((This == NULL) || (DevicePath == NULL)) {
 934     return EFI_INVALID_PARAMETER;
 935   }
 936
 937   Status  = EFI_SUCCESS;
 938   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 939
 940   //
 941   // Check NamespaceId is valid or not.
 942   //
 943   if ((NamespaceId == 0) ||
 944     (NamespaceId > Private->ControllerData->Nn)) {
 945     return EFI_NOT_FOUND;
 946   }
 947
 948   Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));
 949   if (Node == NULL) {
 950     return EFI_OUT_OF_RESOURCES;
 951   }
 952
 953   Node->Header.Type    = MESSAGING_DEVICE_PATH;
 954   Node->Header.SubType = MSG_NVME_NAMESPACE_DP;
 955   SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));
 956   Node->NamespaceId    = NamespaceId;
 957
 958   //
 959   // Allocate a buffer for Identify Namespace data.
 960   //
 961   NamespaceData = NULL;
 962   NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));
 963   if(NamespaceData == NULL) {
 964     Status = EFI_OUT_OF_RESOURCES;
 965     goto Exit;
 966   }
 967
 968   //
 969   // Get UUID from specified Identify Namespace data.
 970   //
 971   Status = NvmeIdentifyNamespace (
 972              Private,
 973              NamespaceId,
 974              (VOID *)NamespaceData
 975              );
 976
 977   if (EFI_ERROR(Status)) {
 978     goto Exit;
 979   }
 980
 981   Node->NamespaceUuid = NamespaceData->Eui64;
 982
 983   *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;
 984
 985 Exit:
 986   if(NamespaceData != NULL) {
 987     FreePool (NamespaceData);
 988   }
 989
 990   if (EFI_ERROR (Status)) {
 991     FreePool (Node);
 992   }
 993
 994   return Status;
 995 }
 996