MdeModulePkg/PciBus: Add IOMMU support.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciBus.h
1 /** @file
2 Header files and data structures needed by PCI Bus module.
3
4 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15
16 #ifndef _EFI_PCI_BUS_H_
17 #define _EFI_PCI_BUS_H_
18
19 #include <PiDxe.h>
20
21 #include <Protocol/LoadedImage.h>
22 #include <Protocol/PciHostBridgeResourceAllocation.h>
23 #include <Protocol/PciIo.h>
24 #include <Protocol/LoadFile2.h>
25 #include <Protocol/PciRootBridgeIo.h>
26 #include <Protocol/PciHotPlugRequest.h>
27 #include <Protocol/DevicePath.h>
28 #include <Protocol/PciPlatform.h>
29 #include <Protocol/PciHotPlugInit.h>
30 #include <Protocol/Decompress.h>
31 #include <Protocol/BusSpecificDriverOverride.h>
32 #include <Protocol/IncompatiblePciDeviceSupport.h>
33 #include <Protocol/PciOverride.h>
34 #include <Protocol/PciEnumerationComplete.h>
35 #include <Protocol/IoMmu.h>
36
37 #include <Library/DebugLib.h>
38 #include <Library/UefiDriverEntryPoint.h>
39 #include <Library/BaseLib.h>
40 #include <Library/UefiLib.h>
41 #include <Library/BaseMemoryLib.h>
42 #include <Library/ReportStatusCodeLib.h>
43 #include <Library/MemoryAllocationLib.h>
44 #include <Library/UefiBootServicesTableLib.h>
45 #include <Library/DevicePathLib.h>
46 #include <Library/PcdLib.h>
47 #include <Library/PeCoffLib.h>
48
49 #include <IndustryStandard/Pci.h>
50 #include <IndustryStandard/PeImage.h>
51 #include <IndustryStandard/Acpi.h>
52
53 typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
54 typedef struct _PCI_BAR PCI_BAR;
55
56 #define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
57 #define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
58
59 #define EFI_PCI_IOV_POLICY_ARI 0x0001
60 #define EFI_PCI_IOV_POLICY_SRIOV 0x0002
61 #define EFI_PCI_IOV_POLICY_MRIOV 0x0004
62
63 typedef enum {
64 PciBarTypeUnknown = 0,
65 PciBarTypeIo16,
66 PciBarTypeIo32,
67 PciBarTypeMem32,
68 PciBarTypePMem32,
69 PciBarTypeMem64,
70 PciBarTypePMem64,
71 PciBarTypeIo,
72 PciBarTypeMem,
73 PciBarTypeMaxType
74 } PCI_BAR_TYPE;
75
76 #include "ComponentName.h"
77 #include "PciIo.h"
78 #include "PciCommand.h"
79 #include "PciDeviceSupport.h"
80 #include "PciEnumerator.h"
81 #include "PciEnumeratorSupport.h"
82 #include "PciDriverOverride.h"
83 #include "PciRomTable.h"
84 #include "PciOptionRomSupport.h"
85 #include "PciPowerManagement.h"
86 #include "PciHotPlugSupport.h"
87 #include "PciLib.h"
88
89 #define VGABASE1 0x3B0
90 #define VGALIMIT1 0x3BB
91
92 #define VGABASE2 0x3C0
93 #define VGALIMIT2 0x3DF
94
95 #define ISABASE 0x100
96 #define ISALIMIT 0x3FF
97
98 //
99 // PCI BAR parameters
100 //
101 struct _PCI_BAR {
102 UINT64 BaseAddress;
103 UINT64 Length;
104 UINT64 Alignment;
105 PCI_BAR_TYPE BarType;
106 BOOLEAN BarTypeFixed;
107 UINT16 Offset;
108 };
109
110 //
111 // defined in PCI Card Specification, 8.0
112 //
113 #define PCI_CARD_MEMORY_BASE_0 0x1C
114 #define PCI_CARD_MEMORY_LIMIT_0 0x20
115 #define PCI_CARD_MEMORY_BASE_1 0x24
116 #define PCI_CARD_MEMORY_LIMIT_1 0x28
117 #define PCI_CARD_IO_BASE_0_LOWER 0x2C
118 #define PCI_CARD_IO_BASE_0_UPPER 0x2E
119 #define PCI_CARD_IO_LIMIT_0_LOWER 0x30
120 #define PCI_CARD_IO_LIMIT_0_UPPER 0x32
121 #define PCI_CARD_IO_BASE_1_LOWER 0x34
122 #define PCI_CARD_IO_BASE_1_UPPER 0x36
123 #define PCI_CARD_IO_LIMIT_1_LOWER 0x38
124 #define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
125 #define PCI_CARD_BRIDGE_CONTROL 0x3E
126
127 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
128 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
129
130 #define RB_IO_RANGE 1
131 #define RB_MEM32_RANGE 2
132 #define RB_PMEM32_RANGE 3
133 #define RB_MEM64_RANGE 4
134 #define RB_PMEM64_RANGE 5
135
136 #define PPB_BAR_0 0
137 #define PPB_BAR_1 1
138 #define PPB_IO_RANGE 2
139 #define PPB_MEM32_RANGE 3
140 #define PPB_PMEM32_RANGE 4
141 #define PPB_PMEM64_RANGE 5
142 #define PPB_MEM64_RANGE 0xFF
143
144 #define P2C_BAR_0 0
145 #define P2C_MEM_1 1
146 #define P2C_MEM_2 2
147 #define P2C_IO_1 3
148 #define P2C_IO_2 4
149
150 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
151 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
152 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
153 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
154 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
155 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
156 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
157
158 #define PCI_MAX_HOST_BRIDGE_NUM 0x0010
159
160 //
161 // Define option for attribute
162 //
163 #define EFI_SET_SUPPORTS 0
164 #define EFI_SET_ATTRIBUTES 1
165
166 #define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
167
168 struct _PCI_IO_DEVICE {
169 UINT32 Signature;
170 EFI_HANDLE Handle;
171 EFI_PCI_IO_PROTOCOL PciIo;
172 LIST_ENTRY Link;
173
174 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
175 EFI_DEVICE_PATH_PROTOCOL *DevicePath;
176 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
177 EFI_LOAD_FILE2_PROTOCOL LoadFile2;
178
179 //
180 // PCI configuration space header type
181 //
182 PCI_TYPE00 Pci;
183
184 //
185 // Bus number, Device number, Function number
186 //
187 UINT8 BusNumber;
188 UINT8 DeviceNumber;
189 UINT8 FunctionNumber;
190
191 //
192 // BAR for this PCI Device
193 //
194 PCI_BAR PciBar[PCI_MAX_BAR];
195
196 //
197 // The bridge device this pci device is subject to
198 //
199 PCI_IO_DEVICE *Parent;
200
201 //
202 // A linked list for children Pci Device if it is bridge device
203 //
204 LIST_ENTRY ChildList;
205
206 //
207 // TRUE if the PCI bus driver creates the handle for this PCI device
208 //
209 BOOLEAN Registered;
210
211 //
212 // TRUE if the PCI bus driver successfully allocates the resource required by
213 // this PCI device
214 //
215 BOOLEAN Allocated;
216
217 //
218 // The attribute this PCI device currently set
219 //
220 UINT64 Attributes;
221
222 //
223 // The attributes this PCI device actually supports
224 //
225 UINT64 Supports;
226
227 //
228 // The resource decode the bridge supports
229 //
230 UINT32 Decodes;
231
232 //
233 // TRUE if the ROM image is from the PCI Option ROM BAR
234 //
235 BOOLEAN EmbeddedRom;
236
237 //
238 // The OptionRom Size
239 //
240 UINT64 RomSize;
241
242 //
243 // The OptionRom Size
244 //
245 UINT64 RomBase;
246
247 //
248 // TRUE if all OpROM (in device or in platform specific position) have been processed
249 //
250 BOOLEAN AllOpRomProcessed;
251
252 //
253 // TRUE if there is any EFI driver in the OptionRom
254 //
255 BOOLEAN BusOverride;
256
257 //
258 // A list tracking reserved resource on a bridge device
259 //
260 LIST_ENTRY ReservedResourceList;
261
262 //
263 // A list tracking image handle of platform specific overriding driver
264 //
265 LIST_ENTRY OptionRomDriverList;
266
267 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
268 EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
269
270 //
271 // Bus number ranges for a PCI Root Bridge device
272 //
273 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
274
275 BOOLEAN IsPciExp;
276 //
277 // For SR-IOV
278 //
279 UINT8 PciExpressCapabilityOffset;
280 UINT32 AriCapabilityOffset;
281 UINT32 SrIovCapabilityOffset;
282 UINT32 MrIovCapabilityOffset;
283 PCI_BAR VfPciBar[PCI_MAX_BAR];
284 UINT32 SystemPageSize;
285 UINT16 InitialVFs;
286 UINT16 ReservedBusNum;
287 //
288 // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
289 // but some chipsets support non-standard I/O window alignments less than 4K.
290 // This field is used to support this case.
291 //
292 UINT16 BridgeIoAlignment;
293 };
294
295 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
296 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
297
298 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
299 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
300
301 #define PCI_IO_DEVICE_FROM_LINK(a) \
302 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
303
304 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
305 CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
306
307
308
309 //
310 // Global Variables
311 //
312 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
313 extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
314 extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
315 extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
316 extern BOOLEAN gFullEnumeration;
317 extern UINTN gPciHostBridgeNumber;
318 extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
319 extern UINT64 gAllOne;
320 extern UINT64 gAllZero;
321 extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
322 extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
323 extern BOOLEAN mReserveIsaAliases;
324 extern BOOLEAN mReserveVgaAliases;
325
326 /**
327 Macro that checks whether device is a GFX device.
328
329 @param _p Specified device.
330
331 @retval TRUE Device is a GFX device.
332 @retval FALSE Device is not a GFX device.
333
334 **/
335 #define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
336
337 /**
338 Test to see if this driver supports ControllerHandle. Any ControllerHandle
339 than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
340
341 @param This Protocol instance pointer.
342 @param Controller Handle of device to test.
343 @param RemainingDevicePath Optional parameter use to pick a specific child
344 device to start.
345
346 @retval EFI_SUCCESS This driver supports this device.
347 @retval EFI_ALREADY_STARTED This driver is already running on this device.
348 @retval other This driver does not support this device.
349
350 **/
351 EFI_STATUS
352 EFIAPI
353 PciBusDriverBindingSupported (
354 IN EFI_DRIVER_BINDING_PROTOCOL *This,
355 IN EFI_HANDLE Controller,
356 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
357 );
358
359 /**
360 Start this driver on ControllerHandle and enumerate Pci bus and start
361 all device under PCI bus.
362
363 @param This Protocol instance pointer.
364 @param Controller Handle of device to bind driver to.
365 @param RemainingDevicePath Optional parameter use to pick a specific child
366 device to start.
367
368 @retval EFI_SUCCESS This driver is added to ControllerHandle.
369 @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.
370 @retval other This driver does not support this device.
371
372 **/
373 EFI_STATUS
374 EFIAPI
375 PciBusDriverBindingStart (
376 IN EFI_DRIVER_BINDING_PROTOCOL *This,
377 IN EFI_HANDLE Controller,
378 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
379 );
380
381 /**
382 Stop this driver on ControllerHandle. Support stopping any child handles
383 created by this driver.
384
385 @param This Protocol instance pointer.
386 @param Controller Handle of device to stop driver on.
387 @param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of
388 children is zero stop the entire bus driver.
389 @param ChildHandleBuffer List of Child Handles to Stop.
390
391 @retval EFI_SUCCESS This driver is removed ControllerHandle.
392 @retval other This driver was not removed from this device.
393
394 **/
395 EFI_STATUS
396 EFIAPI
397 PciBusDriverBindingStop (
398 IN EFI_DRIVER_BINDING_PROTOCOL *This,
399 IN EFI_HANDLE Controller,
400 IN UINTN NumberOfChildren,
401 IN EFI_HANDLE *ChildHandleBuffer
402 );
403
404 #endif