MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2   Header files and data structures needed by PCI Bus module.
   3
   4 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9
  10 #ifndef _EFI_PCI_BUS_H_
  11 #define _EFI_PCI_BUS_H_
  12
  13 #include <PiDxe.h>
  14
  15 #include <Protocol/LoadedImage.h>
  16 #include <Protocol/PciHostBridgeResourceAllocation.h>
  17 #include <Protocol/PciIo.h>
  18 #include <Protocol/LoadFile2.h>
  19 #include <Protocol/PciRootBridgeIo.h>
  20 #include <Protocol/PciHotPlugRequest.h>
  21 #include <Protocol/DevicePath.h>
  22 #include <Protocol/PciPlatform.h>
  23 #include <Protocol/PciHotPlugInit.h>
  24 #include <Protocol/Decompress.h>
  25 #include <Protocol/BusSpecificDriverOverride.h>
  26 #include <Protocol/IncompatiblePciDeviceSupport.h>
  27 #include <Protocol/PciOverride.h>
  28 #include <Protocol/PciEnumerationComplete.h>
  29 #include <Protocol/IoMmu.h>
  30 #include <Protocol/DeviceSecurity.h>
  31
  32 #include <Library/DebugLib.h>
  33 #include <Library/UefiDriverEntryPoint.h>
  34 #include <Library/BaseLib.h>
  35 #include <Library/UefiLib.h>
  36 #include <Library/BaseMemoryLib.h>
  37 #include <Library/ReportStatusCodeLib.h>
  38 #include <Library/MemoryAllocationLib.h>
  39 #include <Library/UefiBootServicesTableLib.h>
  40 #include <Library/DevicePathLib.h>
  41 #include <Library/PcdLib.h>
  42
  43 #include <IndustryStandard/Pci.h>
  44 #include <IndustryStandard/PeImage.h>
  45 #include <IndustryStandard/Acpi.h>
  46
  47 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
  48 typedef struct _PCI_BAR                    PCI_BAR;
  49
  50 #define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
  51 #define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
  52
  53 #define     EFI_PCI_IOV_POLICY_ARI           0x0001
  54 #define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
  55 #define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
  56
  57 typedef enum {
  58   PciBarTypeUnknown = 0,
  59   PciBarTypeIo16,
  60   PciBarTypeIo32,
  61   PciBarTypeMem32,
  62   PciBarTypePMem32,
  63   PciBarTypeMem64,
  64   PciBarTypePMem64,
  65   PciBarTypeOpRom,
  66   PciBarTypeIo,
  67   PciBarTypeMem,
  68   PciBarTypeMaxType
  69 } PCI_BAR_TYPE;
  70
  71 #include "ComponentName.h"
  72 #include "PciIo.h"
  73 #include "PciCommand.h"
  74 #include "PciDeviceSupport.h"
  75 #include "PciEnumerator.h"
  76 #include "PciEnumeratorSupport.h"
  77 #include "PciDriverOverride.h"
  78 #include "PciRomTable.h"
  79 #include "PciOptionRomSupport.h"
  80 #include "PciPowerManagement.h"
  81 #include "PciHotPlugSupport.h"
  82 #include "PciLib.h"
  83
  84 #define VGABASE1  0x3B0
  85 #define VGALIMIT1 0x3BB
  86
  87 #define VGABASE2  0x3C0
  88 #define VGALIMIT2 0x3DF
  89
  90 #define ISABASE   0x100
  91 #define ISALIMIT  0x3FF
  92
  93 //
  94 // PCI BAR parameters
  95 //
  96 struct _PCI_BAR {
  97   UINT64        BaseAddress;
  98   UINT64        Length;
  99   UINT64        Alignment;
 100   PCI_BAR_TYPE  BarType;
 101   BOOLEAN       BarTypeFixed;
 102   UINT16        Offset;
 103 };
 104
 105 //
 106 // defined in PCI Card Specification, 8.0
 107 //
 108 #define PCI_CARD_MEMORY_BASE_0                0x1C
 109 #define PCI_CARD_MEMORY_LIMIT_0               0x20
 110 #define PCI_CARD_MEMORY_BASE_1                0x24
 111 #define PCI_CARD_MEMORY_LIMIT_1               0x28
 112 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
 113 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
 114 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
 115 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
 116 #define PCI_CARD_IO_BASE_1_LOWER              0x34
 117 #define PCI_CARD_IO_BASE_1_UPPER              0x36
 118 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
 119 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
 120 #define PCI_CARD_BRIDGE_CONTROL               0x3E
 121
 122 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
 123 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
 124
 125 #define RB_IO_RANGE                           1
 126 #define RB_MEM32_RANGE                        2
 127 #define RB_PMEM32_RANGE                       3
 128 #define RB_MEM64_RANGE                        4
 129 #define RB_PMEM64_RANGE                       5
 130
 131 #define PPB_BAR_0                             0
 132 #define PPB_BAR_1                             1
 133 #define PPB_IO_RANGE                          2
 134 #define PPB_MEM32_RANGE                       3
 135 #define PPB_PMEM32_RANGE                      4
 136 #define PPB_PMEM64_RANGE                      5
 137 #define PPB_MEM64_RANGE                       0xFF
 138
 139 #define P2C_BAR_0                             0
 140 #define P2C_MEM_1                             1
 141 #define P2C_MEM_2                             2
 142 #define P2C_IO_1                              3
 143 #define P2C_IO_2                              4
 144
 145 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 146 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 147 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 148 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 149 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 150 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 151 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 152
 153 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 154
 155 //
 156 // Define option for attribute
 157 //
 158 #define EFI_SET_SUPPORTS    0
 159 #define EFI_SET_ATTRIBUTES  1
 160
 161 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 162
 163 struct _PCI_IO_DEVICE {
 164   UINT32                                    Signature;
 165   EFI_HANDLE                                Handle;
 166   EFI_PCI_IO_PROTOCOL                       PciIo;
 167   LIST_ENTRY                                Link;
 168
 169   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 170   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 171   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 172   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 173
 174   //
 175   // PCI configuration space header type
 176   //
 177   PCI_TYPE00                                Pci;
 178
 179   //
 180   // Bus number, Device number, Function number
 181   //
 182   UINT8                                     BusNumber;
 183   UINT8                                     DeviceNumber;
 184   UINT8                                     FunctionNumber;
 185
 186   //
 187   // BAR for this PCI Device
 188   //
 189   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 190
 191   //
 192   // The bridge device this pci device is subject to
 193   //
 194   PCI_IO_DEVICE                             *Parent;
 195
 196   //
 197   // A linked list for children Pci Device if it is bridge device
 198   //
 199   LIST_ENTRY                                ChildList;
 200
 201   //
 202   // TRUE if the PCI bus driver creates the handle for this PCI device
 203   //
 204   BOOLEAN                                   Registered;
 205
 206   //
 207   // TRUE if the PCI bus driver successfully allocates the resource required by
 208   // this PCI device
 209   //
 210   BOOLEAN                                   Allocated;
 211
 212   //
 213   // The attribute this PCI device currently set
 214   //
 215   UINT64                                    Attributes;
 216
 217   //
 218   // The attributes this PCI device actually supports
 219   //
 220   UINT64                                    Supports;
 221
 222   //
 223   // The resource decode the bridge supports
 224   //
 225   UINT32                                    Decodes;
 226
 227   //
 228   // TRUE if the ROM image is from the PCI Option ROM BAR
 229   //
 230   BOOLEAN                                   EmbeddedRom;
 231
 232   //
 233   // The OptionRom Size
 234   //
 235   UINT32                                    RomSize;
 236
 237   //
 238   // TRUE if all OpROM (in device or in platform specific position) have been processed
 239   //
 240   BOOLEAN                                   AllOpRomProcessed;
 241
 242   //
 243   // TRUE if there is any EFI driver in the OptionRom
 244   //
 245   BOOLEAN                                   BusOverride;
 246
 247   //
 248   // A list tracking reserved resource on a bridge device
 249   //
 250   LIST_ENTRY                                ReservedResourceList;
 251
 252   //
 253   // A list tracking image handle of platform specific overriding driver
 254   //
 255   LIST_ENTRY                                OptionRomDriverList;
 256
 257   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 258   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 259
 260   //
 261   // Bus number ranges for a PCI Root Bridge device
 262   //
 263   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;
 264
 265   BOOLEAN                                   IsPciExp;
 266   //
 267   // For SR-IOV
 268   //
 269   UINT8                                     PciExpressCapabilityOffset;
 270   UINT32                                    AriCapabilityOffset;
 271   UINT32                                    SrIovCapabilityOffset;
 272   UINT32                                    MrIovCapabilityOffset;
 273   PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
 274   UINT32                                    SystemPageSize;
 275   UINT16                                    InitialVFs;
 276   UINT16                                    ReservedBusNum;
 277   //
 278   // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
 279   // but some chipsets support non-standard I/O window alignments less than 4K.
 280   // This field is used to support this case.
 281   //
 282   UINT16                                    BridgeIoAlignment;
 283   UINT32                                    ResizableBarOffset;
 284   UINT32                                    ResizableBarNumber;
 285 };
 286
 287 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 288   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 289
 290 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 291   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 292
 293 #define PCI_IO_DEVICE_FROM_LINK(a) \
 294   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 295
 296 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 297   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 298
 299
 300
 301 //
 302 // Global Variables
 303 //
 304 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
 305 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 306 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 307 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 308 extern BOOLEAN                                      gFullEnumeration;
 309 extern UINTN                                        gPciHostBridgeNumber;
 310 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 311 extern UINT64                                       gAllOne;
 312 extern UINT64                                       gAllZero;
 313 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 314 extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;
 315 extern BOOLEAN                                      mReserveIsaAliases;
 316 extern BOOLEAN                                      mReserveVgaAliases;
 317
 318 /**
 319   Macro that checks whether device is a GFX device.
 320
 321   @param  _p      Specified device.
 322
 323   @retval TRUE    Device is a GFX device.
 324   @retval FALSE   Device is not a GFX device.
 325
 326 **/
 327 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 328
 329 /**
 330   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 331   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 332
 333   @param  This                Protocol instance pointer.
 334   @param  Controller          Handle of device to test.
 335   @param  RemainingDevicePath Optional parameter use to pick a specific child
 336                               device to start.
 337
 338   @retval EFI_SUCCESS         This driver supports this device.
 339   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 340   @retval other               This driver does not support this device.
 341
 342 **/
 343 EFI_STATUS
 344 EFIAPI
 345 PciBusDriverBindingSupported (
 346   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 347   IN EFI_HANDLE                     Controller,
 348   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 349   );
 350
 351 /**
 352   Start this driver on ControllerHandle and enumerate Pci bus and start
 353   all device under PCI bus.
 354
 355   @param  This                 Protocol instance pointer.
 356   @param  Controller           Handle of device to bind driver to.
 357   @param  RemainingDevicePath  Optional parameter use to pick a specific child
 358                                device to start.
 359
 360   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 361   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 362   @retval other                This driver does not support this device.
 363
 364 **/
 365 EFI_STATUS
 366 EFIAPI
 367 PciBusDriverBindingStart (
 368   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 369   IN EFI_HANDLE                     Controller,
 370   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 371   );
 372
 373 /**
 374   Stop this driver on ControllerHandle. Support stopping any child handles
 375   created by this driver.
 376
 377   @param  This              Protocol instance pointer.
 378   @param  Controller        Handle of device to stop driver on.
 379   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 380                             children is zero stop the entire bus driver.
 381   @param  ChildHandleBuffer List of Child Handles to Stop.
 382
 383   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 384   @retval other             This driver was not removed from this device.
 385
 386 **/
 387 EFI_STATUS
 388 EFIAPI
 389 PciBusDriverBindingStop (
 390   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 391   IN  EFI_HANDLE                    Controller,
 392   IN  UINTN                         NumberOfChildren,
 393   IN  EFI_HANDLE                    *ChildHandleBuffer
 394   );
 395
 396 #endif