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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
4
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
6
7 Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
8 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17 **/
18
19 #include "SdMmcPciHcDxe.h"
20
21 /**
22 Dump the content of SD/MMC host controller's Capability Register.
23
24 @param[in] Slot The slot number of the SD card to send the command to.
25 @param[in] Capability The buffer to store the capability data.
26
27 **/
28 VOID
29 DumpCapabilityReg (
30 IN UINT8 Slot,
31 IN SD_MMC_HC_SLOT_CAP *Capability
32 )
33 {
34 //
35 // Dump Capability Data
36 //
37 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
38 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
39 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
40 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
41 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
49 DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));
50 DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));
51 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
52 DEBUG ((DEBUG_INFO, " SlotType "));
53 if (Capability->SlotType == 0x00) {
54 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
55 } else if (Capability->SlotType == 0x01) {
56 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
57 } else if (Capability->SlotType == 0x02) {
58 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
59 } else {
60 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
61 }
62 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
66 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
67 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
68 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
69 if (Capability->TimerCount == 0) {
70 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
71 } else {
72 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
73 }
74 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
75 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
76 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
77 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
78 return;
79 }
80
81 /**
82 Read SlotInfo register from SD/MMC host controller pci config space.
83
84 @param[in] PciIo The PCI IO protocol instance.
85 @param[out] FirstBar The buffer to store the first BAR value.
86 @param[out] SlotNum The buffer to store the supported slot number.
87
88 @retval EFI_SUCCESS The operation succeeds.
89 @retval Others The operation fails.
90
91 **/
92 EFI_STATUS
93 EFIAPI
94 SdMmcHcGetSlotInfo (
95 IN EFI_PCI_IO_PROTOCOL *PciIo,
96 OUT UINT8 *FirstBar,
97 OUT UINT8 *SlotNum
98 )
99 {
100 EFI_STATUS Status;
101 SD_MMC_HC_SLOT_INFO SlotInfo;
102
103 Status = PciIo->Pci.Read (
104 PciIo,
105 EfiPciIoWidthUint8,
106 SD_MMC_HC_SLOT_OFFSET,
107 sizeof (SlotInfo),
108 &SlotInfo
109 );
110 if (EFI_ERROR (Status)) {
111 return Status;
112 }
113
114 *FirstBar = SlotInfo.FirstBar;
115 *SlotNum = SlotInfo.SlotNum + 1;
116 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
117 return EFI_SUCCESS;
118 }
119
120 /**
121 Read/Write specified SD/MMC host controller mmio register.
122
123 @param[in] PciIo The PCI IO protocol instance.
124 @param[in] BarIndex The BAR index of the standard PCI Configuration
125 header to use as the base address for the memory
126 operation to perform.
127 @param[in] Offset The offset within the selected BAR to start the
128 memory operation.
129 @param[in] Read A boolean to indicate it's read or write operation.
130 @param[in] Count The width of the mmio register in bytes.
131 Must be 1, 2 , 4 or 8 bytes.
132 @param[in, out] Data For read operations, the destination buffer to store
133 the results. For write operations, the source buffer
134 to write data from. The caller is responsible for
135 having ownership of the data buffer and ensuring its
136 size not less than Count bytes.
137
138 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
139 @retval EFI_SUCCESS The read/write operation succeeds.
140 @retval Others The read/write operation fails.
141
142 **/
143 EFI_STATUS
144 EFIAPI
145 SdMmcHcRwMmio (
146 IN EFI_PCI_IO_PROTOCOL *PciIo,
147 IN UINT8 BarIndex,
148 IN UINT32 Offset,
149 IN BOOLEAN Read,
150 IN UINT8 Count,
151 IN OUT VOID *Data
152 )
153 {
154 EFI_STATUS Status;
155
156 if ((PciIo == NULL) || (Data == NULL)) {
157 return EFI_INVALID_PARAMETER;
158 }
159
160 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
161 return EFI_INVALID_PARAMETER;
162 }
163
164 if (Read) {
165 Status = PciIo->Mem.Read (
166 PciIo,
167 EfiPciIoWidthUint8,
168 BarIndex,
169 (UINT64) Offset,
170 Count,
171 Data
172 );
173 } else {
174 Status = PciIo->Mem.Write (
175 PciIo,
176 EfiPciIoWidthUint8,
177 BarIndex,
178 (UINT64) Offset,
179 Count,
180 Data
181 );
182 }
183
184 return Status;
185 }
186
187 /**
188 Do OR operation with the value of the specified SD/MMC host controller mmio register.
189
190 @param[in] PciIo The PCI IO protocol instance.
191 @param[in] BarIndex The BAR index of the standard PCI Configuration
192 header to use as the base address for the memory
193 operation to perform.
194 @param[in] Offset The offset within the selected BAR to start the
195 memory operation.
196 @param[in] Count The width of the mmio register in bytes.
197 Must be 1, 2 , 4 or 8 bytes.
198 @param[in] OrData The pointer to the data used to do OR operation.
199 The caller is responsible for having ownership of
200 the data buffer and ensuring its size not less than
201 Count bytes.
202
203 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
204 @retval EFI_SUCCESS The OR operation succeeds.
205 @retval Others The OR operation fails.
206
207 **/
208 EFI_STATUS
209 EFIAPI
210 SdMmcHcOrMmio (
211 IN EFI_PCI_IO_PROTOCOL *PciIo,
212 IN UINT8 BarIndex,
213 IN UINT32 Offset,
214 IN UINT8 Count,
215 IN VOID *OrData
216 )
217 {
218 EFI_STATUS Status;
219 UINT64 Data;
220 UINT64 Or;
221
222 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
223 if (EFI_ERROR (Status)) {
224 return Status;
225 }
226
227 if (Count == 1) {
228 Or = *(UINT8*) OrData;
229 } else if (Count == 2) {
230 Or = *(UINT16*) OrData;
231 } else if (Count == 4) {
232 Or = *(UINT32*) OrData;
233 } else if (Count == 8) {
234 Or = *(UINT64*) OrData;
235 } else {
236 return EFI_INVALID_PARAMETER;
237 }
238
239 Data |= Or;
240 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
241
242 return Status;
243 }
244
245 /**
246 Do AND operation with the value of the specified SD/MMC host controller mmio register.
247
248 @param[in] PciIo The PCI IO protocol instance.
249 @param[in] BarIndex The BAR index of the standard PCI Configuration
250 header to use as the base address for the memory
251 operation to perform.
252 @param[in] Offset The offset within the selected BAR to start the
253 memory operation.
254 @param[in] Count The width of the mmio register in bytes.
255 Must be 1, 2 , 4 or 8 bytes.
256 @param[in] AndData The pointer to the data used to do AND operation.
257 The caller is responsible for having ownership of
258 the data buffer and ensuring its size not less than
259 Count bytes.
260
261 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
262 @retval EFI_SUCCESS The AND operation succeeds.
263 @retval Others The AND operation fails.
264
265 **/
266 EFI_STATUS
267 EFIAPI
268 SdMmcHcAndMmio (
269 IN EFI_PCI_IO_PROTOCOL *PciIo,
270 IN UINT8 BarIndex,
271 IN UINT32 Offset,
272 IN UINT8 Count,
273 IN VOID *AndData
274 )
275 {
276 EFI_STATUS Status;
277 UINT64 Data;
278 UINT64 And;
279
280 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
281 if (EFI_ERROR (Status)) {
282 return Status;
283 }
284
285 if (Count == 1) {
286 And = *(UINT8*) AndData;
287 } else if (Count == 2) {
288 And = *(UINT16*) AndData;
289 } else if (Count == 4) {
290 And = *(UINT32*) AndData;
291 } else if (Count == 8) {
292 And = *(UINT64*) AndData;
293 } else {
294 return EFI_INVALID_PARAMETER;
295 }
296
297 Data &= And;
298 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
299
300 return Status;
301 }
302
303 /**
304 Wait for the value of the specified MMIO register set to the test value.
305
306 @param[in] PciIo The PCI IO protocol instance.
307 @param[in] BarIndex The BAR index of the standard PCI Configuration
308 header to use as the base address for the memory
309 operation to perform.
310 @param[in] Offset The offset within the selected BAR to start the
311 memory operation.
312 @param[in] Count The width of the mmio register in bytes.
313 Must be 1, 2, 4 or 8 bytes.
314 @param[in] MaskValue The mask value of memory.
315 @param[in] TestValue The test value of memory.
316
317 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
318 @retval EFI_SUCCESS The MMIO register has expected value.
319 @retval Others The MMIO operation fails.
320
321 **/
322 EFI_STATUS
323 EFIAPI
324 SdMmcHcCheckMmioSet (
325 IN EFI_PCI_IO_PROTOCOL *PciIo,
326 IN UINT8 BarIndex,
327 IN UINT32 Offset,
328 IN UINT8 Count,
329 IN UINT64 MaskValue,
330 IN UINT64 TestValue
331 )
332 {
333 EFI_STATUS Status;
334 UINT64 Value;
335
336 //
337 // Access PCI MMIO space to see if the value is the tested one.
338 //
339 Value = 0;
340 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
341 if (EFI_ERROR (Status)) {
342 return Status;
343 }
344
345 Value &= MaskValue;
346
347 if (Value == TestValue) {
348 return EFI_SUCCESS;
349 }
350
351 return EFI_NOT_READY;
352 }
353
354 /**
355 Wait for the value of the specified MMIO register set to the test value.
356
357 @param[in] PciIo The PCI IO protocol instance.
358 @param[in] BarIndex The BAR index of the standard PCI Configuration
359 header to use as the base address for the memory
360 operation to perform.
361 @param[in] Offset The offset within the selected BAR to start the
362 memory operation.
363 @param[in] Count The width of the mmio register in bytes.
364 Must be 1, 2, 4 or 8 bytes.
365 @param[in] MaskValue The mask value of memory.
366 @param[in] TestValue The test value of memory.
367 @param[in] Timeout The time out value for wait memory set, uses 1
368 microsecond as a unit.
369
370 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
371 range.
372 @retval EFI_SUCCESS The MMIO register has expected value.
373 @retval Others The MMIO operation fails.
374
375 **/
376 EFI_STATUS
377 EFIAPI
378 SdMmcHcWaitMmioSet (
379 IN EFI_PCI_IO_PROTOCOL *PciIo,
380 IN UINT8 BarIndex,
381 IN UINT32 Offset,
382 IN UINT8 Count,
383 IN UINT64 MaskValue,
384 IN UINT64 TestValue,
385 IN UINT64 Timeout
386 )
387 {
388 EFI_STATUS Status;
389 BOOLEAN InfiniteWait;
390
391 if (Timeout == 0) {
392 InfiniteWait = TRUE;
393 } else {
394 InfiniteWait = FALSE;
395 }
396
397 while (InfiniteWait || (Timeout > 0)) {
398 Status = SdMmcHcCheckMmioSet (
399 PciIo,
400 BarIndex,
401 Offset,
402 Count,
403 MaskValue,
404 TestValue
405 );
406 if (Status != EFI_NOT_READY) {
407 return Status;
408 }
409
410 //
411 // Stall for 1 microsecond.
412 //
413 gBS->Stall (1);
414
415 Timeout--;
416 }
417
418 return EFI_TIMEOUT;
419 }
420
421 /**
422 Get the controller version information from the specified slot.
423
424 @param[in] PciIo The PCI IO protocol instance.
425 @param[in] Slot The slot number of the SD card to send the command to.
426 @param[out] Version The buffer to store the version information.
427
428 @retval EFI_SUCCESS The operation executes successfully.
429 @retval Others The operation fails.
430
431 **/
432 EFI_STATUS
433 SdMmcHcGetControllerVersion (
434 IN EFI_PCI_IO_PROTOCOL *PciIo,
435 IN UINT8 Slot,
436 OUT UINT16 *Version
437 )
438 {
439 EFI_STATUS Status;
440
441 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);
442 if (EFI_ERROR (Status)) {
443 return Status;
444 }
445
446 *Version &= 0xFF;
447
448 return EFI_SUCCESS;
449 }
450
451 /**
452 Software reset the specified SD/MMC host controller and enable all interrupts.
453
454 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
455 @param[in] Slot The slot number of the SD card to send the command to.
456
457 @retval EFI_SUCCESS The software reset executes successfully.
458 @retval Others The software reset fails.
459
460 **/
461 EFI_STATUS
462 SdMmcHcReset (
463 IN SD_MMC_HC_PRIVATE_DATA *Private,
464 IN UINT8 Slot
465 )
466 {
467 EFI_STATUS Status;
468 UINT8 SwReset;
469 EFI_PCI_IO_PROTOCOL *PciIo;
470
471 //
472 // Notify the SD/MMC override protocol that we are about to reset
473 // the SD/MMC host controller.
474 //
475 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
476 Status = mOverride->NotifyPhase (
477 Private->ControllerHandle,
478 Slot,
479 EdkiiSdMmcResetPre,
480 NULL);
481 if (EFI_ERROR (Status)) {
482 DEBUG ((DEBUG_WARN,
483 "%a: SD/MMC pre reset notifier callback failed - %r\n",
484 __FUNCTION__, Status));
485 return Status;
486 }
487 }
488
489 PciIo = Private->PciIo;
490 SwReset = BIT0;
491 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
492
493 if (EFI_ERROR (Status)) {
494 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
495 return Status;
496 }
497
498 Status = SdMmcHcWaitMmioSet (
499 PciIo,
500 Slot,
501 SD_MMC_HC_SW_RST,
502 sizeof (SwReset),
503 BIT0,
504 0x00,
505 SD_MMC_HC_GENERIC_TIMEOUT
506 );
507 if (EFI_ERROR (Status)) {
508 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
509 return Status;
510 }
511
512 //
513 // Enable all interrupt after reset all.
514 //
515 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
516 if (EFI_ERROR (Status)) {
517 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
518 Status));
519 return Status;
520 }
521
522 //
523 // Notify the SD/MMC override protocol that we have just reset
524 // the SD/MMC host controller.
525 //
526 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
527 Status = mOverride->NotifyPhase (
528 Private->ControllerHandle,
529 Slot,
530 EdkiiSdMmcResetPost,
531 NULL);
532 if (EFI_ERROR (Status)) {
533 DEBUG ((DEBUG_WARN,
534 "%a: SD/MMC post reset notifier callback failed - %r\n",
535 __FUNCTION__, Status));
536 }
537 }
538
539 return Status;
540 }
541
542 /**
543 Set all interrupt status bits in Normal and Error Interrupt Status Enable
544 register.
545
546 @param[in] PciIo The PCI IO protocol instance.
547 @param[in] Slot The slot number of the SD card to send the command to.
548
549 @retval EFI_SUCCESS The operation executes successfully.
550 @retval Others The operation fails.
551
552 **/
553 EFI_STATUS
554 SdMmcHcEnableInterrupt (
555 IN EFI_PCI_IO_PROTOCOL *PciIo,
556 IN UINT8 Slot
557 )
558 {
559 EFI_STATUS Status;
560 UINT16 IntStatus;
561
562 //
563 // Enable all bits in Error Interrupt Status Enable Register
564 //
565 IntStatus = 0xFFFF;
566 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
567 if (EFI_ERROR (Status)) {
568 return Status;
569 }
570 //
571 // Enable all bits in Normal Interrupt Status Enable Register
572 //
573 IntStatus = 0xFFFF;
574 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
575
576 return Status;
577 }
578
579 /**
580 Get the capability data from the specified slot.
581
582 @param[in] PciIo The PCI IO protocol instance.
583 @param[in] Slot The slot number of the SD card to send the command to.
584 @param[out] Capability The buffer to store the capability data.
585
586 @retval EFI_SUCCESS The operation executes successfully.
587 @retval Others The operation fails.
588
589 **/
590 EFI_STATUS
591 SdMmcHcGetCapability (
592 IN EFI_PCI_IO_PROTOCOL *PciIo,
593 IN UINT8 Slot,
594 OUT SD_MMC_HC_SLOT_CAP *Capability
595 )
596 {
597 EFI_STATUS Status;
598 UINT64 Cap;
599
600 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
601 if (EFI_ERROR (Status)) {
602 return Status;
603 }
604
605 CopyMem (Capability, &Cap, sizeof (Cap));
606
607 return EFI_SUCCESS;
608 }
609
610 /**
611 Get the maximum current capability data from the specified slot.
612
613 @param[in] PciIo The PCI IO protocol instance.
614 @param[in] Slot The slot number of the SD card to send the command to.
615 @param[out] MaxCurrent The buffer to store the maximum current capability data.
616
617 @retval EFI_SUCCESS The operation executes successfully.
618 @retval Others The operation fails.
619
620 **/
621 EFI_STATUS
622 SdMmcHcGetMaxCurrent (
623 IN EFI_PCI_IO_PROTOCOL *PciIo,
624 IN UINT8 Slot,
625 OUT UINT64 *MaxCurrent
626 )
627 {
628 EFI_STATUS Status;
629
630 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
631
632 return Status;
633 }
634
635 /**
636 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
637 slot.
638
639 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
640
641 @param[in] PciIo The PCI IO protocol instance.
642 @param[in] Slot The slot number of the SD card to send the command to.
643 @param[out] MediaPresent The pointer to the media present boolean value.
644
645 @retval EFI_SUCCESS There is no media change happened.
646 @retval EFI_MEDIA_CHANGED There is media change happened.
647 @retval Others The detection fails.
648
649 **/
650 EFI_STATUS
651 SdMmcHcCardDetect (
652 IN EFI_PCI_IO_PROTOCOL *PciIo,
653 IN UINT8 Slot,
654 OUT BOOLEAN *MediaPresent
655 )
656 {
657 EFI_STATUS Status;
658 UINT16 Data;
659 UINT32 PresentState;
660
661 //
662 // Check Present State Register to see if there is a card presented.
663 //
664 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
665 if (EFI_ERROR (Status)) {
666 return Status;
667 }
668
669 if ((PresentState & BIT16) != 0) {
670 *MediaPresent = TRUE;
671 } else {
672 *MediaPresent = FALSE;
673 }
674
675 //
676 // Check Normal Interrupt Status Register
677 //
678 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
679 if (EFI_ERROR (Status)) {
680 return Status;
681 }
682
683 if ((Data & (BIT6 | BIT7)) != 0) {
684 //
685 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
686 //
687 Data &= BIT6 | BIT7;
688 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
689 if (EFI_ERROR (Status)) {
690 return Status;
691 }
692
693 return EFI_MEDIA_CHANGED;
694 }
695
696 return EFI_SUCCESS;
697 }
698
699 /**
700 Stop SD/MMC card clock.
701
702 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
703
704 @param[in] PciIo The PCI IO protocol instance.
705 @param[in] Slot The slot number of the SD card to send the command to.
706
707 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
708 @retval Others Fail to stop SD/MMC clock.
709
710 **/
711 EFI_STATUS
712 SdMmcHcStopClock (
713 IN EFI_PCI_IO_PROTOCOL *PciIo,
714 IN UINT8 Slot
715 )
716 {
717 EFI_STATUS Status;
718 UINT32 PresentState;
719 UINT16 ClockCtrl;
720
721 //
722 // Ensure no SD transactions are occurring on the SD Bus by
723 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
724 // in the Present State register to be 0.
725 //
726 Status = SdMmcHcWaitMmioSet (
727 PciIo,
728 Slot,
729 SD_MMC_HC_PRESENT_STATE,
730 sizeof (PresentState),
731 BIT0 | BIT1,
732 0,
733 SD_MMC_HC_GENERIC_TIMEOUT
734 );
735 if (EFI_ERROR (Status)) {
736 return Status;
737 }
738
739 //
740 // Set SD Clock Enable in the Clock Control register to 0
741 //
742 ClockCtrl = (UINT16)~BIT2;
743 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
744
745 return Status;
746 }
747
748 /**
749 SD/MMC card clock supply.
750
751 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
752
753 @param[in] PciIo The PCI IO protocol instance.
754 @param[in] Slot The slot number of the SD card to send the command to.
755 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
756 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
757 @param[in] ControllerVer The version of host controller.
758
759 @retval EFI_SUCCESS The clock is supplied successfully.
760 @retval Others The clock isn't supplied successfully.
761
762 **/
763 EFI_STATUS
764 SdMmcHcClockSupply (
765 IN EFI_PCI_IO_PROTOCOL *PciIo,
766 IN UINT8 Slot,
767 IN UINT64 ClockFreq,
768 IN UINT32 BaseClkFreq,
769 IN UINT16 ControllerVer
770 )
771 {
772 EFI_STATUS Status;
773 UINT32 SettingFreq;
774 UINT32 Divisor;
775 UINT32 Remainder;
776 UINT16 ClockCtrl;
777
778 //
779 // Calculate a divisor for SD clock frequency
780 //
781 ASSERT (BaseClkFreq != 0);
782
783 if (ClockFreq == 0) {
784 return EFI_INVALID_PARAMETER;
785 }
786
787 if (ClockFreq > (BaseClkFreq * 1000)) {
788 ClockFreq = BaseClkFreq * 1000;
789 }
790
791 //
792 // Calculate the divisor of base frequency.
793 //
794 Divisor = 0;
795 SettingFreq = BaseClkFreq * 1000;
796 while (ClockFreq < SettingFreq) {
797 Divisor++;
798
799 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
800 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
801 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
802 break;
803 }
804 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
805 SettingFreq ++;
806 }
807 }
808
809 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
810
811 //
812 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
813 //
814 if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&
815 (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {
816 ASSERT (Divisor <= 0x3FF);
817 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
818 } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||
819 (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {
820 //
821 // Only the most significant bit can be used as divisor.
822 //
823 if (((Divisor - 1) & Divisor) != 0) {
824 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
825 }
826 ASSERT (Divisor <= 0x80);
827 ClockCtrl = (Divisor & 0xFF) << 8;
828 } else {
829 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
830 return EFI_UNSUPPORTED;
831 }
832
833 //
834 // Stop bus clock at first
835 //
836 Status = SdMmcHcStopClock (PciIo, Slot);
837 if (EFI_ERROR (Status)) {
838 return Status;
839 }
840
841 //
842 // Supply clock frequency with specified divisor
843 //
844 ClockCtrl |= BIT0;
845 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
846 if (EFI_ERROR (Status)) {
847 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
848 return Status;
849 }
850
851 //
852 // Wait Internal Clock Stable in the Clock Control register to be 1
853 //
854 Status = SdMmcHcWaitMmioSet (
855 PciIo,
856 Slot,
857 SD_MMC_HC_CLOCK_CTRL,
858 sizeof (ClockCtrl),
859 BIT1,
860 BIT1,
861 SD_MMC_HC_GENERIC_TIMEOUT
862 );
863 if (EFI_ERROR (Status)) {
864 return Status;
865 }
866
867 //
868 // Set SD Clock Enable in the Clock Control register to 1
869 //
870 ClockCtrl = BIT2;
871 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
872
873 return Status;
874 }
875
876 /**
877 SD/MMC bus power control.
878
879 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
880
881 @param[in] PciIo The PCI IO protocol instance.
882 @param[in] Slot The slot number of the SD card to send the command to.
883 @param[in] PowerCtrl The value setting to the power control register.
884
885 @retval TRUE There is a SD/MMC card attached.
886 @retval FALSE There is no a SD/MMC card attached.
887
888 **/
889 EFI_STATUS
890 SdMmcHcPowerControl (
891 IN EFI_PCI_IO_PROTOCOL *PciIo,
892 IN UINT8 Slot,
893 IN UINT8 PowerCtrl
894 )
895 {
896 EFI_STATUS Status;
897
898 //
899 // Clr SD Bus Power
900 //
901 PowerCtrl &= (UINT8)~BIT0;
902 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
903 if (EFI_ERROR (Status)) {
904 return Status;
905 }
906
907 //
908 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
909 //
910 PowerCtrl |= BIT0;
911 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
912
913 return Status;
914 }
915
916 /**
917 Set the SD/MMC bus width.
918
919 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
920
921 @param[in] PciIo The PCI IO protocol instance.
922 @param[in] Slot The slot number of the SD card to send the command to.
923 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
924
925 @retval EFI_SUCCESS The bus width is set successfully.
926 @retval Others The bus width isn't set successfully.
927
928 **/
929 EFI_STATUS
930 SdMmcHcSetBusWidth (
931 IN EFI_PCI_IO_PROTOCOL *PciIo,
932 IN UINT8 Slot,
933 IN UINT16 BusWidth
934 )
935 {
936 EFI_STATUS Status;
937 UINT8 HostCtrl1;
938
939 if (BusWidth == 1) {
940 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
941 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
942 } else if (BusWidth == 4) {
943 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
944 if (EFI_ERROR (Status)) {
945 return Status;
946 }
947 HostCtrl1 |= BIT1;
948 HostCtrl1 &= (UINT8)~BIT5;
949 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
950 } else if (BusWidth == 8) {
951 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
952 if (EFI_ERROR (Status)) {
953 return Status;
954 }
955 HostCtrl1 &= (UINT8)~BIT1;
956 HostCtrl1 |= BIT5;
957 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
958 } else {
959 ASSERT (FALSE);
960 return EFI_INVALID_PARAMETER;
961 }
962
963 return Status;
964 }
965
966 /**
967 Configure V4 controller enhancements at initialization.
968
969 @param[in] PciIo The PCI IO protocol instance.
970 @param[in] Slot The slot number of the SD card to send the command to.
971 @param[in] Capability The capability of the slot.
972 @param[in] ControllerVer The version of host controller.
973
974 @retval EFI_SUCCESS The clock is supplied successfully.
975
976 **/
977 EFI_STATUS
978 SdMmcHcInitV4Enhancements (
979 IN EFI_PCI_IO_PROTOCOL *PciIo,
980 IN UINT8 Slot,
981 IN SD_MMC_HC_SLOT_CAP Capability,
982 IN UINT16 ControllerVer
983 )
984 {
985 EFI_STATUS Status;
986 UINT16 HostCtrl2;
987
988 //
989 // Check if controller version V4 or higher
990 //
991 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
992 HostCtrl2 = SD_MMC_HC_V4_EN;
993 //
994 // Check if V4 64bit support is available
995 //
996 if (Capability.SysBus64V4 != 0) {
997 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
998 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
999 }
1000 //
1001 // Check if controller version V4.10 or higher
1002 //
1003 if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {
1004 HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;
1005 DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));
1006 }
1007 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1008 if (EFI_ERROR (Status)) {
1009 return Status;
1010 }
1011 }
1012
1013 return EFI_SUCCESS;
1014 }
1015
1016 /**
1017 Supply SD/MMC card with lowest clock frequency at initialization.
1018
1019 @param[in] PciIo The PCI IO protocol instance.
1020 @param[in] Slot The slot number of the SD card to send the command to.
1021 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
1022 @param[in] ControllerVer The version of host controller.
1023
1024 @retval EFI_SUCCESS The clock is supplied successfully.
1025 @retval Others The clock isn't supplied successfully.
1026
1027 **/
1028 EFI_STATUS
1029 SdMmcHcInitClockFreq (
1030 IN EFI_PCI_IO_PROTOCOL *PciIo,
1031 IN UINT8 Slot,
1032 IN UINT32 BaseClkFreq,
1033 IN UINT16 ControllerVer
1034 )
1035 {
1036 EFI_STATUS Status;
1037 UINT32 InitFreq;
1038
1039 //
1040 // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
1041 // the Capability Register 1 can be zero, which means a need for obtaining
1042 // the clock frequency via another method. Fail in case it is not updated
1043 // by SW at this point.
1044 //
1045 if (BaseClkFreq == 0) {
1046 //
1047 // Don't support get Base Clock Frequency information via another method
1048 //
1049 return EFI_UNSUPPORTED;
1050 }
1051 //
1052 // Supply 400KHz clock frequency at initialization phase.
1053 //
1054 InitFreq = 400;
1055 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq, ControllerVer);
1056 return Status;
1057 }
1058
1059 /**
1060 Supply SD/MMC card with maximum voltage at initialization.
1061
1062 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1063
1064 @param[in] PciIo The PCI IO protocol instance.
1065 @param[in] Slot The slot number of the SD card to send the command to.
1066 @param[in] Capability The capability of the slot.
1067
1068 @retval EFI_SUCCESS The voltage is supplied successfully.
1069 @retval Others The voltage isn't supplied successfully.
1070
1071 **/
1072 EFI_STATUS
1073 SdMmcHcInitPowerVoltage (
1074 IN EFI_PCI_IO_PROTOCOL *PciIo,
1075 IN UINT8 Slot,
1076 IN SD_MMC_HC_SLOT_CAP Capability
1077 )
1078 {
1079 EFI_STATUS Status;
1080 UINT8 MaxVoltage;
1081 UINT8 HostCtrl2;
1082
1083 //
1084 // Calculate supported maximum voltage according to SD Bus Voltage Select
1085 //
1086 if (Capability.Voltage33 != 0) {
1087 //
1088 // Support 3.3V
1089 //
1090 MaxVoltage = 0x0E;
1091 } else if (Capability.Voltage30 != 0) {
1092 //
1093 // Support 3.0V
1094 //
1095 MaxVoltage = 0x0C;
1096 } else if (Capability.Voltage18 != 0) {
1097 //
1098 // Support 1.8V
1099 //
1100 MaxVoltage = 0x0A;
1101 HostCtrl2 = BIT3;
1102 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1103 gBS->Stall (5000);
1104 if (EFI_ERROR (Status)) {
1105 return Status;
1106 }
1107 } else {
1108 ASSERT (FALSE);
1109 return EFI_DEVICE_ERROR;
1110 }
1111
1112 //
1113 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1114 //
1115 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1116
1117 return Status;
1118 }
1119
1120 /**
1121 Initialize the Timeout Control register with most conservative value at initialization.
1122
1123 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1124
1125 @param[in] PciIo The PCI IO protocol instance.
1126 @param[in] Slot The slot number of the SD card to send the command to.
1127
1128 @retval EFI_SUCCESS The timeout control register is configured successfully.
1129 @retval Others The timeout control register isn't configured successfully.
1130
1131 **/
1132 EFI_STATUS
1133 SdMmcHcInitTimeoutCtrl (
1134 IN EFI_PCI_IO_PROTOCOL *PciIo,
1135 IN UINT8 Slot
1136 )
1137 {
1138 EFI_STATUS Status;
1139 UINT8 Timeout;
1140
1141 Timeout = 0x0E;
1142 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1143
1144 return Status;
1145 }
1146
1147 /**
1148 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1149 at initialization.
1150
1151 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1152 @param[in] Slot The slot number of the SD card to send the command to.
1153
1154 @retval EFI_SUCCESS The host controller is initialized successfully.
1155 @retval Others The host controller isn't initialized successfully.
1156
1157 **/
1158 EFI_STATUS
1159 SdMmcHcInitHost (
1160 IN SD_MMC_HC_PRIVATE_DATA *Private,
1161 IN UINT8 Slot
1162 )
1163 {
1164 EFI_STATUS Status;
1165 EFI_PCI_IO_PROTOCOL *PciIo;
1166 SD_MMC_HC_SLOT_CAP Capability;
1167
1168 //
1169 // Notify the SD/MMC override protocol that we are about to initialize
1170 // the SD/MMC host controller.
1171 //
1172 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1173 Status = mOverride->NotifyPhase (
1174 Private->ControllerHandle,
1175 Slot,
1176 EdkiiSdMmcInitHostPre,
1177 NULL);
1178 if (EFI_ERROR (Status)) {
1179 DEBUG ((DEBUG_WARN,
1180 "%a: SD/MMC pre init notifier callback failed - %r\n",
1181 __FUNCTION__, Status));
1182 return Status;
1183 }
1184 }
1185
1186 PciIo = Private->PciIo;
1187 Capability = Private->Capability[Slot];
1188
1189 Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);
1190 if (EFI_ERROR (Status)) {
1191 return Status;
1192 }
1193
1194 Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
1195 if (EFI_ERROR (Status)) {
1196 return Status;
1197 }
1198
1199 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1200 if (EFI_ERROR (Status)) {
1201 return Status;
1202 }
1203
1204 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1205 if (EFI_ERROR (Status)) {
1206 return Status;
1207 }
1208
1209 //
1210 // Notify the SD/MMC override protocol that we are have just initialized
1211 // the SD/MMC host controller.
1212 //
1213 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1214 Status = mOverride->NotifyPhase (
1215 Private->ControllerHandle,
1216 Slot,
1217 EdkiiSdMmcInitHostPost,
1218 NULL);
1219 if (EFI_ERROR (Status)) {
1220 DEBUG ((DEBUG_WARN,
1221 "%a: SD/MMC post init notifier callback failed - %r\n",
1222 __FUNCTION__, Status));
1223 }
1224 }
1225 return Status;
1226 }
1227
1228 /**
1229 Set SD Host Controler control 2 registry according to selected speed.
1230
1231 @param[in] ControllerHandle The handle of the controller.
1232 @param[in] PciIo The PCI IO protocol instance.
1233 @param[in] Slot The slot number of the SD card to send the command to.
1234 @param[in] Timing The timing to select.
1235
1236 @retval EFI_SUCCESS The timing is set successfully.
1237 @retval Others The timing isn't set successfully.
1238 **/
1239 EFI_STATUS
1240 SdMmcHcUhsSignaling (
1241 IN EFI_HANDLE ControllerHandle,
1242 IN EFI_PCI_IO_PROTOCOL *PciIo,
1243 IN UINT8 Slot,
1244 IN SD_MMC_BUS_MODE Timing
1245 )
1246 {
1247 EFI_STATUS Status;
1248 UINT8 HostCtrl2;
1249
1250 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
1251 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1252 if (EFI_ERROR (Status)) {
1253 return Status;
1254 }
1255
1256 switch (Timing) {
1257 case SdMmcUhsSdr12:
1258 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1259 break;
1260 case SdMmcUhsSdr25:
1261 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1262 break;
1263 case SdMmcUhsSdr50:
1264 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1265 break;
1266 case SdMmcUhsSdr104:
1267 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1268 break;
1269 case SdMmcUhsDdr50:
1270 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1271 break;
1272 case SdMmcMmcLegacy:
1273 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1274 break;
1275 case SdMmcMmcHsSdr:
1276 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1277 break;
1278 case SdMmcMmcHsDdr:
1279 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1280 break;
1281 case SdMmcMmcHs200:
1282 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1283 break;
1284 case SdMmcMmcHs400:
1285 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1286 break;
1287 default:
1288 HostCtrl2 = 0;
1289 break;
1290 }
1291 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1292 if (EFI_ERROR (Status)) {
1293 return Status;
1294 }
1295
1296 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1297 Status = mOverride->NotifyPhase (
1298 ControllerHandle,
1299 Slot,
1300 EdkiiSdMmcUhsSignaling,
1301 &Timing
1302 );
1303 if (EFI_ERROR (Status)) {
1304 DEBUG ((
1305 DEBUG_ERROR,
1306 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1307 __FUNCTION__,
1308 Status
1309 ));
1310 return Status;
1311 }
1312 }
1313
1314 return EFI_SUCCESS;
1315 }
1316
1317 /**
1318 Turn on/off LED.
1319
1320 @param[in] PciIo The PCI IO protocol instance.
1321 @param[in] Slot The slot number of the SD card to send the command to.
1322 @param[in] On The boolean to turn on/off LED.
1323
1324 @retval EFI_SUCCESS The LED is turned on/off successfully.
1325 @retval Others The LED isn't turned on/off successfully.
1326
1327 **/
1328 EFI_STATUS
1329 SdMmcHcLedOnOff (
1330 IN EFI_PCI_IO_PROTOCOL *PciIo,
1331 IN UINT8 Slot,
1332 IN BOOLEAN On
1333 )
1334 {
1335 EFI_STATUS Status;
1336 UINT8 HostCtrl1;
1337
1338 if (On) {
1339 HostCtrl1 = BIT0;
1340 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1341 } else {
1342 HostCtrl1 = (UINT8)~BIT0;
1343 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1344 }
1345
1346 return Status;
1347 }
1348
1349 /**
1350 Build ADMA descriptor table for transfer.
1351
1352 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1353
1354 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1355 @param[in] ControllerVer The version of host controller.
1356
1357 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1358 @retval Others The ADMA descriptor table isn't created successfully.
1359
1360 **/
1361 EFI_STATUS
1362 BuildAdmaDescTable (
1363 IN SD_MMC_HC_TRB *Trb,
1364 IN UINT16 ControllerVer
1365 )
1366 {
1367 EFI_PHYSICAL_ADDRESS Data;
1368 UINT64 DataLen;
1369 UINT64 Entries;
1370 UINT32 Index;
1371 UINT64 Remaining;
1372 UINT64 Address;
1373 UINTN TableSize;
1374 EFI_PCI_IO_PROTOCOL *PciIo;
1375 EFI_STATUS Status;
1376 UINTN Bytes;
1377 BOOLEAN AddressingMode64;
1378 BOOLEAN DataLength26;
1379 UINT32 AdmaMaxDataPerLine;
1380 UINT32 DescSize;
1381 VOID *AdmaDesc;
1382
1383 AddressingMode64 = FALSE;
1384 DataLength26 = FALSE;
1385 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;
1386 DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);
1387 AdmaDesc = NULL;
1388
1389 Data = Trb->DataPhy;
1390 DataLen = Trb->DataLen;
1391 PciIo = Trb->Private->PciIo;
1392
1393 //
1394 // Detect whether 64bit addressing is supported.
1395 //
1396 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
1397 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1398 SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);
1399 if (!EFI_ERROR (Status)) {
1400 AddressingMode64 = TRUE;
1401 DescSize = sizeof (SD_MMC_HC_ADMA_64_DESC_LINE);
1402 }
1403 }
1404 //
1405 // Check for valid ranges in 32bit ADMA Descriptor Table
1406 //
1407 if (!AddressingMode64 &&
1408 ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {
1409 return EFI_INVALID_PARAMETER;
1410 }
1411 //
1412 // Check address field alignment
1413 //
1414 if (AddressingMode64) {
1415 //
1416 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1417 //
1418 if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {
1419 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));
1420 }
1421 } else {
1422 //
1423 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1424 //
1425 if ((Data & (BIT0 | BIT1)) != 0) {
1426 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1427 }
1428 }
1429 //
1430 // Detect whether 26bit data length is supported.
1431 //
1432 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1433 SD_MMC_HC_26_DATA_LEN_ADMA_EN, SD_MMC_HC_26_DATA_LEN_ADMA_EN);
1434 if (!EFI_ERROR (Status)) {
1435 DataLength26 = TRUE;
1436 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;
1437 }
1438
1439 Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
1440 TableSize = (UINTN)MultU64x32 (Entries, DescSize);
1441 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1442 Status = PciIo->AllocateBuffer (
1443 PciIo,
1444 AllocateAnyPages,
1445 EfiBootServicesData,
1446 EFI_SIZE_TO_PAGES (TableSize),
1447 (VOID **)&AdmaDesc,
1448 0
1449 );
1450 if (EFI_ERROR (Status)) {
1451 return EFI_OUT_OF_RESOURCES;
1452 }
1453 ZeroMem (AdmaDesc, TableSize);
1454 Bytes = TableSize;
1455 Status = PciIo->Map (
1456 PciIo,
1457 EfiPciIoOperationBusMasterCommonBuffer,
1458 AdmaDesc,
1459 &Bytes,
1460 &Trb->AdmaDescPhy,
1461 &Trb->AdmaMap
1462 );
1463
1464 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1465 //
1466 // Map error or unable to map the whole RFis buffer into a contiguous region.
1467 //
1468 PciIo->FreeBuffer (
1469 PciIo,
1470 EFI_SIZE_TO_PAGES (TableSize),
1471 AdmaDesc
1472 );
1473 return EFI_OUT_OF_RESOURCES;
1474 }
1475
1476 if ((!AddressingMode64) &&
1477 (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1478 //
1479 // The ADMA doesn't support 64bit addressing.
1480 //
1481 PciIo->Unmap (
1482 PciIo,
1483 Trb->AdmaMap
1484 );
1485 PciIo->FreeBuffer (
1486 PciIo,
1487 EFI_SIZE_TO_PAGES (TableSize),
1488 AdmaDesc
1489 );
1490 return EFI_DEVICE_ERROR;
1491 }
1492
1493 Remaining = DataLen;
1494 Address = Data;
1495 if (!AddressingMode64) {
1496 Trb->Adma32Desc = AdmaDesc;
1497 Trb->Adma64Desc = NULL;
1498 } else {
1499 Trb->Adma64Desc = AdmaDesc;
1500 Trb->Adma32Desc = NULL;
1501 }
1502 for (Index = 0; Index < Entries; Index++) {
1503 if (!AddressingMode64) {
1504 if (Remaining <= AdmaMaxDataPerLine) {
1505 Trb->Adma32Desc[Index].Valid = 1;
1506 Trb->Adma32Desc[Index].Act = 2;
1507 if (DataLength26) {
1508 Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1509 }
1510 Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1511 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1512 break;
1513 } else {
1514 Trb->Adma32Desc[Index].Valid = 1;
1515 Trb->Adma32Desc[Index].Act = 2;
1516 if (DataLength26) {
1517 Trb->Adma32Desc[Index].UpperLength = 0;
1518 }
1519 Trb->Adma32Desc[Index].LowerLength = 0;
1520 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1521 }
1522 } else {
1523 if (Remaining <= AdmaMaxDataPerLine) {
1524 Trb->Adma64Desc[Index].Valid = 1;
1525 Trb->Adma64Desc[Index].Act = 2;
1526 if (DataLength26) {
1527 Trb->Adma64Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1528 }
1529 Trb->Adma64Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1530 Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;
1531 Trb->Adma64Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1532 break;
1533 } else {
1534 Trb->Adma64Desc[Index].Valid = 1;
1535 Trb->Adma64Desc[Index].Act = 2;
1536 if (DataLength26) {
1537 Trb->Adma64Desc[Index].UpperLength = 0;
1538 }
1539 Trb->Adma64Desc[Index].LowerLength = 0;
1540 Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;
1541 Trb->Adma64Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1542 }
1543 }
1544
1545 Remaining -= AdmaMaxDataPerLine;
1546 Address += AdmaMaxDataPerLine;
1547 }
1548
1549 //
1550 // Set the last descriptor line as end of descriptor table
1551 //
1552 AddressingMode64 ? (Trb->Adma64Desc[Index].End = 1) : (Trb->Adma32Desc[Index].End = 1);
1553 return EFI_SUCCESS;
1554 }
1555
1556 /**
1557 Create a new TRB for the SD/MMC cmd request.
1558
1559 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1560 @param[in] Slot The slot number of the SD card to send the command to.
1561 @param[in] Packet A pointer to the SD command data structure.
1562 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1563 not NULL, then nonblocking I/O is performed, and Event
1564 will be signaled when the Packet completes.
1565
1566 @return Created Trb or NULL.
1567
1568 **/
1569 SD_MMC_HC_TRB *
1570 SdMmcCreateTrb (
1571 IN SD_MMC_HC_PRIVATE_DATA *Private,
1572 IN UINT8 Slot,
1573 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1574 IN EFI_EVENT Event
1575 )
1576 {
1577 SD_MMC_HC_TRB *Trb;
1578 EFI_STATUS Status;
1579 EFI_TPL OldTpl;
1580 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1581 EFI_PCI_IO_PROTOCOL *PciIo;
1582 UINTN MapLength;
1583
1584 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1585 if (Trb == NULL) {
1586 return NULL;
1587 }
1588
1589 Trb->Signature = SD_MMC_HC_TRB_SIG;
1590 Trb->Slot = Slot;
1591 Trb->BlockSize = 0x200;
1592 Trb->Packet = Packet;
1593 Trb->Event = Event;
1594 Trb->Started = FALSE;
1595 Trb->Timeout = Packet->Timeout;
1596 Trb->Private = Private;
1597
1598 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1599 Trb->Data = Packet->InDataBuffer;
1600 Trb->DataLen = Packet->InTransferLength;
1601 Trb->Read = TRUE;
1602 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1603 Trb->Data = Packet->OutDataBuffer;
1604 Trb->DataLen = Packet->OutTransferLength;
1605 Trb->Read = FALSE;
1606 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1607 Trb->Data = NULL;
1608 Trb->DataLen = 0;
1609 } else {
1610 goto Error;
1611 }
1612
1613 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1614 Trb->BlockSize = (UINT16)Trb->DataLen;
1615 }
1616
1617 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1618 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1619 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1620 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1621 Trb->Mode = SdMmcPioMode;
1622 } else {
1623 if (Trb->Read) {
1624 Flag = EfiPciIoOperationBusMasterWrite;
1625 } else {
1626 Flag = EfiPciIoOperationBusMasterRead;
1627 }
1628
1629 PciIo = Private->PciIo;
1630 if (Trb->DataLen != 0) {
1631 MapLength = Trb->DataLen;
1632 Status = PciIo->Map (
1633 PciIo,
1634 Flag,
1635 Trb->Data,
1636 &MapLength,
1637 &Trb->DataPhy,
1638 &Trb->DataMap
1639 );
1640 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1641 Status = EFI_BAD_BUFFER_SIZE;
1642 goto Error;
1643 }
1644 }
1645
1646 if (Trb->DataLen == 0) {
1647 Trb->Mode = SdMmcNoData;
1648 } else if (Private->Capability[Slot].Adma2 != 0) {
1649 Trb->Mode = SdMmcAdmaMode;
1650 Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
1651 if (EFI_ERROR (Status)) {
1652 PciIo->Unmap (PciIo, Trb->DataMap);
1653 goto Error;
1654 }
1655 } else if (Private->Capability[Slot].Sdma != 0) {
1656 Trb->Mode = SdMmcSdmaMode;
1657 } else {
1658 Trb->Mode = SdMmcPioMode;
1659 }
1660 }
1661
1662 if (Event != NULL) {
1663 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1664 InsertTailList (&Private->Queue, &Trb->TrbList);
1665 gBS->RestoreTPL (OldTpl);
1666 }
1667
1668 return Trb;
1669
1670 Error:
1671 SdMmcFreeTrb (Trb);
1672 return NULL;
1673 }
1674
1675 /**
1676 Free the resource used by the TRB.
1677
1678 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1679
1680 **/
1681 VOID
1682 SdMmcFreeTrb (
1683 IN SD_MMC_HC_TRB *Trb
1684 )
1685 {
1686 EFI_PCI_IO_PROTOCOL *PciIo;
1687
1688 PciIo = Trb->Private->PciIo;
1689
1690 if (Trb->AdmaMap != NULL) {
1691 PciIo->Unmap (
1692 PciIo,
1693 Trb->AdmaMap
1694 );
1695 }
1696 if (Trb->Adma32Desc != NULL) {
1697 PciIo->FreeBuffer (
1698 PciIo,
1699 Trb->AdmaPages,
1700 Trb->Adma32Desc
1701 );
1702 }
1703 if (Trb->Adma64Desc != NULL) {
1704 PciIo->FreeBuffer (
1705 PciIo,
1706 Trb->AdmaPages,
1707 Trb->Adma64Desc
1708 );
1709 }
1710 if (Trb->DataMap != NULL) {
1711 PciIo->Unmap (
1712 PciIo,
1713 Trb->DataMap
1714 );
1715 }
1716 FreePool (Trb);
1717 return;
1718 }
1719
1720 /**
1721 Check if the env is ready for execute specified TRB.
1722
1723 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1724 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1725
1726 @retval EFI_SUCCESS The env is ready for TRB execution.
1727 @retval EFI_NOT_READY The env is not ready for TRB execution.
1728 @retval Others Some erros happen.
1729
1730 **/
1731 EFI_STATUS
1732 SdMmcCheckTrbEnv (
1733 IN SD_MMC_HC_PRIVATE_DATA *Private,
1734 IN SD_MMC_HC_TRB *Trb
1735 )
1736 {
1737 EFI_STATUS Status;
1738 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1739 EFI_PCI_IO_PROTOCOL *PciIo;
1740 UINT32 PresentState;
1741
1742 Packet = Trb->Packet;
1743
1744 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1745 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1746 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1747 //
1748 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1749 // the Present State register to be 0
1750 //
1751 PresentState = BIT0 | BIT1;
1752 } else {
1753 //
1754 // Wait Command Inhibit (CMD) in the Present State register
1755 // to be 0
1756 //
1757 PresentState = BIT0;
1758 }
1759
1760 PciIo = Private->PciIo;
1761 Status = SdMmcHcCheckMmioSet (
1762 PciIo,
1763 Trb->Slot,
1764 SD_MMC_HC_PRESENT_STATE,
1765 sizeof (PresentState),
1766 PresentState,
1767 0
1768 );
1769
1770 return Status;
1771 }
1772
1773 /**
1774 Wait for the env to be ready for execute specified TRB.
1775
1776 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1777 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1778
1779 @retval EFI_SUCCESS The env is ready for TRB execution.
1780 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1781 @retval Others Some erros happen.
1782
1783 **/
1784 EFI_STATUS
1785 SdMmcWaitTrbEnv (
1786 IN SD_MMC_HC_PRIVATE_DATA *Private,
1787 IN SD_MMC_HC_TRB *Trb
1788 )
1789 {
1790 EFI_STATUS Status;
1791 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1792 UINT64 Timeout;
1793 BOOLEAN InfiniteWait;
1794
1795 //
1796 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1797 //
1798 Packet = Trb->Packet;
1799 Timeout = Packet->Timeout;
1800 if (Timeout == 0) {
1801 InfiniteWait = TRUE;
1802 } else {
1803 InfiniteWait = FALSE;
1804 }
1805
1806 while (InfiniteWait || (Timeout > 0)) {
1807 //
1808 // Check Trb execution result by reading Normal Interrupt Status register.
1809 //
1810 Status = SdMmcCheckTrbEnv (Private, Trb);
1811 if (Status != EFI_NOT_READY) {
1812 return Status;
1813 }
1814 //
1815 // Stall for 1 microsecond.
1816 //
1817 gBS->Stall (1);
1818
1819 Timeout--;
1820 }
1821
1822 return EFI_TIMEOUT;
1823 }
1824
1825 /**
1826 Execute the specified TRB.
1827
1828 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1829 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1830
1831 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1832 @retval Others Some erros happen when sending this request to the host controller.
1833
1834 **/
1835 EFI_STATUS
1836 SdMmcExecTrb (
1837 IN SD_MMC_HC_PRIVATE_DATA *Private,
1838 IN SD_MMC_HC_TRB *Trb
1839 )
1840 {
1841 EFI_STATUS Status;
1842 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1843 EFI_PCI_IO_PROTOCOL *PciIo;
1844 UINT16 Cmd;
1845 UINT16 IntStatus;
1846 UINT32 Argument;
1847 UINT32 BlkCount;
1848 UINT16 BlkSize;
1849 UINT16 TransMode;
1850 UINT8 HostCtrl1;
1851 UINT64 SdmaAddr;
1852 UINT64 AdmaAddr;
1853 BOOLEAN AddressingMode64;
1854
1855 AddressingMode64 = FALSE;
1856
1857 Packet = Trb->Packet;
1858 PciIo = Trb->Private->PciIo;
1859 //
1860 // Clear all bits in Error Interrupt Status Register
1861 //
1862 IntStatus = 0xFFFF;
1863 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1864 if (EFI_ERROR (Status)) {
1865 return Status;
1866 }
1867 //
1868 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1869 //
1870 IntStatus = 0xFF3F;
1871 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1872 if (EFI_ERROR (Status)) {
1873 return Status;
1874 }
1875 //
1876 // Set Host Control 1 register DMA Select field
1877 //
1878 if (Trb->Mode == SdMmcAdmaMode) {
1879 HostCtrl1 = BIT4;
1880 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1881 if (EFI_ERROR (Status)) {
1882 return Status;
1883 }
1884 }
1885
1886 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1887
1888 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1889 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1890 SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);
1891 if (!EFI_ERROR (Status)) {
1892 AddressingMode64 = TRUE;
1893 }
1894 }
1895
1896 if (Trb->Mode == SdMmcSdmaMode) {
1897 if ((!AddressingMode64) &&
1898 ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {
1899 return EFI_INVALID_PARAMETER;
1900 }
1901
1902 SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;
1903
1904 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1905 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);
1906 } else {
1907 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);
1908 }
1909
1910 if (EFI_ERROR (Status)) {
1911 return Status;
1912 }
1913 } else if (Trb->Mode == SdMmcAdmaMode) {
1914 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1915 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1916 if (EFI_ERROR (Status)) {
1917 return Status;
1918 }
1919 }
1920
1921 BlkSize = Trb->BlockSize;
1922 if (Trb->Mode == SdMmcSdmaMode) {
1923 //
1924 // Set SDMA boundary to be 512K bytes.
1925 //
1926 BlkSize |= 0x7000;
1927 }
1928
1929 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1930 if (EFI_ERROR (Status)) {
1931 return Status;
1932 }
1933
1934 BlkCount = 0;
1935 if (Trb->Mode != SdMmcNoData) {
1936 //
1937 // Calcuate Block Count.
1938 //
1939 BlkCount = (Trb->DataLen / Trb->BlockSize);
1940 }
1941 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {
1942 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);
1943 } else {
1944 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);
1945 }
1946 if (EFI_ERROR (Status)) {
1947 return Status;
1948 }
1949
1950 Argument = Packet->SdMmcCmdBlk->CommandArgument;
1951 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1952 if (EFI_ERROR (Status)) {
1953 return Status;
1954 }
1955
1956 TransMode = 0;
1957 if (Trb->Mode != SdMmcNoData) {
1958 if (Trb->Mode != SdMmcPioMode) {
1959 TransMode |= BIT0;
1960 }
1961 if (Trb->Read) {
1962 TransMode |= BIT4;
1963 }
1964 if (BlkCount > 1) {
1965 TransMode |= BIT5 | BIT1;
1966 }
1967 //
1968 // Only SD memory card needs to use AUTO CMD12 feature.
1969 //
1970 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
1971 if (BlkCount > 1) {
1972 TransMode |= BIT2;
1973 }
1974 }
1975 }
1976
1977 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1978 if (EFI_ERROR (Status)) {
1979 return Status;
1980 }
1981
1982 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
1983 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
1984 Cmd |= BIT5;
1985 }
1986 //
1987 // Convert ResponseType to value
1988 //
1989 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1990 switch (Packet->SdMmcCmdBlk->ResponseType) {
1991 case SdMmcResponseTypeR1:
1992 case SdMmcResponseTypeR5:
1993 case SdMmcResponseTypeR6:
1994 case SdMmcResponseTypeR7:
1995 Cmd |= (BIT1 | BIT3 | BIT4);
1996 break;
1997 case SdMmcResponseTypeR2:
1998 Cmd |= (BIT0 | BIT3);
1999 break;
2000 case SdMmcResponseTypeR3:
2001 case SdMmcResponseTypeR4:
2002 Cmd |= BIT1;
2003 break;
2004 case SdMmcResponseTypeR1b:
2005 case SdMmcResponseTypeR5b:
2006 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
2007 break;
2008 default:
2009 ASSERT (FALSE);
2010 break;
2011 }
2012 }
2013 //
2014 // Execute cmd
2015 //
2016 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
2017 return Status;
2018 }
2019
2020 /**
2021 Check the TRB execution result.
2022
2023 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2024 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2025
2026 @retval EFI_SUCCESS The TRB is executed successfully.
2027 @retval EFI_NOT_READY The TRB is not completed for execution.
2028 @retval Others Some erros happen when executing this request.
2029
2030 **/
2031 EFI_STATUS
2032 SdMmcCheckTrbResult (
2033 IN SD_MMC_HC_PRIVATE_DATA *Private,
2034 IN SD_MMC_HC_TRB *Trb
2035 )
2036 {
2037 EFI_STATUS Status;
2038 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2039 UINT16 IntStatus;
2040 UINT32 Response[4];
2041 UINT64 SdmaAddr;
2042 UINT8 Index;
2043 UINT8 SwReset;
2044 UINT32 PioLength;
2045
2046 SwReset = 0;
2047 Packet = Trb->Packet;
2048 //
2049 // Check Trb execution result by reading Normal Interrupt Status register.
2050 //
2051 Status = SdMmcHcRwMmio (
2052 Private->PciIo,
2053 Trb->Slot,
2054 SD_MMC_HC_NOR_INT_STS,
2055 TRUE,
2056 sizeof (IntStatus),
2057 &IntStatus
2058 );
2059 if (EFI_ERROR (Status)) {
2060 goto Done;
2061 }
2062 //
2063 // Check Transfer Complete bit is set or not.
2064 //
2065 if ((IntStatus & BIT1) == BIT1) {
2066 if ((IntStatus & BIT15) == BIT15) {
2067 //
2068 // Read Error Interrupt Status register to check if the error is
2069 // Data Timeout Error.
2070 // If yes, treat it as success as Transfer Complete has higher
2071 // priority than Data Timeout Error.
2072 //
2073 Status = SdMmcHcRwMmio (
2074 Private->PciIo,
2075 Trb->Slot,
2076 SD_MMC_HC_ERR_INT_STS,
2077 TRUE,
2078 sizeof (IntStatus),
2079 &IntStatus
2080 );
2081 if (!EFI_ERROR (Status)) {
2082 if ((IntStatus & BIT4) == BIT4) {
2083 Status = EFI_SUCCESS;
2084 } else {
2085 Status = EFI_DEVICE_ERROR;
2086 }
2087 }
2088 }
2089
2090 goto Done;
2091 }
2092 //
2093 // Check if there is a error happened during cmd execution.
2094 // If yes, then do error recovery procedure to follow SD Host Controller
2095 // Simplified Spec 3.0 section 3.10.1.
2096 //
2097 if ((IntStatus & BIT15) == BIT15) {
2098 Status = SdMmcHcRwMmio (
2099 Private->PciIo,
2100 Trb->Slot,
2101 SD_MMC_HC_ERR_INT_STS,
2102 TRUE,
2103 sizeof (IntStatus),
2104 &IntStatus
2105 );
2106 if (EFI_ERROR (Status)) {
2107 goto Done;
2108 }
2109 if ((IntStatus & 0x0F) != 0) {
2110 SwReset |= BIT1;
2111 }
2112 if ((IntStatus & 0xF0) != 0) {
2113 SwReset |= BIT2;
2114 }
2115
2116 Status = SdMmcHcRwMmio (
2117 Private->PciIo,
2118 Trb->Slot,
2119 SD_MMC_HC_SW_RST,
2120 FALSE,
2121 sizeof (SwReset),
2122 &SwReset
2123 );
2124 if (EFI_ERROR (Status)) {
2125 goto Done;
2126 }
2127 Status = SdMmcHcWaitMmioSet (
2128 Private->PciIo,
2129 Trb->Slot,
2130 SD_MMC_HC_SW_RST,
2131 sizeof (SwReset),
2132 0xFF,
2133 0,
2134 SD_MMC_HC_GENERIC_TIMEOUT
2135 );
2136 if (EFI_ERROR (Status)) {
2137 goto Done;
2138 }
2139
2140 Status = EFI_DEVICE_ERROR;
2141 goto Done;
2142 }
2143 //
2144 // Check if DMA interrupt is signalled for the SDMA transfer.
2145 //
2146 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
2147 //
2148 // Clear DMA interrupt bit.
2149 //
2150 IntStatus = BIT3;
2151 Status = SdMmcHcRwMmio (
2152 Private->PciIo,
2153 Trb->Slot,
2154 SD_MMC_HC_NOR_INT_STS,
2155 FALSE,
2156 sizeof (IntStatus),
2157 &IntStatus
2158 );
2159 if (EFI_ERROR (Status)) {
2160 goto Done;
2161 }
2162 //
2163 // Update SDMA Address register.
2164 //
2165 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
2166
2167 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2168 Status = SdMmcHcRwMmio (
2169 Private->PciIo,
2170 Trb->Slot,
2171 SD_MMC_HC_ADMA_SYS_ADDR,
2172 FALSE,
2173 sizeof (UINT64),
2174 &SdmaAddr
2175 );
2176 } else {
2177 Status = SdMmcHcRwMmio (
2178 Private->PciIo,
2179 Trb->Slot,
2180 SD_MMC_HC_SDMA_ADDR,
2181 FALSE,
2182 sizeof (UINT32),
2183 &SdmaAddr
2184 );
2185 }
2186
2187 if (EFI_ERROR (Status)) {
2188 goto Done;
2189 }
2190 Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
2191 }
2192
2193 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
2194 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
2195 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
2196 if ((IntStatus & BIT0) == BIT0) {
2197 Status = EFI_SUCCESS;
2198 goto Done;
2199 }
2200 }
2201
2202 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
2203 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
2204 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
2205 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
2206 //
2207 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2208 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2209 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2210 //
2211 if ((IntStatus & BIT5) == BIT5) {
2212 //
2213 // Clear Buffer Read Ready interrupt at first.
2214 //
2215 IntStatus = BIT5;
2216 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2217 //
2218 // Read data out from Buffer Port register
2219 //
2220 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
2221 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
2222 }
2223 Status = EFI_SUCCESS;
2224 goto Done;
2225 }
2226 }
2227
2228 Status = EFI_NOT_READY;
2229 Done:
2230 //
2231 // Get response data when the cmd is executed successfully.
2232 //
2233 if (!EFI_ERROR (Status)) {
2234 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2235 for (Index = 0; Index < 4; Index++) {
2236 Status = SdMmcHcRwMmio (
2237 Private->PciIo,
2238 Trb->Slot,
2239 SD_MMC_HC_RESPONSE + Index * 4,
2240 TRUE,
2241 sizeof (UINT32),
2242 &Response[Index]
2243 );
2244 if (EFI_ERROR (Status)) {
2245 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2246 return Status;
2247 }
2248 }
2249 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2250 }
2251 }
2252
2253 if (Status != EFI_NOT_READY) {
2254 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2255 }
2256
2257 return Status;
2258 }
2259
2260 /**
2261 Wait for the TRB execution result.
2262
2263 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2264 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2265
2266 @retval EFI_SUCCESS The TRB is executed successfully.
2267 @retval Others Some erros happen when executing this request.
2268
2269 **/
2270 EFI_STATUS
2271 SdMmcWaitTrbResult (
2272 IN SD_MMC_HC_PRIVATE_DATA *Private,
2273 IN SD_MMC_HC_TRB *Trb
2274 )
2275 {
2276 EFI_STATUS Status;
2277 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2278 UINT64 Timeout;
2279 BOOLEAN InfiniteWait;
2280
2281 Packet = Trb->Packet;
2282 //
2283 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2284 //
2285 Timeout = Packet->Timeout;
2286 if (Timeout == 0) {
2287 InfiniteWait = TRUE;
2288 } else {
2289 InfiniteWait = FALSE;
2290 }
2291
2292 while (InfiniteWait || (Timeout > 0)) {
2293 //
2294 // Check Trb execution result by reading Normal Interrupt Status register.
2295 //
2296 Status = SdMmcCheckTrbResult (Private, Trb);
2297 if (Status != EFI_NOT_READY) {
2298 return Status;
2299 }
2300 //
2301 // Stall for 1 microsecond.
2302 //
2303 gBS->Stall (1);
2304
2305 Timeout--;
2306 }
2307
2308 return EFI_TIMEOUT;
2309 }
2310
EFI Development Kit II mirror for PVE