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MdeModulePkg/SdMmcPciHcDxe: Do not map memory for non DMA transfer
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
5 4.20.
6
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
8
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
12
13 **/
14
15 #include "SdMmcPciHcDxe.h"
16
17 /**
18 Dump the content of SD/MMC host controller's Capability Register.
19
20 @param[in] Slot The slot number of the SD card to send the command to.
21 @param[in] Capability The buffer to store the capability data.
22
23 **/
24 VOID
25 DumpCapabilityReg (
26 IN UINT8 Slot,
27 IN SD_MMC_HC_SLOT_CAP *Capability
28 )
29 {
30 //
31 // Dump Capability Data
32 //
33 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
34 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
35 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
36 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
37 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
38 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
39 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
40 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " SlotType "));
49 if (Capability->SlotType == 0x00) {
50 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
51 } else if (Capability->SlotType == 0x01) {
52 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
53 } else if (Capability->SlotType == 0x02) {
54 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
55 } else {
56 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
57 }
58 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
59 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
60 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
65 if (Capability->TimerCount == 0) {
66 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
67 } else {
68 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
69 }
70 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
71 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
72 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
73 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
74 return;
75 }
76
77 /**
78 Read SlotInfo register from SD/MMC host controller pci config space.
79
80 @param[in] PciIo The PCI IO protocol instance.
81 @param[out] FirstBar The buffer to store the first BAR value.
82 @param[out] SlotNum The buffer to store the supported slot number.
83
84 @retval EFI_SUCCESS The operation succeeds.
85 @retval Others The operation fails.
86
87 **/
88 EFI_STATUS
89 EFIAPI
90 SdMmcHcGetSlotInfo (
91 IN EFI_PCI_IO_PROTOCOL *PciIo,
92 OUT UINT8 *FirstBar,
93 OUT UINT8 *SlotNum
94 )
95 {
96 EFI_STATUS Status;
97 SD_MMC_HC_SLOT_INFO SlotInfo;
98
99 Status = PciIo->Pci.Read (
100 PciIo,
101 EfiPciIoWidthUint8,
102 SD_MMC_HC_SLOT_OFFSET,
103 sizeof (SlotInfo),
104 &SlotInfo
105 );
106 if (EFI_ERROR (Status)) {
107 return Status;
108 }
109
110 *FirstBar = SlotInfo.FirstBar;
111 *SlotNum = SlotInfo.SlotNum + 1;
112 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
113 return EFI_SUCCESS;
114 }
115
116 /**
117 Read/Write specified SD/MMC host controller mmio register.
118
119 @param[in] PciIo The PCI IO protocol instance.
120 @param[in] BarIndex The BAR index of the standard PCI Configuration
121 header to use as the base address for the memory
122 operation to perform.
123 @param[in] Offset The offset within the selected BAR to start the
124 memory operation.
125 @param[in] Read A boolean to indicate it's read or write operation.
126 @param[in] Count The width of the mmio register in bytes.
127 Must be 1, 2 , 4 or 8 bytes.
128 @param[in, out] Data For read operations, the destination buffer to store
129 the results. For write operations, the source buffer
130 to write data from. The caller is responsible for
131 having ownership of the data buffer and ensuring its
132 size not less than Count bytes.
133
134 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
135 @retval EFI_SUCCESS The read/write operation succeeds.
136 @retval Others The read/write operation fails.
137
138 **/
139 EFI_STATUS
140 EFIAPI
141 SdMmcHcRwMmio (
142 IN EFI_PCI_IO_PROTOCOL *PciIo,
143 IN UINT8 BarIndex,
144 IN UINT32 Offset,
145 IN BOOLEAN Read,
146 IN UINT8 Count,
147 IN OUT VOID *Data
148 )
149 {
150 EFI_STATUS Status;
151 EFI_PCI_IO_PROTOCOL_WIDTH Width;
152
153 if ((PciIo == NULL) || (Data == NULL)) {
154 return EFI_INVALID_PARAMETER;
155 }
156
157 switch (Count) {
158 case 1:
159 Width = EfiPciIoWidthUint8;
160 break;
161 case 2:
162 Width = EfiPciIoWidthUint16;
163 Count = 1;
164 break;
165 case 4:
166 Width = EfiPciIoWidthUint32;
167 Count = 1;
168 break;
169 case 8:
170 Width = EfiPciIoWidthUint32;
171 Count = 2;
172 break;
173 default:
174 return EFI_INVALID_PARAMETER;
175 }
176
177 if (Read) {
178 Status = PciIo->Mem.Read (
179 PciIo,
180 Width,
181 BarIndex,
182 (UINT64) Offset,
183 Count,
184 Data
185 );
186 } else {
187 Status = PciIo->Mem.Write (
188 PciIo,
189 Width,
190 BarIndex,
191 (UINT64) Offset,
192 Count,
193 Data
194 );
195 }
196
197 return Status;
198 }
199
200 /**
201 Do OR operation with the value of the specified SD/MMC host controller mmio register.
202
203 @param[in] PciIo The PCI IO protocol instance.
204 @param[in] BarIndex The BAR index of the standard PCI Configuration
205 header to use as the base address for the memory
206 operation to perform.
207 @param[in] Offset The offset within the selected BAR to start the
208 memory operation.
209 @param[in] Count The width of the mmio register in bytes.
210 Must be 1, 2 , 4 or 8 bytes.
211 @param[in] OrData The pointer to the data used to do OR operation.
212 The caller is responsible for having ownership of
213 the data buffer and ensuring its size not less than
214 Count bytes.
215
216 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
217 @retval EFI_SUCCESS The OR operation succeeds.
218 @retval Others The OR operation fails.
219
220 **/
221 EFI_STATUS
222 EFIAPI
223 SdMmcHcOrMmio (
224 IN EFI_PCI_IO_PROTOCOL *PciIo,
225 IN UINT8 BarIndex,
226 IN UINT32 Offset,
227 IN UINT8 Count,
228 IN VOID *OrData
229 )
230 {
231 EFI_STATUS Status;
232 UINT64 Data;
233 UINT64 Or;
234
235 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
236 if (EFI_ERROR (Status)) {
237 return Status;
238 }
239
240 if (Count == 1) {
241 Or = *(UINT8*) OrData;
242 } else if (Count == 2) {
243 Or = *(UINT16*) OrData;
244 } else if (Count == 4) {
245 Or = *(UINT32*) OrData;
246 } else if (Count == 8) {
247 Or = *(UINT64*) OrData;
248 } else {
249 return EFI_INVALID_PARAMETER;
250 }
251
252 Data |= Or;
253 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
254
255 return Status;
256 }
257
258 /**
259 Do AND operation with the value of the specified SD/MMC host controller mmio register.
260
261 @param[in] PciIo The PCI IO protocol instance.
262 @param[in] BarIndex The BAR index of the standard PCI Configuration
263 header to use as the base address for the memory
264 operation to perform.
265 @param[in] Offset The offset within the selected BAR to start the
266 memory operation.
267 @param[in] Count The width of the mmio register in bytes.
268 Must be 1, 2 , 4 or 8 bytes.
269 @param[in] AndData The pointer to the data used to do AND operation.
270 The caller is responsible for having ownership of
271 the data buffer and ensuring its size not less than
272 Count bytes.
273
274 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
275 @retval EFI_SUCCESS The AND operation succeeds.
276 @retval Others The AND operation fails.
277
278 **/
279 EFI_STATUS
280 EFIAPI
281 SdMmcHcAndMmio (
282 IN EFI_PCI_IO_PROTOCOL *PciIo,
283 IN UINT8 BarIndex,
284 IN UINT32 Offset,
285 IN UINT8 Count,
286 IN VOID *AndData
287 )
288 {
289 EFI_STATUS Status;
290 UINT64 Data;
291 UINT64 And;
292
293 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
294 if (EFI_ERROR (Status)) {
295 return Status;
296 }
297
298 if (Count == 1) {
299 And = *(UINT8*) AndData;
300 } else if (Count == 2) {
301 And = *(UINT16*) AndData;
302 } else if (Count == 4) {
303 And = *(UINT32*) AndData;
304 } else if (Count == 8) {
305 And = *(UINT64*) AndData;
306 } else {
307 return EFI_INVALID_PARAMETER;
308 }
309
310 Data &= And;
311 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
312
313 return Status;
314 }
315
316 /**
317 Wait for the value of the specified MMIO register set to the test value.
318
319 @param[in] PciIo The PCI IO protocol instance.
320 @param[in] BarIndex The BAR index of the standard PCI Configuration
321 header to use as the base address for the memory
322 operation to perform.
323 @param[in] Offset The offset within the selected BAR to start the
324 memory operation.
325 @param[in] Count The width of the mmio register in bytes.
326 Must be 1, 2, 4 or 8 bytes.
327 @param[in] MaskValue The mask value of memory.
328 @param[in] TestValue The test value of memory.
329
330 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
331 @retval EFI_SUCCESS The MMIO register has expected value.
332 @retval Others The MMIO operation fails.
333
334 **/
335 EFI_STATUS
336 EFIAPI
337 SdMmcHcCheckMmioSet (
338 IN EFI_PCI_IO_PROTOCOL *PciIo,
339 IN UINT8 BarIndex,
340 IN UINT32 Offset,
341 IN UINT8 Count,
342 IN UINT64 MaskValue,
343 IN UINT64 TestValue
344 )
345 {
346 EFI_STATUS Status;
347 UINT64 Value;
348
349 //
350 // Access PCI MMIO space to see if the value is the tested one.
351 //
352 Value = 0;
353 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
354 if (EFI_ERROR (Status)) {
355 return Status;
356 }
357
358 Value &= MaskValue;
359
360 if (Value == TestValue) {
361 return EFI_SUCCESS;
362 }
363
364 return EFI_NOT_READY;
365 }
366
367 /**
368 Wait for the value of the specified MMIO register set to the test value.
369
370 @param[in] PciIo The PCI IO protocol instance.
371 @param[in] BarIndex The BAR index of the standard PCI Configuration
372 header to use as the base address for the memory
373 operation to perform.
374 @param[in] Offset The offset within the selected BAR to start the
375 memory operation.
376 @param[in] Count The width of the mmio register in bytes.
377 Must be 1, 2, 4 or 8 bytes.
378 @param[in] MaskValue The mask value of memory.
379 @param[in] TestValue The test value of memory.
380 @param[in] Timeout The time out value for wait memory set, uses 1
381 microsecond as a unit.
382
383 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
384 range.
385 @retval EFI_SUCCESS The MMIO register has expected value.
386 @retval Others The MMIO operation fails.
387
388 **/
389 EFI_STATUS
390 EFIAPI
391 SdMmcHcWaitMmioSet (
392 IN EFI_PCI_IO_PROTOCOL *PciIo,
393 IN UINT8 BarIndex,
394 IN UINT32 Offset,
395 IN UINT8 Count,
396 IN UINT64 MaskValue,
397 IN UINT64 TestValue,
398 IN UINT64 Timeout
399 )
400 {
401 EFI_STATUS Status;
402 BOOLEAN InfiniteWait;
403
404 if (Timeout == 0) {
405 InfiniteWait = TRUE;
406 } else {
407 InfiniteWait = FALSE;
408 }
409
410 while (InfiniteWait || (Timeout > 0)) {
411 Status = SdMmcHcCheckMmioSet (
412 PciIo,
413 BarIndex,
414 Offset,
415 Count,
416 MaskValue,
417 TestValue
418 );
419 if (Status != EFI_NOT_READY) {
420 return Status;
421 }
422
423 //
424 // Stall for 1 microsecond.
425 //
426 gBS->Stall (1);
427
428 Timeout--;
429 }
430
431 return EFI_TIMEOUT;
432 }
433
434 /**
435 Get the controller version information from the specified slot.
436
437 @param[in] PciIo The PCI IO protocol instance.
438 @param[in] Slot The slot number of the SD card to send the command to.
439 @param[out] Version The buffer to store the version information.
440
441 @retval EFI_SUCCESS The operation executes successfully.
442 @retval Others The operation fails.
443
444 **/
445 EFI_STATUS
446 SdMmcHcGetControllerVersion (
447 IN EFI_PCI_IO_PROTOCOL *PciIo,
448 IN UINT8 Slot,
449 OUT UINT16 *Version
450 )
451 {
452 EFI_STATUS Status;
453
454 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);
455 if (EFI_ERROR (Status)) {
456 return Status;
457 }
458
459 *Version &= 0xFF;
460
461 return EFI_SUCCESS;
462 }
463
464 /**
465 Software reset the specified SD/MMC host controller and enable all interrupts.
466
467 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
468 @param[in] Slot The slot number of the SD card to send the command to.
469
470 @retval EFI_SUCCESS The software reset executes successfully.
471 @retval Others The software reset fails.
472
473 **/
474 EFI_STATUS
475 SdMmcHcReset (
476 IN SD_MMC_HC_PRIVATE_DATA *Private,
477 IN UINT8 Slot
478 )
479 {
480 EFI_STATUS Status;
481 UINT8 SwReset;
482 EFI_PCI_IO_PROTOCOL *PciIo;
483
484 //
485 // Notify the SD/MMC override protocol that we are about to reset
486 // the SD/MMC host controller.
487 //
488 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
489 Status = mOverride->NotifyPhase (
490 Private->ControllerHandle,
491 Slot,
492 EdkiiSdMmcResetPre,
493 NULL);
494 if (EFI_ERROR (Status)) {
495 DEBUG ((DEBUG_WARN,
496 "%a: SD/MMC pre reset notifier callback failed - %r\n",
497 __FUNCTION__, Status));
498 return Status;
499 }
500 }
501
502 PciIo = Private->PciIo;
503 SwReset = BIT0;
504 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
505
506 if (EFI_ERROR (Status)) {
507 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
508 return Status;
509 }
510
511 Status = SdMmcHcWaitMmioSet (
512 PciIo,
513 Slot,
514 SD_MMC_HC_SW_RST,
515 sizeof (SwReset),
516 BIT0,
517 0x00,
518 SD_MMC_HC_GENERIC_TIMEOUT
519 );
520 if (EFI_ERROR (Status)) {
521 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
522 return Status;
523 }
524
525 //
526 // Enable all interrupt after reset all.
527 //
528 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
529 if (EFI_ERROR (Status)) {
530 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
531 Status));
532 return Status;
533 }
534
535 //
536 // Notify the SD/MMC override protocol that we have just reset
537 // the SD/MMC host controller.
538 //
539 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
540 Status = mOverride->NotifyPhase (
541 Private->ControllerHandle,
542 Slot,
543 EdkiiSdMmcResetPost,
544 NULL);
545 if (EFI_ERROR (Status)) {
546 DEBUG ((DEBUG_WARN,
547 "%a: SD/MMC post reset notifier callback failed - %r\n",
548 __FUNCTION__, Status));
549 }
550 }
551
552 return Status;
553 }
554
555 /**
556 Set all interrupt status bits in Normal and Error Interrupt Status Enable
557 register.
558
559 @param[in] PciIo The PCI IO protocol instance.
560 @param[in] Slot The slot number of the SD card to send the command to.
561
562 @retval EFI_SUCCESS The operation executes successfully.
563 @retval Others The operation fails.
564
565 **/
566 EFI_STATUS
567 SdMmcHcEnableInterrupt (
568 IN EFI_PCI_IO_PROTOCOL *PciIo,
569 IN UINT8 Slot
570 )
571 {
572 EFI_STATUS Status;
573 UINT16 IntStatus;
574
575 //
576 // Enable all bits in Error Interrupt Status Enable Register
577 //
578 IntStatus = 0xFFFF;
579 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
580 if (EFI_ERROR (Status)) {
581 return Status;
582 }
583 //
584 // Enable all bits in Normal Interrupt Status Enable Register
585 //
586 IntStatus = 0xFFFF;
587 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
588
589 return Status;
590 }
591
592 /**
593 Get the capability data from the specified slot.
594
595 @param[in] PciIo The PCI IO protocol instance.
596 @param[in] Slot The slot number of the SD card to send the command to.
597 @param[out] Capability The buffer to store the capability data.
598
599 @retval EFI_SUCCESS The operation executes successfully.
600 @retval Others The operation fails.
601
602 **/
603 EFI_STATUS
604 SdMmcHcGetCapability (
605 IN EFI_PCI_IO_PROTOCOL *PciIo,
606 IN UINT8 Slot,
607 OUT SD_MMC_HC_SLOT_CAP *Capability
608 )
609 {
610 EFI_STATUS Status;
611 UINT64 Cap;
612
613 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
614 if (EFI_ERROR (Status)) {
615 return Status;
616 }
617
618 CopyMem (Capability, &Cap, sizeof (Cap));
619
620 return EFI_SUCCESS;
621 }
622
623 /**
624 Get the maximum current capability data from the specified slot.
625
626 @param[in] PciIo The PCI IO protocol instance.
627 @param[in] Slot The slot number of the SD card to send the command to.
628 @param[out] MaxCurrent The buffer to store the maximum current capability data.
629
630 @retval EFI_SUCCESS The operation executes successfully.
631 @retval Others The operation fails.
632
633 **/
634 EFI_STATUS
635 SdMmcHcGetMaxCurrent (
636 IN EFI_PCI_IO_PROTOCOL *PciIo,
637 IN UINT8 Slot,
638 OUT UINT64 *MaxCurrent
639 )
640 {
641 EFI_STATUS Status;
642
643 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
644
645 return Status;
646 }
647
648 /**
649 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
650 slot.
651
652 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
653
654 @param[in] PciIo The PCI IO protocol instance.
655 @param[in] Slot The slot number of the SD card to send the command to.
656 @param[out] MediaPresent The pointer to the media present boolean value.
657
658 @retval EFI_SUCCESS There is no media change happened.
659 @retval EFI_MEDIA_CHANGED There is media change happened.
660 @retval Others The detection fails.
661
662 **/
663 EFI_STATUS
664 SdMmcHcCardDetect (
665 IN EFI_PCI_IO_PROTOCOL *PciIo,
666 IN UINT8 Slot,
667 OUT BOOLEAN *MediaPresent
668 )
669 {
670 EFI_STATUS Status;
671 UINT16 Data;
672 UINT32 PresentState;
673
674 //
675 // Check Present State Register to see if there is a card presented.
676 //
677 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
678 if (EFI_ERROR (Status)) {
679 return Status;
680 }
681
682 if ((PresentState & BIT16) != 0) {
683 *MediaPresent = TRUE;
684 } else {
685 *MediaPresent = FALSE;
686 }
687
688 //
689 // Check Normal Interrupt Status Register
690 //
691 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
692 if (EFI_ERROR (Status)) {
693 return Status;
694 }
695
696 if ((Data & (BIT6 | BIT7)) != 0) {
697 //
698 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
699 //
700 Data &= BIT6 | BIT7;
701 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
702 if (EFI_ERROR (Status)) {
703 return Status;
704 }
705
706 return EFI_MEDIA_CHANGED;
707 }
708
709 return EFI_SUCCESS;
710 }
711
712 /**
713 Stop SD/MMC card clock.
714
715 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
716
717 @param[in] PciIo The PCI IO protocol instance.
718 @param[in] Slot The slot number of the SD card to send the command to.
719
720 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
721 @retval Others Fail to stop SD/MMC clock.
722
723 **/
724 EFI_STATUS
725 SdMmcHcStopClock (
726 IN EFI_PCI_IO_PROTOCOL *PciIo,
727 IN UINT8 Slot
728 )
729 {
730 EFI_STATUS Status;
731 UINT32 PresentState;
732 UINT16 ClockCtrl;
733
734 //
735 // Ensure no SD transactions are occurring on the SD Bus by
736 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
737 // in the Present State register to be 0.
738 //
739 Status = SdMmcHcWaitMmioSet (
740 PciIo,
741 Slot,
742 SD_MMC_HC_PRESENT_STATE,
743 sizeof (PresentState),
744 BIT0 | BIT1,
745 0,
746 SD_MMC_HC_GENERIC_TIMEOUT
747 );
748 if (EFI_ERROR (Status)) {
749 return Status;
750 }
751
752 //
753 // Set SD Clock Enable in the Clock Control register to 0
754 //
755 ClockCtrl = (UINT16)~BIT2;
756 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
757
758 return Status;
759 }
760
761 /**
762 Start the SD clock.
763
764 @param[in] PciIo The PCI IO protocol instance.
765 @param[in] Slot The slot number.
766
767 @retval EFI_SUCCESS Succeeded to start the SD clock.
768 @retval Others Failed to start the SD clock.
769 **/
770 EFI_STATUS
771 SdMmcHcStartSdClock (
772 IN EFI_PCI_IO_PROTOCOL *PciIo,
773 IN UINT8 Slot
774 )
775 {
776 UINT16 ClockCtrl;
777
778 //
779 // Set SD Clock Enable in the Clock Control register to 1
780 //
781 ClockCtrl = BIT2;
782 return SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
783 }
784
785 /**
786 SD/MMC card clock supply.
787
788 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
789
790 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
791 @param[in] Slot The slot number of the SD card to send the command to.
792 @param[in] BusTiming BusTiming at which the frequency change is done.
793 @param[in] FirstTimeSetup Flag to indicate whether the clock is being setup for the first time.
794 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
795
796 @retval EFI_SUCCESS The clock is supplied successfully.
797 @retval Others The clock isn't supplied successfully.
798
799 **/
800 EFI_STATUS
801 SdMmcHcClockSupply (
802 IN SD_MMC_HC_PRIVATE_DATA *Private,
803 IN UINT8 Slot,
804 IN SD_MMC_BUS_MODE BusTiming,
805 IN BOOLEAN FirstTimeSetup,
806 IN UINT64 ClockFreq
807 )
808 {
809 EFI_STATUS Status;
810 UINT32 SettingFreq;
811 UINT32 Divisor;
812 UINT32 Remainder;
813 UINT16 ClockCtrl;
814 UINT32 BaseClkFreq;
815 UINT16 ControllerVer;
816 EFI_PCI_IO_PROTOCOL *PciIo;
817
818 PciIo = Private->PciIo;
819 BaseClkFreq = Private->BaseClkFreq[Slot];
820 ControllerVer = Private->ControllerVersion[Slot];
821
822 if (BaseClkFreq == 0 || ClockFreq == 0) {
823 return EFI_INVALID_PARAMETER;
824 }
825
826 if (ClockFreq > (BaseClkFreq * 1000)) {
827 ClockFreq = BaseClkFreq * 1000;
828 }
829
830 //
831 // Calculate the divisor of base frequency.
832 //
833 Divisor = 0;
834 SettingFreq = BaseClkFreq * 1000;
835 while (ClockFreq < SettingFreq) {
836 Divisor++;
837
838 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
839 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
840 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
841 break;
842 }
843 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
844 SettingFreq ++;
845 }
846 }
847
848 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
849
850 //
851 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
852 //
853 if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&
854 (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {
855 ASSERT (Divisor <= 0x3FF);
856 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
857 } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||
858 (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {
859 //
860 // Only the most significant bit can be used as divisor.
861 //
862 if (((Divisor - 1) & Divisor) != 0) {
863 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
864 }
865 ASSERT (Divisor <= 0x80);
866 ClockCtrl = (Divisor & 0xFF) << 8;
867 } else {
868 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
869 return EFI_UNSUPPORTED;
870 }
871
872 //
873 // Stop bus clock at first
874 //
875 Status = SdMmcHcStopClock (PciIo, Slot);
876 if (EFI_ERROR (Status)) {
877 return Status;
878 }
879
880 //
881 // Supply clock frequency with specified divisor
882 //
883 ClockCtrl |= BIT0;
884 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
885 if (EFI_ERROR (Status)) {
886 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
887 return Status;
888 }
889
890 //
891 // Wait Internal Clock Stable in the Clock Control register to be 1
892 //
893 Status = SdMmcHcWaitMmioSet (
894 PciIo,
895 Slot,
896 SD_MMC_HC_CLOCK_CTRL,
897 sizeof (ClockCtrl),
898 BIT1,
899 BIT1,
900 SD_MMC_HC_GENERIC_TIMEOUT
901 );
902 if (EFI_ERROR (Status)) {
903 return Status;
904 }
905
906 Status = SdMmcHcStartSdClock (PciIo, Slot);
907 if (EFI_ERROR (Status)) {
908 return Status;
909 }
910
911 //
912 // We don't notify the platform on first time setup to avoid changing
913 // legacy behavior. During first time setup we also don't know what type
914 // of the card slot it is and which enum value of BusTiming applies.
915 //
916 if (!FirstTimeSetup && mOverride != NULL && mOverride->NotifyPhase != NULL) {
917 Status = mOverride->NotifyPhase (
918 Private->ControllerHandle,
919 Slot,
920 EdkiiSdMmcSwitchClockFreqPost,
921 &BusTiming
922 );
923 if (EFI_ERROR (Status)) {
924 DEBUG ((
925 DEBUG_ERROR,
926 "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
927 __FUNCTION__,
928 Status
929 ));
930 return Status;
931 }
932 }
933
934 Private->Slot[Slot].CurrentFreq = ClockFreq;
935
936 return Status;
937 }
938
939 /**
940 SD/MMC bus power control.
941
942 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
943
944 @param[in] PciIo The PCI IO protocol instance.
945 @param[in] Slot The slot number of the SD card to send the command to.
946 @param[in] PowerCtrl The value setting to the power control register.
947
948 @retval TRUE There is a SD/MMC card attached.
949 @retval FALSE There is no a SD/MMC card attached.
950
951 **/
952 EFI_STATUS
953 SdMmcHcPowerControl (
954 IN EFI_PCI_IO_PROTOCOL *PciIo,
955 IN UINT8 Slot,
956 IN UINT8 PowerCtrl
957 )
958 {
959 EFI_STATUS Status;
960
961 //
962 // Clr SD Bus Power
963 //
964 PowerCtrl &= (UINT8)~BIT0;
965 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
966 if (EFI_ERROR (Status)) {
967 return Status;
968 }
969
970 //
971 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
972 //
973 PowerCtrl |= BIT0;
974 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
975
976 return Status;
977 }
978
979 /**
980 Set the SD/MMC bus width.
981
982 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
983
984 @param[in] PciIo The PCI IO protocol instance.
985 @param[in] Slot The slot number of the SD card to send the command to.
986 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
987
988 @retval EFI_SUCCESS The bus width is set successfully.
989 @retval Others The bus width isn't set successfully.
990
991 **/
992 EFI_STATUS
993 SdMmcHcSetBusWidth (
994 IN EFI_PCI_IO_PROTOCOL *PciIo,
995 IN UINT8 Slot,
996 IN UINT16 BusWidth
997 )
998 {
999 EFI_STATUS Status;
1000 UINT8 HostCtrl1;
1001
1002 if (BusWidth == 1) {
1003 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
1004 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1005 } else if (BusWidth == 4) {
1006 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
1007 if (EFI_ERROR (Status)) {
1008 return Status;
1009 }
1010 HostCtrl1 |= BIT1;
1011 HostCtrl1 &= (UINT8)~BIT5;
1012 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
1013 } else if (BusWidth == 8) {
1014 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
1015 if (EFI_ERROR (Status)) {
1016 return Status;
1017 }
1018 HostCtrl1 &= (UINT8)~BIT1;
1019 HostCtrl1 |= BIT5;
1020 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
1021 } else {
1022 ASSERT (FALSE);
1023 return EFI_INVALID_PARAMETER;
1024 }
1025
1026 return Status;
1027 }
1028
1029 /**
1030 Configure V4 controller enhancements at initialization.
1031
1032 @param[in] PciIo The PCI IO protocol instance.
1033 @param[in] Slot The slot number of the SD card to send the command to.
1034 @param[in] Capability The capability of the slot.
1035 @param[in] ControllerVer The version of host controller.
1036
1037 @retval EFI_SUCCESS The clock is supplied successfully.
1038
1039 **/
1040 EFI_STATUS
1041 SdMmcHcInitV4Enhancements (
1042 IN EFI_PCI_IO_PROTOCOL *PciIo,
1043 IN UINT8 Slot,
1044 IN SD_MMC_HC_SLOT_CAP Capability,
1045 IN UINT16 ControllerVer
1046 )
1047 {
1048 EFI_STATUS Status;
1049 UINT16 HostCtrl2;
1050
1051 //
1052 // Check if controller version V4 or higher
1053 //
1054 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
1055 HostCtrl2 = SD_MMC_HC_V4_EN;
1056 //
1057 // Check if controller version V4.0
1058 //
1059 if (ControllerVer == SD_MMC_HC_CTRL_VER_400) {
1060 //
1061 // Check if 64bit support is available
1062 //
1063 if (Capability.SysBus64V3 != 0) {
1064 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1065 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1066 }
1067 }
1068 //
1069 // Check if controller version V4.10 or higher
1070 //
1071 else if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {
1072 //
1073 // Check if 64bit support is available
1074 //
1075 if (Capability.SysBus64V4 != 0) {
1076 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1077 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1078 }
1079 HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;
1080 DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));
1081 }
1082 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1083 if (EFI_ERROR (Status)) {
1084 return Status;
1085 }
1086 }
1087
1088 return EFI_SUCCESS;
1089 }
1090
1091 /**
1092 Supply SD/MMC card with maximum voltage at initialization.
1093
1094 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1095
1096 @param[in] PciIo The PCI IO protocol instance.
1097 @param[in] Slot The slot number of the SD card to send the command to.
1098 @param[in] Capability The capability of the slot.
1099
1100 @retval EFI_SUCCESS The voltage is supplied successfully.
1101 @retval Others The voltage isn't supplied successfully.
1102
1103 **/
1104 EFI_STATUS
1105 SdMmcHcInitPowerVoltage (
1106 IN EFI_PCI_IO_PROTOCOL *PciIo,
1107 IN UINT8 Slot,
1108 IN SD_MMC_HC_SLOT_CAP Capability
1109 )
1110 {
1111 EFI_STATUS Status;
1112 UINT8 MaxVoltage;
1113 UINT8 HostCtrl2;
1114
1115 //
1116 // Calculate supported maximum voltage according to SD Bus Voltage Select
1117 //
1118 if (Capability.Voltage33 != 0) {
1119 //
1120 // Support 3.3V
1121 //
1122 MaxVoltage = 0x0E;
1123 } else if (Capability.Voltage30 != 0) {
1124 //
1125 // Support 3.0V
1126 //
1127 MaxVoltage = 0x0C;
1128 } else if (Capability.Voltage18 != 0) {
1129 //
1130 // Support 1.8V
1131 //
1132 MaxVoltage = 0x0A;
1133 HostCtrl2 = BIT3;
1134 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1135 gBS->Stall (5000);
1136 if (EFI_ERROR (Status)) {
1137 return Status;
1138 }
1139 } else {
1140 ASSERT (FALSE);
1141 return EFI_DEVICE_ERROR;
1142 }
1143
1144 //
1145 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1146 //
1147 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1148
1149 return Status;
1150 }
1151
1152 /**
1153 Initialize the Timeout Control register with most conservative value at initialization.
1154
1155 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1156
1157 @param[in] PciIo The PCI IO protocol instance.
1158 @param[in] Slot The slot number of the SD card to send the command to.
1159
1160 @retval EFI_SUCCESS The timeout control register is configured successfully.
1161 @retval Others The timeout control register isn't configured successfully.
1162
1163 **/
1164 EFI_STATUS
1165 SdMmcHcInitTimeoutCtrl (
1166 IN EFI_PCI_IO_PROTOCOL *PciIo,
1167 IN UINT8 Slot
1168 )
1169 {
1170 EFI_STATUS Status;
1171 UINT8 Timeout;
1172
1173 Timeout = 0x0E;
1174 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1175
1176 return Status;
1177 }
1178
1179 /**
1180 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1181 at initialization.
1182
1183 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1184 @param[in] Slot The slot number of the SD card to send the command to.
1185
1186 @retval EFI_SUCCESS The host controller is initialized successfully.
1187 @retval Others The host controller isn't initialized successfully.
1188
1189 **/
1190 EFI_STATUS
1191 SdMmcHcInitHost (
1192 IN SD_MMC_HC_PRIVATE_DATA *Private,
1193 IN UINT8 Slot
1194 )
1195 {
1196 EFI_STATUS Status;
1197 EFI_PCI_IO_PROTOCOL *PciIo;
1198 SD_MMC_HC_SLOT_CAP Capability;
1199
1200 //
1201 // Notify the SD/MMC override protocol that we are about to initialize
1202 // the SD/MMC host controller.
1203 //
1204 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1205 Status = mOverride->NotifyPhase (
1206 Private->ControllerHandle,
1207 Slot,
1208 EdkiiSdMmcInitHostPre,
1209 NULL);
1210 if (EFI_ERROR (Status)) {
1211 DEBUG ((DEBUG_WARN,
1212 "%a: SD/MMC pre init notifier callback failed - %r\n",
1213 __FUNCTION__, Status));
1214 return Status;
1215 }
1216 }
1217
1218 PciIo = Private->PciIo;
1219 Capability = Private->Capability[Slot];
1220
1221 Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);
1222 if (EFI_ERROR (Status)) {
1223 return Status;
1224 }
1225
1226 //
1227 // Perform first time clock setup with 400 KHz frequency.
1228 // We send the 0 as the BusTiming value because at this time
1229 // we still do not know the slot type and which enum value will apply.
1230 // Since it is a first time setup SdMmcHcClockSupply won't notify
1231 // the platofrm driver anyway so it doesn't matter.
1232 //
1233 Status = SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400);
1234 if (EFI_ERROR (Status)) {
1235 return Status;
1236 }
1237
1238 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1239 if (EFI_ERROR (Status)) {
1240 return Status;
1241 }
1242
1243 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1244 if (EFI_ERROR (Status)) {
1245 return Status;
1246 }
1247
1248 //
1249 // Notify the SD/MMC override protocol that we are have just initialized
1250 // the SD/MMC host controller.
1251 //
1252 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1253 Status = mOverride->NotifyPhase (
1254 Private->ControllerHandle,
1255 Slot,
1256 EdkiiSdMmcInitHostPost,
1257 NULL);
1258 if (EFI_ERROR (Status)) {
1259 DEBUG ((DEBUG_WARN,
1260 "%a: SD/MMC post init notifier callback failed - %r\n",
1261 __FUNCTION__, Status));
1262 }
1263 }
1264 return Status;
1265 }
1266
1267 /**
1268 Set SD Host Controler control 2 registry according to selected speed.
1269
1270 @param[in] ControllerHandle The handle of the controller.
1271 @param[in] PciIo The PCI IO protocol instance.
1272 @param[in] Slot The slot number of the SD card to send the command to.
1273 @param[in] Timing The timing to select.
1274
1275 @retval EFI_SUCCESS The timing is set successfully.
1276 @retval Others The timing isn't set successfully.
1277 **/
1278 EFI_STATUS
1279 SdMmcHcUhsSignaling (
1280 IN EFI_HANDLE ControllerHandle,
1281 IN EFI_PCI_IO_PROTOCOL *PciIo,
1282 IN UINT8 Slot,
1283 IN SD_MMC_BUS_MODE Timing
1284 )
1285 {
1286 EFI_STATUS Status;
1287 UINT8 HostCtrl2;
1288
1289 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
1290 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1291 if (EFI_ERROR (Status)) {
1292 return Status;
1293 }
1294
1295 switch (Timing) {
1296 case SdMmcUhsSdr12:
1297 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1298 break;
1299 case SdMmcUhsSdr25:
1300 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1301 break;
1302 case SdMmcUhsSdr50:
1303 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1304 break;
1305 case SdMmcUhsSdr104:
1306 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1307 break;
1308 case SdMmcUhsDdr50:
1309 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1310 break;
1311 case SdMmcMmcLegacy:
1312 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1313 break;
1314 case SdMmcMmcHsSdr:
1315 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1316 break;
1317 case SdMmcMmcHsDdr:
1318 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1319 break;
1320 case SdMmcMmcHs200:
1321 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1322 break;
1323 case SdMmcMmcHs400:
1324 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1325 break;
1326 default:
1327 HostCtrl2 = 0;
1328 break;
1329 }
1330 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1331 if (EFI_ERROR (Status)) {
1332 return Status;
1333 }
1334
1335 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1336 Status = mOverride->NotifyPhase (
1337 ControllerHandle,
1338 Slot,
1339 EdkiiSdMmcUhsSignaling,
1340 &Timing
1341 );
1342 if (EFI_ERROR (Status)) {
1343 DEBUG ((
1344 DEBUG_ERROR,
1345 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1346 __FUNCTION__,
1347 Status
1348 ));
1349 return Status;
1350 }
1351 }
1352
1353 return EFI_SUCCESS;
1354 }
1355
1356 /**
1357 Set driver strength in host controller.
1358
1359 @param[in] PciIo The PCI IO protocol instance.
1360 @param[in] SlotIndex The slot index of the card.
1361 @param[in] DriverStrength DriverStrength to set in the controller.
1362
1363 @retval EFI_SUCCESS Driver strength programmed successfully.
1364 @retval Others Failed to set driver strength.
1365 **/
1366 EFI_STATUS
1367 SdMmcSetDriverStrength (
1368 IN EFI_PCI_IO_PROTOCOL *PciIo,
1369 IN UINT8 SlotIndex,
1370 IN SD_DRIVER_STRENGTH_TYPE DriverStrength
1371 )
1372 {
1373 EFI_STATUS Status;
1374 UINT16 HostCtrl2;
1375
1376 if (DriverStrength == SdDriverStrengthIgnore) {
1377 return EFI_SUCCESS;
1378 }
1379
1380 HostCtrl2 = (UINT16)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
1381 Status = SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1382 if (EFI_ERROR (Status)) {
1383 return Status;
1384 }
1385
1386 HostCtrl2 = (DriverStrength << 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
1387 return SdMmcHcOrMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1388 }
1389
1390 /**
1391 Turn on/off LED.
1392
1393 @param[in] PciIo The PCI IO protocol instance.
1394 @param[in] Slot The slot number of the SD card to send the command to.
1395 @param[in] On The boolean to turn on/off LED.
1396
1397 @retval EFI_SUCCESS The LED is turned on/off successfully.
1398 @retval Others The LED isn't turned on/off successfully.
1399
1400 **/
1401 EFI_STATUS
1402 SdMmcHcLedOnOff (
1403 IN EFI_PCI_IO_PROTOCOL *PciIo,
1404 IN UINT8 Slot,
1405 IN BOOLEAN On
1406 )
1407 {
1408 EFI_STATUS Status;
1409 UINT8 HostCtrl1;
1410
1411 if (On) {
1412 HostCtrl1 = BIT0;
1413 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1414 } else {
1415 HostCtrl1 = (UINT8)~BIT0;
1416 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1417 }
1418
1419 return Status;
1420 }
1421
1422 /**
1423 Build ADMA descriptor table for transfer.
1424
1425 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1426
1427 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1428 @param[in] ControllerVer The version of host controller.
1429
1430 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1431 @retval Others The ADMA descriptor table isn't created successfully.
1432
1433 **/
1434 EFI_STATUS
1435 BuildAdmaDescTable (
1436 IN SD_MMC_HC_TRB *Trb,
1437 IN UINT16 ControllerVer
1438 )
1439 {
1440 EFI_PHYSICAL_ADDRESS Data;
1441 UINT64 DataLen;
1442 UINT64 Entries;
1443 UINT32 Index;
1444 UINT64 Remaining;
1445 UINT64 Address;
1446 UINTN TableSize;
1447 EFI_PCI_IO_PROTOCOL *PciIo;
1448 EFI_STATUS Status;
1449 UINTN Bytes;
1450 UINT32 AdmaMaxDataPerLine;
1451 UINT32 DescSize;
1452 VOID *AdmaDesc;
1453
1454 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;
1455 DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);
1456 AdmaDesc = NULL;
1457
1458 Data = Trb->DataPhy;
1459 DataLen = Trb->DataLen;
1460 PciIo = Trb->Private->PciIo;
1461
1462 //
1463 // Check for valid ranges in 32bit ADMA Descriptor Table
1464 //
1465 if ((Trb->Mode == SdMmcAdma32bMode) &&
1466 ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {
1467 return EFI_INVALID_PARAMETER;
1468 }
1469 //
1470 // Check address field alignment
1471 //
1472 if (Trb->Mode != SdMmcAdma32bMode) {
1473 //
1474 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1475 //
1476 if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {
1477 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));
1478 }
1479 } else {
1480 //
1481 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1482 //
1483 if ((Data & (BIT0 | BIT1)) != 0) {
1484 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1485 }
1486 }
1487
1488 //
1489 // Configure 64b ADMA.
1490 //
1491 if (Trb->Mode == SdMmcAdma64bV3Mode) {
1492 DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);
1493 }else if (Trb->Mode == SdMmcAdma64bV4Mode) {
1494 DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);
1495 }
1496 //
1497 // Configure 26b data length.
1498 //
1499 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1500 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;
1501 }
1502
1503 Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
1504 TableSize = (UINTN)MultU64x32 (Entries, DescSize);
1505 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1506 Status = PciIo->AllocateBuffer (
1507 PciIo,
1508 AllocateAnyPages,
1509 EfiBootServicesData,
1510 EFI_SIZE_TO_PAGES (TableSize),
1511 (VOID **)&AdmaDesc,
1512 0
1513 );
1514 if (EFI_ERROR (Status)) {
1515 return EFI_OUT_OF_RESOURCES;
1516 }
1517 ZeroMem (AdmaDesc, TableSize);
1518 Bytes = TableSize;
1519 Status = PciIo->Map (
1520 PciIo,
1521 EfiPciIoOperationBusMasterCommonBuffer,
1522 AdmaDesc,
1523 &Bytes,
1524 &Trb->AdmaDescPhy,
1525 &Trb->AdmaMap
1526 );
1527
1528 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1529 //
1530 // Map error or unable to map the whole RFis buffer into a contiguous region.
1531 //
1532 PciIo->FreeBuffer (
1533 PciIo,
1534 EFI_SIZE_TO_PAGES (TableSize),
1535 AdmaDesc
1536 );
1537 return EFI_OUT_OF_RESOURCES;
1538 }
1539
1540 if ((Trb->Mode == SdMmcAdma32bMode) &&
1541 (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1542 //
1543 // The ADMA doesn't support 64bit addressing.
1544 //
1545 PciIo->Unmap (
1546 PciIo,
1547 Trb->AdmaMap
1548 );
1549 Trb->AdmaMap = NULL;
1550
1551 PciIo->FreeBuffer (
1552 PciIo,
1553 EFI_SIZE_TO_PAGES (TableSize),
1554 AdmaDesc
1555 );
1556 return EFI_DEVICE_ERROR;
1557 }
1558
1559 Remaining = DataLen;
1560 Address = Data;
1561 if (Trb->Mode == SdMmcAdma32bMode) {
1562 Trb->Adma32Desc = AdmaDesc;
1563 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1564 Trb->Adma64V3Desc = AdmaDesc;
1565 } else {
1566 Trb->Adma64V4Desc = AdmaDesc;
1567 }
1568
1569 for (Index = 0; Index < Entries; Index++) {
1570 if (Trb->Mode == SdMmcAdma32bMode) {
1571 if (Remaining <= AdmaMaxDataPerLine) {
1572 Trb->Adma32Desc[Index].Valid = 1;
1573 Trb->Adma32Desc[Index].Act = 2;
1574 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1575 Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1576 }
1577 Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1578 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1579 break;
1580 } else {
1581 Trb->Adma32Desc[Index].Valid = 1;
1582 Trb->Adma32Desc[Index].Act = 2;
1583 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1584 Trb->Adma32Desc[Index].UpperLength = 0;
1585 }
1586 Trb->Adma32Desc[Index].LowerLength = 0;
1587 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1588 }
1589 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1590 if (Remaining <= AdmaMaxDataPerLine) {
1591 Trb->Adma64V3Desc[Index].Valid = 1;
1592 Trb->Adma64V3Desc[Index].Act = 2;
1593 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1594 Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1595 }
1596 Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1597 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1598 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1599 break;
1600 } else {
1601 Trb->Adma64V3Desc[Index].Valid = 1;
1602 Trb->Adma64V3Desc[Index].Act = 2;
1603 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1604 Trb->Adma64V3Desc[Index].UpperLength = 0;
1605 }
1606 Trb->Adma64V3Desc[Index].LowerLength = 0;
1607 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1608 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1609 }
1610 } else {
1611 if (Remaining <= AdmaMaxDataPerLine) {
1612 Trb->Adma64V4Desc[Index].Valid = 1;
1613 Trb->Adma64V4Desc[Index].Act = 2;
1614 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1615 Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1616 }
1617 Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1618 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1619 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1620 break;
1621 } else {
1622 Trb->Adma64V4Desc[Index].Valid = 1;
1623 Trb->Adma64V4Desc[Index].Act = 2;
1624 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1625 Trb->Adma64V4Desc[Index].UpperLength = 0;
1626 }
1627 Trb->Adma64V4Desc[Index].LowerLength = 0;
1628 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1629 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1630 }
1631 }
1632
1633 Remaining -= AdmaMaxDataPerLine;
1634 Address += AdmaMaxDataPerLine;
1635 }
1636
1637 //
1638 // Set the last descriptor line as end of descriptor table
1639 //
1640 if (Trb->Mode == SdMmcAdma32bMode) {
1641 Trb->Adma32Desc[Index].End = 1;
1642 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1643 Trb->Adma64V3Desc[Index].End = 1;
1644 } else {
1645 Trb->Adma64V4Desc[Index].End = 1;
1646 }
1647 return EFI_SUCCESS;
1648 }
1649
1650 /**
1651 Prints the contents of the command packet to the debug port.
1652
1653 @param[in] DebugLevel Debug level at which the packet should be printed.
1654 @param[in] Packet Pointer to packet to print.
1655 **/
1656 VOID
1657 SdMmcPrintPacket (
1658 IN UINT32 DebugLevel,
1659 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet
1660 )
1661 {
1662 if (Packet == NULL) {
1663 return;
1664 }
1665
1666 DEBUG ((DebugLevel, "Printing EFI_SD_MMC_PASS_THRU_COMMAND_PACKET\n"));
1667 if (Packet->SdMmcCmdBlk != NULL) {
1668 DEBUG ((DebugLevel, "Command index: %d, argument: %X\n", Packet->SdMmcCmdBlk->CommandIndex, Packet->SdMmcCmdBlk->CommandArgument));
1669 DEBUG ((DebugLevel, "Command type: %d, response type: %d\n", Packet->SdMmcCmdBlk->CommandType, Packet->SdMmcCmdBlk->ResponseType));
1670 }
1671 if (Packet->SdMmcStatusBlk != NULL) {
1672 DEBUG ((DebugLevel, "Response 0: %X, 1: %X, 2: %X, 3: %X\n",
1673 Packet->SdMmcStatusBlk->Resp0,
1674 Packet->SdMmcStatusBlk->Resp1,
1675 Packet->SdMmcStatusBlk->Resp2,
1676 Packet->SdMmcStatusBlk->Resp3
1677 ));
1678 }
1679 DEBUG ((DebugLevel, "Timeout: %ld\n", Packet->Timeout));
1680 DEBUG ((DebugLevel, "InDataBuffer: %p\n", Packet->InDataBuffer));
1681 DEBUG ((DebugLevel, "OutDataBuffer: %p\n", Packet->OutDataBuffer));
1682 DEBUG ((DebugLevel, "InTransferLength: %d\n", Packet->InTransferLength));
1683 DEBUG ((DebugLevel, "OutTransferLength: %d\n", Packet->OutTransferLength));
1684 DEBUG ((DebugLevel, "TransactionStatus: %r\n", Packet->TransactionStatus));
1685 }
1686
1687 /**
1688 Prints the contents of the TRB to the debug port.
1689
1690 @param[in] DebugLevel Debug level at which the TRB should be printed.
1691 @param[in] Trb Pointer to the TRB structure.
1692 **/
1693 VOID
1694 SdMmcPrintTrb (
1695 IN UINT32 DebugLevel,
1696 IN SD_MMC_HC_TRB *Trb
1697 )
1698 {
1699 if (Trb == NULL) {
1700 return;
1701 }
1702
1703 DEBUG ((DebugLevel, "Printing SD_MMC_HC_TRB\n"));
1704 DEBUG ((DebugLevel, "Slot: %d\n", Trb->Slot));
1705 DEBUG ((DebugLevel, "BlockSize: %d\n", Trb->BlockSize));
1706 DEBUG ((DebugLevel, "Data: %p\n", Trb->Data));
1707 DEBUG ((DebugLevel, "DataLen: %d\n", Trb->DataLen));
1708 DEBUG ((DebugLevel, "Read: %d\n", Trb->Read));
1709 DEBUG ((DebugLevel, "DataPhy: %lX\n", Trb->DataPhy));
1710 DEBUG ((DebugLevel, "DataMap: %p\n", Trb->DataMap));
1711 DEBUG ((DebugLevel, "Mode: %d\n", Trb->Mode));
1712 DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode));
1713 DEBUG ((DebugLevel, "Event: %p\n", Trb->Event));
1714 DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));
1715 DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete));
1716 DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout));
1717 DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
1718 DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc));
1719 DEBUG ((DebugLevel, "Adma64V3Desc: %p\n", Trb->Adma64V3Desc));
1720 DEBUG ((DebugLevel, "Adma64V4Desc: %p\n", Trb->Adma64V4Desc));
1721 DEBUG ((DebugLevel, "AdmaMap: %p\n", Trb->AdmaMap));
1722 DEBUG ((DebugLevel, "AdmaPages: %X\n", Trb->AdmaPages));
1723
1724 SdMmcPrintPacket (DebugLevel, Trb->Packet);
1725 }
1726
1727 /**
1728 Sets up host memory to allow DMA transfer.
1729
1730 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1731 @param[in] Slot The slot number of the SD card to send the command to.
1732 @param[in] Packet A pointer to the SD command data structure.
1733
1734 @retval EFI_SUCCESS Memory has been mapped for DMA transfer.
1735 @retval Others Memory has not been mapped.
1736 **/
1737 EFI_STATUS
1738 SdMmcSetupMemoryForDmaTransfer (
1739 IN SD_MMC_HC_PRIVATE_DATA *Private,
1740 IN UINT8 Slot,
1741 IN SD_MMC_HC_TRB *Trb
1742 )
1743 {
1744 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1745 EFI_PCI_IO_PROTOCOL *PciIo;
1746 UINTN MapLength;
1747 EFI_STATUS Status;
1748
1749 if (Trb->Read) {
1750 Flag = EfiPciIoOperationBusMasterWrite;
1751 } else {
1752 Flag = EfiPciIoOperationBusMasterRead;
1753 }
1754
1755 PciIo = Private->PciIo;
1756 if (Trb->Data != NULL && Trb->DataLen != 0) {
1757 MapLength = Trb->DataLen;
1758 Status = PciIo->Map (
1759 PciIo,
1760 Flag,
1761 Trb->Data,
1762 &MapLength,
1763 &Trb->DataPhy,
1764 &Trb->DataMap
1765 );
1766 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1767 return EFI_BAD_BUFFER_SIZE;
1768 }
1769 }
1770
1771 if (Trb->Mode == SdMmcAdma32bMode ||
1772 Trb->Mode == SdMmcAdma64bV3Mode ||
1773 Trb->Mode == SdMmcAdma64bV4Mode) {
1774 Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
1775 if (EFI_ERROR (Status)) {
1776 return Status;
1777 }
1778 }
1779
1780 return EFI_SUCCESS;
1781 }
1782
1783 /**
1784 Create a new TRB for the SD/MMC cmd request.
1785
1786 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1787 @param[in] Slot The slot number of the SD card to send the command to.
1788 @param[in] Packet A pointer to the SD command data structure.
1789 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1790 not NULL, then nonblocking I/O is performed, and Event
1791 will be signaled when the Packet completes.
1792
1793 @return Created Trb or NULL.
1794
1795 **/
1796 SD_MMC_HC_TRB *
1797 SdMmcCreateTrb (
1798 IN SD_MMC_HC_PRIVATE_DATA *Private,
1799 IN UINT8 Slot,
1800 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1801 IN EFI_EVENT Event
1802 )
1803 {
1804 SD_MMC_HC_TRB *Trb;
1805 EFI_STATUS Status;
1806 EFI_TPL OldTpl;
1807
1808 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1809 if (Trb == NULL) {
1810 return NULL;
1811 }
1812
1813 Trb->Signature = SD_MMC_HC_TRB_SIG;
1814 Trb->Slot = Slot;
1815 Trb->BlockSize = 0x200;
1816 Trb->Packet = Packet;
1817 Trb->Event = Event;
1818 Trb->Started = FALSE;
1819 Trb->CommandComplete = FALSE;
1820 Trb->Timeout = Packet->Timeout;
1821 Trb->Retries = SD_MMC_TRB_RETRIES;
1822 Trb->Private = Private;
1823
1824 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1825 Trb->Data = Packet->InDataBuffer;
1826 Trb->DataLen = Packet->InTransferLength;
1827 Trb->Read = TRUE;
1828 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1829 Trb->Data = Packet->OutDataBuffer;
1830 Trb->DataLen = Packet->OutTransferLength;
1831 Trb->Read = FALSE;
1832 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1833 Trb->Data = NULL;
1834 Trb->DataLen = 0;
1835 } else {
1836 goto Error;
1837 }
1838
1839 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1840 Trb->BlockSize = (UINT16)Trb->DataLen;
1841 }
1842
1843 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1844 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1845 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1846 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1847 Trb->Mode = SdMmcPioMode;
1848 } else {
1849 if (Trb->DataLen == 0) {
1850 Trb->Mode = SdMmcNoData;
1851 } else if (Private->Capability[Slot].Adma2 != 0) {
1852 Trb->Mode = SdMmcAdma32bMode;
1853 Trb->AdmaLengthMode = SdMmcAdmaLen16b;
1854 if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&
1855 (Private->Capability[Slot].SysBus64V3 == 1)) {
1856 Trb->Mode = SdMmcAdma64bV3Mode;
1857 } else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&
1858 (Private->Capability[Slot].SysBus64V3 == 1)) ||
1859 ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&
1860 (Private->Capability[Slot].SysBus64V4 == 1))) {
1861 Trb->Mode = SdMmcAdma64bV4Mode;
1862 }
1863 if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {
1864 Trb->AdmaLengthMode = SdMmcAdmaLen26b;
1865 }
1866 Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);
1867 if (EFI_ERROR (Status)) {
1868 goto Error;
1869 }
1870 } else if (Private->Capability[Slot].Sdma != 0) {
1871 Trb->Mode = SdMmcSdmaMode;
1872 Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);
1873 if (EFI_ERROR (Status)) {
1874 goto Error;
1875 }
1876 } else {
1877 Trb->Mode = SdMmcPioMode;
1878 }
1879 }
1880
1881 if (Event != NULL) {
1882 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1883 InsertTailList (&Private->Queue, &Trb->TrbList);
1884 gBS->RestoreTPL (OldTpl);
1885 }
1886
1887 return Trb;
1888
1889 Error:
1890 SdMmcFreeTrb (Trb);
1891 return NULL;
1892 }
1893
1894 /**
1895 Free the resource used by the TRB.
1896
1897 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1898
1899 **/
1900 VOID
1901 SdMmcFreeTrb (
1902 IN SD_MMC_HC_TRB *Trb
1903 )
1904 {
1905 EFI_PCI_IO_PROTOCOL *PciIo;
1906
1907 PciIo = Trb->Private->PciIo;
1908
1909 if (Trb->AdmaMap != NULL) {
1910 PciIo->Unmap (
1911 PciIo,
1912 Trb->AdmaMap
1913 );
1914 }
1915 if (Trb->Adma32Desc != NULL) {
1916 PciIo->FreeBuffer (
1917 PciIo,
1918 Trb->AdmaPages,
1919 Trb->Adma32Desc
1920 );
1921 }
1922 if (Trb->Adma64V3Desc != NULL) {
1923 PciIo->FreeBuffer (
1924 PciIo,
1925 Trb->AdmaPages,
1926 Trb->Adma64V3Desc
1927 );
1928 }
1929 if (Trb->Adma64V4Desc != NULL) {
1930 PciIo->FreeBuffer (
1931 PciIo,
1932 Trb->AdmaPages,
1933 Trb->Adma64V4Desc
1934 );
1935 }
1936 if (Trb->DataMap != NULL) {
1937 PciIo->Unmap (
1938 PciIo,
1939 Trb->DataMap
1940 );
1941 }
1942 FreePool (Trb);
1943 return;
1944 }
1945
1946 /**
1947 Check if the env is ready for execute specified TRB.
1948
1949 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1950 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1951
1952 @retval EFI_SUCCESS The env is ready for TRB execution.
1953 @retval EFI_NOT_READY The env is not ready for TRB execution.
1954 @retval Others Some erros happen.
1955
1956 **/
1957 EFI_STATUS
1958 SdMmcCheckTrbEnv (
1959 IN SD_MMC_HC_PRIVATE_DATA *Private,
1960 IN SD_MMC_HC_TRB *Trb
1961 )
1962 {
1963 EFI_STATUS Status;
1964 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1965 EFI_PCI_IO_PROTOCOL *PciIo;
1966 UINT32 PresentState;
1967
1968 Packet = Trb->Packet;
1969
1970 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1971 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1972 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1973 //
1974 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1975 // the Present State register to be 0
1976 //
1977 PresentState = BIT0 | BIT1;
1978 } else {
1979 //
1980 // Wait Command Inhibit (CMD) in the Present State register
1981 // to be 0
1982 //
1983 PresentState = BIT0;
1984 }
1985
1986 PciIo = Private->PciIo;
1987 Status = SdMmcHcCheckMmioSet (
1988 PciIo,
1989 Trb->Slot,
1990 SD_MMC_HC_PRESENT_STATE,
1991 sizeof (PresentState),
1992 PresentState,
1993 0
1994 );
1995
1996 return Status;
1997 }
1998
1999 /**
2000 Wait for the env to be ready for execute specified TRB.
2001
2002 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2003 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2004
2005 @retval EFI_SUCCESS The env is ready for TRB execution.
2006 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
2007 @retval Others Some erros happen.
2008
2009 **/
2010 EFI_STATUS
2011 SdMmcWaitTrbEnv (
2012 IN SD_MMC_HC_PRIVATE_DATA *Private,
2013 IN SD_MMC_HC_TRB *Trb
2014 )
2015 {
2016 EFI_STATUS Status;
2017 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2018 UINT64 Timeout;
2019 BOOLEAN InfiniteWait;
2020
2021 //
2022 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2023 //
2024 Packet = Trb->Packet;
2025 Timeout = Packet->Timeout;
2026 if (Timeout == 0) {
2027 InfiniteWait = TRUE;
2028 } else {
2029 InfiniteWait = FALSE;
2030 }
2031
2032 while (InfiniteWait || (Timeout > 0)) {
2033 //
2034 // Check Trb execution result by reading Normal Interrupt Status register.
2035 //
2036 Status = SdMmcCheckTrbEnv (Private, Trb);
2037 if (Status != EFI_NOT_READY) {
2038 return Status;
2039 }
2040 //
2041 // Stall for 1 microsecond.
2042 //
2043 gBS->Stall (1);
2044
2045 Timeout--;
2046 }
2047
2048 return EFI_TIMEOUT;
2049 }
2050
2051 /**
2052 Execute the specified TRB.
2053
2054 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2055 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2056
2057 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
2058 @retval Others Some erros happen when sending this request to the host controller.
2059
2060 **/
2061 EFI_STATUS
2062 SdMmcExecTrb (
2063 IN SD_MMC_HC_PRIVATE_DATA *Private,
2064 IN SD_MMC_HC_TRB *Trb
2065 )
2066 {
2067 EFI_STATUS Status;
2068 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2069 EFI_PCI_IO_PROTOCOL *PciIo;
2070 UINT16 Cmd;
2071 UINT16 IntStatus;
2072 UINT32 Argument;
2073 UINT32 BlkCount;
2074 UINT16 BlkSize;
2075 UINT16 TransMode;
2076 UINT8 HostCtrl1;
2077 UINT64 SdmaAddr;
2078 UINT64 AdmaAddr;
2079 BOOLEAN AddressingMode64;
2080
2081 AddressingMode64 = FALSE;
2082
2083 Packet = Trb->Packet;
2084 PciIo = Trb->Private->PciIo;
2085 //
2086 // Clear all bits in Error Interrupt Status Register
2087 //
2088 IntStatus = 0xFFFF;
2089 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2090 if (EFI_ERROR (Status)) {
2091 return Status;
2092 }
2093 //
2094 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
2095 //
2096 IntStatus = 0xFF3F;
2097 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2098 if (EFI_ERROR (Status)) {
2099 return Status;
2100 }
2101
2102 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2103 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
2104 SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_64_ADDR_EN);
2105 if (!EFI_ERROR (Status)) {
2106 AddressingMode64 = TRUE;
2107 }
2108 }
2109
2110 //
2111 // Set Host Control 1 register DMA Select field
2112 //
2113 if ((Trb->Mode == SdMmcAdma32bMode) ||
2114 (Trb->Mode == SdMmcAdma64bV4Mode)) {
2115 HostCtrl1 = BIT4;
2116 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
2117 if (EFI_ERROR (Status)) {
2118 return Status;
2119 }
2120 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
2121 HostCtrl1 = BIT4|BIT3;
2122 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
2123 if (EFI_ERROR (Status)) {
2124 return Status;
2125 }
2126 }
2127
2128 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
2129
2130 if (Trb->Mode == SdMmcSdmaMode) {
2131 if ((!AddressingMode64) &&
2132 ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {
2133 return EFI_INVALID_PARAMETER;
2134 }
2135
2136 SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;
2137
2138 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2139 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);
2140 } else {
2141 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);
2142 }
2143
2144 if (EFI_ERROR (Status)) {
2145 return Status;
2146 }
2147 } else if ((Trb->Mode == SdMmcAdma32bMode) ||
2148 (Trb->Mode == SdMmcAdma64bV3Mode) ||
2149 (Trb->Mode == SdMmcAdma64bV4Mode)) {
2150 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
2151 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
2152 if (EFI_ERROR (Status)) {
2153 return Status;
2154 }
2155 }
2156
2157 BlkSize = Trb->BlockSize;
2158 if (Trb->Mode == SdMmcSdmaMode) {
2159 //
2160 // Set SDMA boundary to be 512K bytes.
2161 //
2162 BlkSize |= 0x7000;
2163 }
2164
2165 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
2166 if (EFI_ERROR (Status)) {
2167 return Status;
2168 }
2169
2170 BlkCount = 0;
2171 if (Trb->Mode != SdMmcNoData) {
2172 //
2173 // Calcuate Block Count.
2174 //
2175 BlkCount = (Trb->DataLen / Trb->BlockSize);
2176 }
2177 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {
2178 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);
2179 } else {
2180 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);
2181 }
2182 if (EFI_ERROR (Status)) {
2183 return Status;
2184 }
2185
2186 Argument = Packet->SdMmcCmdBlk->CommandArgument;
2187 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
2188 if (EFI_ERROR (Status)) {
2189 return Status;
2190 }
2191
2192 TransMode = 0;
2193 if (Trb->Mode != SdMmcNoData) {
2194 if (Trb->Mode != SdMmcPioMode) {
2195 TransMode |= BIT0;
2196 }
2197 if (Trb->Read) {
2198 TransMode |= BIT4;
2199 }
2200 if (BlkCount > 1) {
2201 TransMode |= BIT5 | BIT1;
2202 }
2203 //
2204 // Only SD memory card needs to use AUTO CMD12 feature.
2205 //
2206 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
2207 if (BlkCount > 1) {
2208 TransMode |= BIT2;
2209 }
2210 }
2211 }
2212
2213 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
2214 if (EFI_ERROR (Status)) {
2215 return Status;
2216 }
2217
2218 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
2219 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
2220 Cmd |= BIT5;
2221 }
2222 //
2223 // Convert ResponseType to value
2224 //
2225 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2226 switch (Packet->SdMmcCmdBlk->ResponseType) {
2227 case SdMmcResponseTypeR1:
2228 case SdMmcResponseTypeR5:
2229 case SdMmcResponseTypeR6:
2230 case SdMmcResponseTypeR7:
2231 Cmd |= (BIT1 | BIT3 | BIT4);
2232 break;
2233 case SdMmcResponseTypeR2:
2234 Cmd |= (BIT0 | BIT3);
2235 break;
2236 case SdMmcResponseTypeR3:
2237 case SdMmcResponseTypeR4:
2238 Cmd |= BIT1;
2239 break;
2240 case SdMmcResponseTypeR1b:
2241 case SdMmcResponseTypeR5b:
2242 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
2243 break;
2244 default:
2245 ASSERT (FALSE);
2246 break;
2247 }
2248 }
2249 //
2250 // Execute cmd
2251 //
2252 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
2253 return Status;
2254 }
2255
2256 /**
2257 Performs SW reset based on passed error status mask.
2258
2259 @param[in] Private Pointer to driver private data.
2260 @param[in] Slot Index of the slot to reset.
2261 @param[in] ErrIntStatus Error interrupt status mask.
2262
2263 @retval EFI_SUCCESS Software reset performed successfully.
2264 @retval Other Software reset failed.
2265 **/
2266 EFI_STATUS
2267 SdMmcSoftwareReset (
2268 IN SD_MMC_HC_PRIVATE_DATA *Private,
2269 IN UINT8 Slot,
2270 IN UINT16 ErrIntStatus
2271 )
2272 {
2273 UINT8 SwReset;
2274 EFI_STATUS Status;
2275
2276 SwReset = 0;
2277 if ((ErrIntStatus & 0x0F) != 0) {
2278 SwReset |= BIT1;
2279 }
2280 if ((ErrIntStatus & 0x70) != 0) {
2281 SwReset |= BIT2;
2282 }
2283
2284 Status = SdMmcHcRwMmio (
2285 Private->PciIo,
2286 Slot,
2287 SD_MMC_HC_SW_RST,
2288 FALSE,
2289 sizeof (SwReset),
2290 &SwReset
2291 );
2292 if (EFI_ERROR (Status)) {
2293 return Status;
2294 }
2295
2296 Status = SdMmcHcWaitMmioSet (
2297 Private->PciIo,
2298 Slot,
2299 SD_MMC_HC_SW_RST,
2300 sizeof (SwReset),
2301 0xFF,
2302 0,
2303 SD_MMC_HC_GENERIC_TIMEOUT
2304 );
2305 if (EFI_ERROR (Status)) {
2306 return Status;
2307 }
2308
2309 return EFI_SUCCESS;
2310 }
2311
2312 /**
2313 Checks the error status in error status register
2314 and issues appropriate software reset as described in
2315 SD specification section 3.10.
2316
2317 @param[in] Private Pointer to driver private data.
2318 @param[in] Slot Index of the slot for device.
2319 @param[in] IntStatus Normal interrupt status mask.
2320
2321 @retval EFI_CRC_ERROR CRC error happened during CMD execution.
2322 @retval EFI_SUCCESS No error reported.
2323 @retval Others Some other error happened.
2324
2325 **/
2326 EFI_STATUS
2327 SdMmcCheckAndRecoverErrors (
2328 IN SD_MMC_HC_PRIVATE_DATA *Private,
2329 IN UINT8 Slot,
2330 IN UINT16 IntStatus
2331 )
2332 {
2333 UINT16 ErrIntStatus;
2334 EFI_STATUS Status;
2335 EFI_STATUS ErrorStatus;
2336
2337 if ((IntStatus & BIT15) == 0) {
2338 return EFI_SUCCESS;
2339 }
2340
2341 Status = SdMmcHcRwMmio (
2342 Private->PciIo,
2343 Slot,
2344 SD_MMC_HC_ERR_INT_STS,
2345 TRUE,
2346 sizeof (ErrIntStatus),
2347 &ErrIntStatus
2348 );
2349 if (EFI_ERROR (Status)) {
2350 return Status;
2351 }
2352
2353 DEBUG ((DEBUG_ERROR, "Error reported by SDHCI\n"));
2354 DEBUG ((DEBUG_ERROR, "Interrupt status = %X\n", IntStatus));
2355 DEBUG ((DEBUG_ERROR, "Error interrupt status = %X\n", ErrIntStatus));
2356
2357 //
2358 // If the data timeout error is reported
2359 // but data transfer is signaled as completed we
2360 // have to ignore data timeout. We also assume that no
2361 // other error is present on the link since data transfer
2362 // completed successfully. Error interrupt status
2363 // register is going to be reset when the next command
2364 // is started.
2365 //
2366 if (((ErrIntStatus & BIT4) != 0) && ((IntStatus & BIT1) != 0)) {
2367 return EFI_SUCCESS;
2368 }
2369
2370 //
2371 // We treat both CMD and DAT CRC errors and
2372 // end bits errors as EFI_CRC_ERROR. This will
2373 // let higher layer know that the error possibly
2374 // happened due to random bus condition and the
2375 // command can be retried.
2376 //
2377 if ((ErrIntStatus & (BIT1 | BIT2 | BIT5 | BIT6)) != 0) {
2378 ErrorStatus = EFI_CRC_ERROR;
2379 } else {
2380 ErrorStatus = EFI_DEVICE_ERROR;
2381 }
2382
2383 Status = SdMmcSoftwareReset (Private, Slot, ErrIntStatus);
2384 if (EFI_ERROR (Status)) {
2385 return Status;
2386 }
2387
2388 return ErrorStatus;
2389 }
2390
2391 /**
2392 Reads the response data into the TRB buffer.
2393 This function assumes that caller made sure that
2394 command has completed.
2395
2396 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2397 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2398
2399 @retval EFI_SUCCESS Response read successfully.
2400 @retval Others Failed to get response.
2401 **/
2402 EFI_STATUS
2403 SdMmcGetResponse (
2404 IN SD_MMC_HC_PRIVATE_DATA *Private,
2405 IN SD_MMC_HC_TRB *Trb
2406 )
2407 {
2408 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2409 UINT8 Index;
2410 UINT32 Response[4];
2411 EFI_STATUS Status;
2412
2413 Packet = Trb->Packet;
2414
2415 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeBc) {
2416 return EFI_SUCCESS;
2417 }
2418
2419 for (Index = 0; Index < 4; Index++) {
2420 Status = SdMmcHcRwMmio (
2421 Private->PciIo,
2422 Trb->Slot,
2423 SD_MMC_HC_RESPONSE + Index * 4,
2424 TRUE,
2425 sizeof (UINT32),
2426 &Response[Index]
2427 );
2428 if (EFI_ERROR (Status)) {
2429 return Status;
2430 }
2431 }
2432 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2433
2434 return EFI_SUCCESS;
2435 }
2436
2437 /**
2438 Checks if the command completed. If the command
2439 completed it gets the response and records the
2440 command completion in the TRB.
2441
2442 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2443 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2444 @param[in] IntStatus Snapshot of the normal interrupt status register.
2445
2446 @retval EFI_SUCCESS Command completed successfully.
2447 @retval EFI_NOT_READY Command completion still pending.
2448 @retval Others Command failed to complete.
2449 **/
2450 EFI_STATUS
2451 SdMmcCheckCommandComplete (
2452 IN SD_MMC_HC_PRIVATE_DATA *Private,
2453 IN SD_MMC_HC_TRB *Trb,
2454 IN UINT16 IntStatus
2455 )
2456 {
2457 UINT16 Data16;
2458 EFI_STATUS Status;
2459
2460 if ((IntStatus & BIT0) != 0) {
2461 Data16 = BIT0;
2462 Status = SdMmcHcRwMmio (
2463 Private->PciIo,
2464 Trb->Slot,
2465 SD_MMC_HC_NOR_INT_STS,
2466 FALSE,
2467 sizeof (Data16),
2468 &Data16
2469 );
2470 if (EFI_ERROR (Status)) {
2471 return Status;
2472 }
2473 Status = SdMmcGetResponse (Private, Trb);
2474 if (EFI_ERROR (Status)) {
2475 return Status;
2476 }
2477 Trb->CommandComplete = TRUE;
2478 return EFI_SUCCESS;
2479 }
2480
2481 return EFI_NOT_READY;
2482 }
2483
2484 /**
2485 Update the SDMA address on the SDMA buffer boundary interrupt.
2486
2487 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2488 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2489
2490 @retval EFI_SUCCESS Updated SDMA buffer address.
2491 @retval Others Failed to update SDMA buffer address.
2492 **/
2493 EFI_STATUS
2494 SdMmcUpdateSdmaAddress (
2495 IN SD_MMC_HC_PRIVATE_DATA *Private,
2496 IN SD_MMC_HC_TRB *Trb
2497 )
2498 {
2499 UINT64 SdmaAddr;
2500 EFI_STATUS Status;
2501
2502 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
2503
2504 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2505 Status = SdMmcHcRwMmio (
2506 Private->PciIo,
2507 Trb->Slot,
2508 SD_MMC_HC_ADMA_SYS_ADDR,
2509 FALSE,
2510 sizeof (UINT64),
2511 &SdmaAddr
2512 );
2513 } else {
2514 Status = SdMmcHcRwMmio (
2515 Private->PciIo,
2516 Trb->Slot,
2517 SD_MMC_HC_SDMA_ADDR,
2518 FALSE,
2519 sizeof (UINT32),
2520 &SdmaAddr
2521 );
2522 }
2523
2524 if (EFI_ERROR (Status)) {
2525 return Status;
2526 }
2527
2528 Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
2529 return EFI_SUCCESS;
2530 }
2531
2532 /**
2533 Checks if the data transfer completed and performs any actions
2534 neccessary to continue the data transfer such as SDMA system
2535 address fixup or PIO data transfer.
2536
2537 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2538 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2539 @param[in] IntStatus Snapshot of the normal interrupt status register.
2540
2541 @retval EFI_SUCCESS Data transfer completed successfully.
2542 @retval EFI_NOT_READY Data transfer completion still pending.
2543 @retval Others Data transfer failed to complete.
2544 **/
2545 EFI_STATUS
2546 SdMmcCheckDataTransfer (
2547 IN SD_MMC_HC_PRIVATE_DATA *Private,
2548 IN SD_MMC_HC_TRB *Trb,
2549 IN UINT16 IntStatus
2550 )
2551 {
2552 UINT16 Data16;
2553 EFI_STATUS Status;
2554
2555 if ((IntStatus & BIT1) != 0) {
2556 Data16 = BIT1;
2557 Status = SdMmcHcRwMmio (
2558 Private->PciIo,
2559 Trb->Slot,
2560 SD_MMC_HC_NOR_INT_STS,
2561 FALSE,
2562 sizeof (Data16),
2563 &Data16
2564 );
2565 return Status;
2566 }
2567
2568 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) != 0)) {
2569 Data16 = BIT3;
2570 Status = SdMmcHcRwMmio (
2571 Private->PciIo,
2572 Trb->Slot,
2573 SD_MMC_HC_NOR_INT_STS,
2574 FALSE,
2575 sizeof (Data16),
2576 &Data16
2577 );
2578 if (EFI_ERROR (Status)) {
2579 return Status;
2580 }
2581 Status = SdMmcUpdateSdmaAddress (Private, Trb);
2582 if (EFI_ERROR (Status)) {
2583 return Status;
2584 }
2585 }
2586
2587 return EFI_NOT_READY;
2588 }
2589
2590 /**
2591 Check the TRB execution result.
2592
2593 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2594 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2595
2596 @retval EFI_SUCCESS The TRB is executed successfully.
2597 @retval EFI_NOT_READY The TRB is not completed for execution.
2598 @retval Others Some erros happen when executing this request.
2599
2600 **/
2601 EFI_STATUS
2602 SdMmcCheckTrbResult (
2603 IN SD_MMC_HC_PRIVATE_DATA *Private,
2604 IN SD_MMC_HC_TRB *Trb
2605 )
2606 {
2607 EFI_STATUS Status;
2608 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2609 UINT16 IntStatus;
2610 UINT32 PioLength;
2611
2612 Packet = Trb->Packet;
2613 //
2614 // Check Trb execution result by reading Normal Interrupt Status register.
2615 //
2616 Status = SdMmcHcRwMmio (
2617 Private->PciIo,
2618 Trb->Slot,
2619 SD_MMC_HC_NOR_INT_STS,
2620 TRUE,
2621 sizeof (IntStatus),
2622 &IntStatus
2623 );
2624 if (EFI_ERROR (Status)) {
2625 goto Done;
2626 }
2627
2628 //
2629 // Check if there are any errors reported by host controller
2630 // and if neccessary recover the controller before next command is executed.
2631 //
2632 Status = SdMmcCheckAndRecoverErrors (Private, Trb->Slot, IntStatus);
2633 if (EFI_ERROR (Status)) {
2634 goto Done;
2635 }
2636
2637 //
2638 // Tuning commands are the only ones that do not generate command
2639 // complete interrupt. Process them here before entering the code
2640 // that waits for command completion.
2641 //
2642 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
2643 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
2644 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
2645 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
2646 //
2647 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2648 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2649 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2650 //
2651 if ((IntStatus & BIT5) == BIT5) {
2652 //
2653 // Clear Buffer Read Ready interrupt at first.
2654 //
2655 IntStatus = BIT5;
2656 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2657 //
2658 // Read data out from Buffer Port register
2659 //
2660 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
2661 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
2662 }
2663 Status = EFI_SUCCESS;
2664 goto Done;
2665 }
2666 }
2667
2668 if (!Trb->CommandComplete) {
2669 Status = SdMmcCheckCommandComplete (Private, Trb, IntStatus);
2670 if (EFI_ERROR (Status)) {
2671 goto Done;
2672 }
2673 }
2674
2675 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc ||
2676 Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b ||
2677 Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b) {
2678 Status = SdMmcCheckDataTransfer (Private, Trb, IntStatus);
2679 } else {
2680 Status = EFI_SUCCESS;
2681 }
2682
2683 Done:
2684 if (Status != EFI_NOT_READY) {
2685 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2686 if (EFI_ERROR (Status)) {
2687 DEBUG ((DEBUG_ERROR, "TRB failed with %r\n", Status));
2688 SdMmcPrintTrb (DEBUG_ERROR, Trb);
2689 } else {
2690 DEBUG ((DEBUG_VERBOSE, "TRB success\n"));
2691 SdMmcPrintTrb (DEBUG_VERBOSE, Trb);
2692 }
2693 }
2694
2695 return Status;
2696 }
2697
2698 /**
2699 Wait for the TRB execution result.
2700
2701 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2702 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2703
2704 @retval EFI_SUCCESS The TRB is executed successfully.
2705 @retval Others Some erros happen when executing this request.
2706
2707 **/
2708 EFI_STATUS
2709 SdMmcWaitTrbResult (
2710 IN SD_MMC_HC_PRIVATE_DATA *Private,
2711 IN SD_MMC_HC_TRB *Trb
2712 )
2713 {
2714 EFI_STATUS Status;
2715 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2716 UINT64 Timeout;
2717 BOOLEAN InfiniteWait;
2718
2719 Packet = Trb->Packet;
2720 //
2721 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2722 //
2723 Timeout = Packet->Timeout;
2724 if (Timeout == 0) {
2725 InfiniteWait = TRUE;
2726 } else {
2727 InfiniteWait = FALSE;
2728 }
2729
2730 while (InfiniteWait || (Timeout > 0)) {
2731 //
2732 // Check Trb execution result by reading Normal Interrupt Status register.
2733 //
2734 Status = SdMmcCheckTrbResult (Private, Trb);
2735 if (Status != EFI_NOT_READY) {
2736 return Status;
2737 }
2738 //
2739 // Stall for 1 microsecond.
2740 //
2741 gBS->Stall (1);
2742
2743 Timeout--;
2744 }
2745
2746 return EFI_TIMEOUT;
2747 }
2748
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