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MdeModulePkg/SdMmcPciHcDxe: Use BaseClk if the target clock is larger
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
4
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
6
7 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include "SdMmcPciHcDxe.h"
19
20 /**
21 Dump the content of SD/MMC host controller's Capability Register.
22
23 @param[in] Slot The slot number of the SD card to send the command to.
24 @param[in] Capability The buffer to store the capability data.
25
26 **/
27 VOID
28 DumpCapabilityReg (
29 IN UINT8 Slot,
30 IN SD_MMC_HC_SLOT_CAP *Capability
31 )
32 {
33 //
34 // Dump Capability Data
35 //
36 DEBUG ((EFI_D_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
37 DEBUG ((EFI_D_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
38 DEBUG ((EFI_D_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
39 DEBUG ((EFI_D_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
40 DEBUG ((EFI_D_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
41 DEBUG ((EFI_D_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
42 DEBUG ((EFI_D_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
43 DEBUG ((EFI_D_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
44 DEBUG ((EFI_D_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
45 DEBUG ((EFI_D_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
46 DEBUG ((EFI_D_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
47 DEBUG ((EFI_D_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
48 DEBUG ((EFI_D_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));
49 DEBUG ((EFI_D_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
50 DEBUG ((EFI_D_INFO, " SlotType "));
51 if (Capability->SlotType == 0x00) {
52 DEBUG ((EFI_D_INFO, "%a\n", "Removable Slot"));
53 } else if (Capability->SlotType == 0x01) {
54 DEBUG ((EFI_D_INFO, "%a\n", "Embedded Slot"));
55 } else if (Capability->SlotType == 0x02) {
56 DEBUG ((EFI_D_INFO, "%a\n", "Shared Bus Slot"));
57 } else {
58 DEBUG ((EFI_D_INFO, "%a\n", "Reserved"));
59 }
60 DEBUG ((EFI_D_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
61 DEBUG ((EFI_D_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
62 DEBUG ((EFI_D_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
63 DEBUG ((EFI_D_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
64 DEBUG ((EFI_D_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
65 DEBUG ((EFI_D_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
66 DEBUG ((EFI_D_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
67 if (Capability->TimerCount == 0) {
68 DEBUG ((EFI_D_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
69 } else {
70 DEBUG ((EFI_D_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
71 }
72 DEBUG ((EFI_D_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
73 DEBUG ((EFI_D_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
74 DEBUG ((EFI_D_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
75 DEBUG ((EFI_D_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
76 return;
77 }
78
79 /**
80 Read SlotInfo register from SD/MMC host controller pci config space.
81
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
85
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
88
89 **/
90 EFI_STATUS
91 EFIAPI
92 SdMmcHcGetSlotInfo (
93 IN EFI_PCI_IO_PROTOCOL *PciIo,
94 OUT UINT8 *FirstBar,
95 OUT UINT8 *SlotNum
96 )
97 {
98 EFI_STATUS Status;
99 SD_MMC_HC_SLOT_INFO SlotInfo;
100
101 Status = PciIo->Pci.Read (
102 PciIo,
103 EfiPciIoWidthUint8,
104 SD_MMC_HC_SLOT_OFFSET,
105 sizeof (SlotInfo),
106 &SlotInfo
107 );
108 if (EFI_ERROR (Status)) {
109 return Status;
110 }
111
112 *FirstBar = SlotInfo.FirstBar;
113 *SlotNum = SlotInfo.SlotNum + 1;
114 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
115 return EFI_SUCCESS;
116 }
117
118 /**
119 Read/Write specified SD/MMC host controller mmio register.
120
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
126 memory operation.
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
135
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
139
140 **/
141 EFI_STATUS
142 EFIAPI
143 SdMmcHcRwMmio (
144 IN EFI_PCI_IO_PROTOCOL *PciIo,
145 IN UINT8 BarIndex,
146 IN UINT32 Offset,
147 IN BOOLEAN Read,
148 IN UINT8 Count,
149 IN OUT VOID *Data
150 )
151 {
152 EFI_STATUS Status;
153
154 if ((PciIo == NULL) || (Data == NULL)) {
155 return EFI_INVALID_PARAMETER;
156 }
157
158 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
159 return EFI_INVALID_PARAMETER;
160 }
161
162 if (Read) {
163 Status = PciIo->Mem.Read (
164 PciIo,
165 EfiPciIoWidthUint8,
166 BarIndex,
167 (UINT64) Offset,
168 Count,
169 Data
170 );
171 } else {
172 Status = PciIo->Mem.Write (
173 PciIo,
174 EfiPciIoWidthUint8,
175 BarIndex,
176 (UINT64) Offset,
177 Count,
178 Data
179 );
180 }
181
182 return Status;
183 }
184
185 /**
186 Do OR operation with the value of the specified SD/MMC host controller mmio register.
187
188 @param[in] PciIo The PCI IO protocol instance.
189 @param[in] BarIndex The BAR index of the standard PCI Configuration
190 header to use as the base address for the memory
191 operation to perform.
192 @param[in] Offset The offset within the selected BAR to start the
193 memory operation.
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2 , 4 or 8 bytes.
196 @param[in] OrData The pointer to the data used to do OR operation.
197 The caller is responsible for having ownership of
198 the data buffer and ensuring its size not less than
199 Count bytes.
200
201 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
202 @retval EFI_SUCCESS The OR operation succeeds.
203 @retval Others The OR operation fails.
204
205 **/
206 EFI_STATUS
207 EFIAPI
208 SdMmcHcOrMmio (
209 IN EFI_PCI_IO_PROTOCOL *PciIo,
210 IN UINT8 BarIndex,
211 IN UINT32 Offset,
212 IN UINT8 Count,
213 IN VOID *OrData
214 )
215 {
216 EFI_STATUS Status;
217 UINT64 Data;
218 UINT64 Or;
219
220 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
221 if (EFI_ERROR (Status)) {
222 return Status;
223 }
224
225 if (Count == 1) {
226 Or = *(UINT8*) OrData;
227 } else if (Count == 2) {
228 Or = *(UINT16*) OrData;
229 } else if (Count == 4) {
230 Or = *(UINT32*) OrData;
231 } else if (Count == 8) {
232 Or = *(UINT64*) OrData;
233 } else {
234 return EFI_INVALID_PARAMETER;
235 }
236
237 Data |= Or;
238 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
239
240 return Status;
241 }
242
243 /**
244 Do AND operation with the value of the specified SD/MMC host controller mmio register.
245
246 @param[in] PciIo The PCI IO protocol instance.
247 @param[in] BarIndex The BAR index of the standard PCI Configuration
248 header to use as the base address for the memory
249 operation to perform.
250 @param[in] Offset The offset within the selected BAR to start the
251 memory operation.
252 @param[in] Count The width of the mmio register in bytes.
253 Must be 1, 2 , 4 or 8 bytes.
254 @param[in] AndData The pointer to the data used to do AND operation.
255 The caller is responsible for having ownership of
256 the data buffer and ensuring its size not less than
257 Count bytes.
258
259 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
260 @retval EFI_SUCCESS The AND operation succeeds.
261 @retval Others The AND operation fails.
262
263 **/
264 EFI_STATUS
265 EFIAPI
266 SdMmcHcAndMmio (
267 IN EFI_PCI_IO_PROTOCOL *PciIo,
268 IN UINT8 BarIndex,
269 IN UINT32 Offset,
270 IN UINT8 Count,
271 IN VOID *AndData
272 )
273 {
274 EFI_STATUS Status;
275 UINT64 Data;
276 UINT64 And;
277
278 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
279 if (EFI_ERROR (Status)) {
280 return Status;
281 }
282
283 if (Count == 1) {
284 And = *(UINT8*) AndData;
285 } else if (Count == 2) {
286 And = *(UINT16*) AndData;
287 } else if (Count == 4) {
288 And = *(UINT32*) AndData;
289 } else if (Count == 8) {
290 And = *(UINT64*) AndData;
291 } else {
292 return EFI_INVALID_PARAMETER;
293 }
294
295 Data &= And;
296 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
297
298 return Status;
299 }
300
301 /**
302 Wait for the value of the specified MMIO register set to the test value.
303
304 @param[in] PciIo The PCI IO protocol instance.
305 @param[in] BarIndex The BAR index of the standard PCI Configuration
306 header to use as the base address for the memory
307 operation to perform.
308 @param[in] Offset The offset within the selected BAR to start the
309 memory operation.
310 @param[in] Count The width of the mmio register in bytes.
311 Must be 1, 2, 4 or 8 bytes.
312 @param[in] MaskValue The mask value of memory.
313 @param[in] TestValue The test value of memory.
314
315 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
316 @retval EFI_SUCCESS The MMIO register has expected value.
317 @retval Others The MMIO operation fails.
318
319 **/
320 EFI_STATUS
321 EFIAPI
322 SdMmcHcCheckMmioSet (
323 IN EFI_PCI_IO_PROTOCOL *PciIo,
324 IN UINT8 BarIndex,
325 IN UINT32 Offset,
326 IN UINT8 Count,
327 IN UINT64 MaskValue,
328 IN UINT64 TestValue
329 )
330 {
331 EFI_STATUS Status;
332 UINT64 Value;
333
334 //
335 // Access PCI MMIO space to see if the value is the tested one.
336 //
337 Value = 0;
338 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
339 if (EFI_ERROR (Status)) {
340 return Status;
341 }
342
343 Value &= MaskValue;
344
345 if (Value == TestValue) {
346 return EFI_SUCCESS;
347 }
348
349 return EFI_NOT_READY;
350 }
351
352 /**
353 Wait for the value of the specified MMIO register set to the test value.
354
355 @param[in] PciIo The PCI IO protocol instance.
356 @param[in] BarIndex The BAR index of the standard PCI Configuration
357 header to use as the base address for the memory
358 operation to perform.
359 @param[in] Offset The offset within the selected BAR to start the
360 memory operation.
361 @param[in] Count The width of the mmio register in bytes.
362 Must be 1, 2, 4 or 8 bytes.
363 @param[in] MaskValue The mask value of memory.
364 @param[in] TestValue The test value of memory.
365 @param[in] Timeout The time out value for wait memory set, uses 1
366 microsecond as a unit.
367
368 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
369 range.
370 @retval EFI_SUCCESS The MMIO register has expected value.
371 @retval Others The MMIO operation fails.
372
373 **/
374 EFI_STATUS
375 EFIAPI
376 SdMmcHcWaitMmioSet (
377 IN EFI_PCI_IO_PROTOCOL *PciIo,
378 IN UINT8 BarIndex,
379 IN UINT32 Offset,
380 IN UINT8 Count,
381 IN UINT64 MaskValue,
382 IN UINT64 TestValue,
383 IN UINT64 Timeout
384 )
385 {
386 EFI_STATUS Status;
387 BOOLEAN InfiniteWait;
388
389 if (Timeout == 0) {
390 InfiniteWait = TRUE;
391 } else {
392 InfiniteWait = FALSE;
393 }
394
395 while (InfiniteWait || (Timeout > 0)) {
396 Status = SdMmcHcCheckMmioSet (
397 PciIo,
398 BarIndex,
399 Offset,
400 Count,
401 MaskValue,
402 TestValue
403 );
404 if (Status != EFI_NOT_READY) {
405 return Status;
406 }
407
408 //
409 // Stall for 1 microsecond.
410 //
411 gBS->Stall (1);
412
413 Timeout--;
414 }
415
416 return EFI_TIMEOUT;
417 }
418
419 /**
420 Software reset the specified SD/MMC host controller and enable all interrupts.
421
422 @param[in] PciIo The PCI IO protocol instance.
423 @param[in] Slot The slot number of the SD card to send the command to.
424
425 @retval EFI_SUCCESS The software reset executes successfully.
426 @retval Others The software reset fails.
427
428 **/
429 EFI_STATUS
430 SdMmcHcReset (
431 IN EFI_PCI_IO_PROTOCOL *PciIo,
432 IN UINT8 Slot
433 )
434 {
435 EFI_STATUS Status;
436 UINT8 SwReset;
437
438 SwReset = 0xFF;
439 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);
440
441 if (EFI_ERROR (Status)) {
442 DEBUG ((EFI_D_ERROR, "SdMmcHcReset: write full 1 fails: %r\n", Status));
443 return Status;
444 }
445
446 Status = SdMmcHcWaitMmioSet (
447 PciIo,
448 Slot,
449 SD_MMC_HC_SW_RST,
450 sizeof (SwReset),
451 0xFF,
452 0x00,
453 SD_MMC_HC_GENERIC_TIMEOUT
454 );
455 if (EFI_ERROR (Status)) {
456 DEBUG ((EFI_D_INFO, "SdMmcHcReset: reset done with %r\n", Status));
457 return Status;
458 }
459 //
460 // Enable all interrupt after reset all.
461 //
462 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
463
464 return Status;
465 }
466
467 /**
468 Set all interrupt status bits in Normal and Error Interrupt Status Enable
469 register.
470
471 @param[in] PciIo The PCI IO protocol instance.
472 @param[in] Slot The slot number of the SD card to send the command to.
473
474 @retval EFI_SUCCESS The operation executes successfully.
475 @retval Others The operation fails.
476
477 **/
478 EFI_STATUS
479 SdMmcHcEnableInterrupt (
480 IN EFI_PCI_IO_PROTOCOL *PciIo,
481 IN UINT8 Slot
482 )
483 {
484 EFI_STATUS Status;
485 UINT16 IntStatus;
486
487 //
488 // Enable all bits in Error Interrupt Status Enable Register
489 //
490 IntStatus = 0xFFFF;
491 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
492 if (EFI_ERROR (Status)) {
493 return Status;
494 }
495 //
496 // Enable all bits in Normal Interrupt Status Enable Register
497 //
498 IntStatus = 0xFFFF;
499 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
500
501 return Status;
502 }
503
504 /**
505 Get the capability data from the specified slot.
506
507 @param[in] PciIo The PCI IO protocol instance.
508 @param[in] Slot The slot number of the SD card to send the command to.
509 @param[out] Capability The buffer to store the capability data.
510
511 @retval EFI_SUCCESS The operation executes successfully.
512 @retval Others The operation fails.
513
514 **/
515 EFI_STATUS
516 SdMmcHcGetCapability (
517 IN EFI_PCI_IO_PROTOCOL *PciIo,
518 IN UINT8 Slot,
519 OUT SD_MMC_HC_SLOT_CAP *Capability
520 )
521 {
522 EFI_STATUS Status;
523 UINT64 Cap;
524
525 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
526 if (EFI_ERROR (Status)) {
527 return Status;
528 }
529
530 CopyMem (Capability, &Cap, sizeof (Cap));
531
532 return EFI_SUCCESS;
533 }
534
535 /**
536 Get the maximum current capability data from the specified slot.
537
538 @param[in] PciIo The PCI IO protocol instance.
539 @param[in] Slot The slot number of the SD card to send the command to.
540 @param[out] MaxCurrent The buffer to store the maximum current capability data.
541
542 @retval EFI_SUCCESS The operation executes successfully.
543 @retval Others The operation fails.
544
545 **/
546 EFI_STATUS
547 SdMmcHcGetMaxCurrent (
548 IN EFI_PCI_IO_PROTOCOL *PciIo,
549 IN UINT8 Slot,
550 OUT UINT64 *MaxCurrent
551 )
552 {
553 EFI_STATUS Status;
554
555 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
556
557 return Status;
558 }
559
560 /**
561 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
562 slot.
563
564 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
565
566 @param[in] PciIo The PCI IO protocol instance.
567 @param[in] Slot The slot number of the SD card to send the command to.
568 @param[out] MediaPresent The pointer to the media present boolean value.
569
570 @retval EFI_SUCCESS There is no media change happened.
571 @retval EFI_MEDIA_CHANGED There is media change happened.
572 @retval Others The detection fails.
573
574 **/
575 EFI_STATUS
576 SdMmcHcCardDetect (
577 IN EFI_PCI_IO_PROTOCOL *PciIo,
578 IN UINT8 Slot,
579 OUT BOOLEAN *MediaPresent
580 )
581 {
582 EFI_STATUS Status;
583 UINT16 Data;
584 UINT32 PresentState;
585
586 //
587 // Check Present State Register to see if there is a card presented.
588 //
589 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
590 if (EFI_ERROR (Status)) {
591 return Status;
592 }
593
594 if ((PresentState & BIT16) != 0) {
595 *MediaPresent = TRUE;
596 } else {
597 *MediaPresent = FALSE;
598 }
599
600 //
601 // Check Normal Interrupt Status Register
602 //
603 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
604 if (EFI_ERROR (Status)) {
605 return Status;
606 }
607
608 if ((Data & (BIT6 | BIT7)) != 0) {
609 //
610 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
611 //
612 Data &= BIT6 | BIT7;
613 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
614 if (EFI_ERROR (Status)) {
615 return Status;
616 }
617
618 return EFI_MEDIA_CHANGED;
619 }
620
621 return EFI_SUCCESS;
622 }
623
624 /**
625 Stop SD/MMC card clock.
626
627 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
628
629 @param[in] PciIo The PCI IO protocol instance.
630 @param[in] Slot The slot number of the SD card to send the command to.
631
632 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
633 @retval Others Fail to stop SD/MMC clock.
634
635 **/
636 EFI_STATUS
637 SdMmcHcStopClock (
638 IN EFI_PCI_IO_PROTOCOL *PciIo,
639 IN UINT8 Slot
640 )
641 {
642 EFI_STATUS Status;
643 UINT32 PresentState;
644 UINT16 ClockCtrl;
645
646 //
647 // Ensure no SD transactions are occurring on the SD Bus by
648 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
649 // in the Present State register to be 0.
650 //
651 Status = SdMmcHcWaitMmioSet (
652 PciIo,
653 Slot,
654 SD_MMC_HC_PRESENT_STATE,
655 sizeof (PresentState),
656 BIT0 | BIT1,
657 0,
658 SD_MMC_HC_GENERIC_TIMEOUT
659 );
660 if (EFI_ERROR (Status)) {
661 return Status;
662 }
663
664 //
665 // Set SD Clock Enable in the Clock Control register to 0
666 //
667 ClockCtrl = (UINT16)~BIT2;
668 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
669
670 return Status;
671 }
672
673 /**
674 SD/MMC card clock supply.
675
676 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
677
678 @param[in] PciIo The PCI IO protocol instance.
679 @param[in] Slot The slot number of the SD card to send the command to.
680 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
681 @param[in] Capability The capability of the slot.
682
683 @retval EFI_SUCCESS The clock is supplied successfully.
684 @retval Others The clock isn't supplied successfully.
685
686 **/
687 EFI_STATUS
688 SdMmcHcClockSupply (
689 IN EFI_PCI_IO_PROTOCOL *PciIo,
690 IN UINT8 Slot,
691 IN UINT64 ClockFreq,
692 IN SD_MMC_HC_SLOT_CAP Capability
693 )
694 {
695 EFI_STATUS Status;
696 UINT32 BaseClkFreq;
697 UINT32 SettingFreq;
698 UINT32 Divisor;
699 UINT32 Remainder;
700 UINT16 ControllerVer;
701 UINT16 ClockCtrl;
702
703 //
704 // Calculate a divisor for SD clock frequency
705 //
706 ASSERT (Capability.BaseClkFreq != 0);
707
708 BaseClkFreq = Capability.BaseClkFreq;
709 if (ClockFreq == 0) {
710 return EFI_INVALID_PARAMETER;
711 }
712
713 if (ClockFreq > (BaseClkFreq * 1000)) {
714 ClockFreq = BaseClkFreq * 1000;
715 }
716
717 //
718 // Calculate the divisor of base frequency.
719 //
720 Divisor = 0;
721 SettingFreq = BaseClkFreq * 1000;
722 while (ClockFreq < SettingFreq) {
723 Divisor++;
724
725 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
726 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
727 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
728 break;
729 }
730 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
731 SettingFreq ++;
732 }
733 }
734
735 DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
736
737 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
738 if (EFI_ERROR (Status)) {
739 return Status;
740 }
741 //
742 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
743 //
744 if ((ControllerVer & 0xFF) == 2) {
745 ASSERT (Divisor <= 0x3FF);
746 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
747 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
748 //
749 // Only the most significant bit can be used as divisor.
750 //
751 if (((Divisor - 1) & Divisor) != 0) {
752 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
753 }
754 ASSERT (Divisor <= 0x80);
755 ClockCtrl = (Divisor & 0xFF) << 8;
756 } else {
757 DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
758 return EFI_UNSUPPORTED;
759 }
760
761 //
762 // Stop bus clock at first
763 //
764 Status = SdMmcHcStopClock (PciIo, Slot);
765 if (EFI_ERROR (Status)) {
766 return Status;
767 }
768
769 //
770 // Supply clock frequency with specified divisor
771 //
772 ClockCtrl |= BIT0;
773 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
774 if (EFI_ERROR (Status)) {
775 DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
776 return Status;
777 }
778
779 //
780 // Wait Internal Clock Stable in the Clock Control register to be 1
781 //
782 Status = SdMmcHcWaitMmioSet (
783 PciIo,
784 Slot,
785 SD_MMC_HC_CLOCK_CTRL,
786 sizeof (ClockCtrl),
787 BIT1,
788 BIT1,
789 SD_MMC_HC_GENERIC_TIMEOUT
790 );
791 if (EFI_ERROR (Status)) {
792 return Status;
793 }
794
795 //
796 // Set SD Clock Enable in the Clock Control register to 1
797 //
798 ClockCtrl = BIT2;
799 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
800
801 return Status;
802 }
803
804 /**
805 SD/MMC bus power control.
806
807 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
808
809 @param[in] PciIo The PCI IO protocol instance.
810 @param[in] Slot The slot number of the SD card to send the command to.
811 @param[in] PowerCtrl The value setting to the power control register.
812
813 @retval TRUE There is a SD/MMC card attached.
814 @retval FALSE There is no a SD/MMC card attached.
815
816 **/
817 EFI_STATUS
818 SdMmcHcPowerControl (
819 IN EFI_PCI_IO_PROTOCOL *PciIo,
820 IN UINT8 Slot,
821 IN UINT8 PowerCtrl
822 )
823 {
824 EFI_STATUS Status;
825
826 //
827 // Clr SD Bus Power
828 //
829 PowerCtrl &= (UINT8)~BIT0;
830 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
831 if (EFI_ERROR (Status)) {
832 return Status;
833 }
834
835 //
836 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
837 //
838 PowerCtrl |= BIT0;
839 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
840
841 return Status;
842 }
843
844 /**
845 Set the SD/MMC bus width.
846
847 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
848
849 @param[in] PciIo The PCI IO protocol instance.
850 @param[in] Slot The slot number of the SD card to send the command to.
851 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
852
853 @retval EFI_SUCCESS The bus width is set successfully.
854 @retval Others The bus width isn't set successfully.
855
856 **/
857 EFI_STATUS
858 SdMmcHcSetBusWidth (
859 IN EFI_PCI_IO_PROTOCOL *PciIo,
860 IN UINT8 Slot,
861 IN UINT16 BusWidth
862 )
863 {
864 EFI_STATUS Status;
865 UINT8 HostCtrl1;
866
867 if (BusWidth == 1) {
868 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
869 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
870 } else if (BusWidth == 4) {
871 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
872 if (EFI_ERROR (Status)) {
873 return Status;
874 }
875 HostCtrl1 |= BIT1;
876 HostCtrl1 &= (UINT8)~BIT5;
877 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
878 } else if (BusWidth == 8) {
879 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
880 if (EFI_ERROR (Status)) {
881 return Status;
882 }
883 HostCtrl1 &= (UINT8)~BIT1;
884 HostCtrl1 |= BIT5;
885 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
886 } else {
887 ASSERT (FALSE);
888 return EFI_INVALID_PARAMETER;
889 }
890
891 return Status;
892 }
893
894 /**
895 Supply SD/MMC card with lowest clock frequency at initialization.
896
897 @param[in] PciIo The PCI IO protocol instance.
898 @param[in] Slot The slot number of the SD card to send the command to.
899 @param[in] Capability The capability of the slot.
900
901 @retval EFI_SUCCESS The clock is supplied successfully.
902 @retval Others The clock isn't supplied successfully.
903
904 **/
905 EFI_STATUS
906 SdMmcHcInitClockFreq (
907 IN EFI_PCI_IO_PROTOCOL *PciIo,
908 IN UINT8 Slot,
909 IN SD_MMC_HC_SLOT_CAP Capability
910 )
911 {
912 EFI_STATUS Status;
913 UINT32 InitFreq;
914
915 //
916 // Calculate a divisor for SD clock frequency
917 //
918 if (Capability.BaseClkFreq == 0) {
919 //
920 // Don't support get Base Clock Frequency information via another method
921 //
922 return EFI_UNSUPPORTED;
923 }
924 //
925 // Supply 400KHz clock frequency at initialization phase.
926 //
927 InitFreq = 400;
928 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
929 return Status;
930 }
931
932 /**
933 Supply SD/MMC card with maximum voltage at initialization.
934
935 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
936
937 @param[in] PciIo The PCI IO protocol instance.
938 @param[in] Slot The slot number of the SD card to send the command to.
939 @param[in] Capability The capability of the slot.
940
941 @retval EFI_SUCCESS The voltage is supplied successfully.
942 @retval Others The voltage isn't supplied successfully.
943
944 **/
945 EFI_STATUS
946 SdMmcHcInitPowerVoltage (
947 IN EFI_PCI_IO_PROTOCOL *PciIo,
948 IN UINT8 Slot,
949 IN SD_MMC_HC_SLOT_CAP Capability
950 )
951 {
952 EFI_STATUS Status;
953 UINT8 MaxVoltage;
954 UINT8 HostCtrl2;
955
956 //
957 // Calculate supported maximum voltage according to SD Bus Voltage Select
958 //
959 if (Capability.Voltage33 != 0) {
960 //
961 // Support 3.3V
962 //
963 MaxVoltage = 0x0E;
964 } else if (Capability.Voltage30 != 0) {
965 //
966 // Support 3.0V
967 //
968 MaxVoltage = 0x0C;
969 } else if (Capability.Voltage18 != 0) {
970 //
971 // Support 1.8V
972 //
973 MaxVoltage = 0x0A;
974 HostCtrl2 = BIT3;
975 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
976 gBS->Stall (5000);
977 if (EFI_ERROR (Status)) {
978 return Status;
979 }
980 } else {
981 ASSERT (FALSE);
982 return EFI_DEVICE_ERROR;
983 }
984
985 //
986 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
987 //
988 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
989
990 return Status;
991 }
992
993 /**
994 Initialize the Timeout Control register with most conservative value at initialization.
995
996 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
997
998 @param[in] PciIo The PCI IO protocol instance.
999 @param[in] Slot The slot number of the SD card to send the command to.
1000
1001 @retval EFI_SUCCESS The timeout control register is configured successfully.
1002 @retval Others The timeout control register isn't configured successfully.
1003
1004 **/
1005 EFI_STATUS
1006 SdMmcHcInitTimeoutCtrl (
1007 IN EFI_PCI_IO_PROTOCOL *PciIo,
1008 IN UINT8 Slot
1009 )
1010 {
1011 EFI_STATUS Status;
1012 UINT8 Timeout;
1013
1014 Timeout = 0x0E;
1015 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1016
1017 return Status;
1018 }
1019
1020 /**
1021 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1022 at initialization.
1023
1024 @param[in] PciIo The PCI IO protocol instance.
1025 @param[in] Slot The slot number of the SD card to send the command to.
1026 @param[in] Capability The capability of the slot.
1027
1028 @retval EFI_SUCCESS The host controller is initialized successfully.
1029 @retval Others The host controller isn't initialized successfully.
1030
1031 **/
1032 EFI_STATUS
1033 SdMmcHcInitHost (
1034 IN EFI_PCI_IO_PROTOCOL *PciIo,
1035 IN UINT8 Slot,
1036 IN SD_MMC_HC_SLOT_CAP Capability
1037 )
1038 {
1039 EFI_STATUS Status;
1040
1041 Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
1042 if (EFI_ERROR (Status)) {
1043 return Status;
1044 }
1045
1046 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1047 if (EFI_ERROR (Status)) {
1048 return Status;
1049 }
1050
1051 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1052 return Status;
1053 }
1054
1055 /**
1056 Turn on/off LED.
1057
1058 @param[in] PciIo The PCI IO protocol instance.
1059 @param[in] Slot The slot number of the SD card to send the command to.
1060 @param[in] On The boolean to turn on/off LED.
1061
1062 @retval EFI_SUCCESS The LED is turned on/off successfully.
1063 @retval Others The LED isn't turned on/off successfully.
1064
1065 **/
1066 EFI_STATUS
1067 SdMmcHcLedOnOff (
1068 IN EFI_PCI_IO_PROTOCOL *PciIo,
1069 IN UINT8 Slot,
1070 IN BOOLEAN On
1071 )
1072 {
1073 EFI_STATUS Status;
1074 UINT8 HostCtrl1;
1075
1076 if (On) {
1077 HostCtrl1 = BIT0;
1078 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1079 } else {
1080 HostCtrl1 = (UINT8)~BIT0;
1081 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1082 }
1083
1084 return Status;
1085 }
1086
1087 /**
1088 Build ADMA descriptor table for transfer.
1089
1090 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
1091
1092 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1093
1094 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1095 @retval Others The ADMA descriptor table isn't created successfully.
1096
1097 **/
1098 EFI_STATUS
1099 BuildAdmaDescTable (
1100 IN SD_MMC_HC_TRB *Trb
1101 )
1102 {
1103 EFI_PHYSICAL_ADDRESS Data;
1104 UINT64 DataLen;
1105 UINT64 Entries;
1106 UINT32 Index;
1107 UINT64 Remaining;
1108 UINT32 Address;
1109 UINTN TableSize;
1110 EFI_PCI_IO_PROTOCOL *PciIo;
1111 EFI_STATUS Status;
1112 UINTN Bytes;
1113
1114 Data = Trb->DataPhy;
1115 DataLen = Trb->DataLen;
1116 PciIo = Trb->Private->PciIo;
1117 //
1118 // Only support 32bit ADMA Descriptor Table
1119 //
1120 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
1121 return EFI_INVALID_PARAMETER;
1122 }
1123 //
1124 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1125 // for 32-bit address descriptor table.
1126 //
1127 if ((Data & (BIT0 | BIT1)) != 0) {
1128 DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1129 }
1130
1131 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
1132 TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));
1133 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1134 Status = PciIo->AllocateBuffer (
1135 PciIo,
1136 AllocateAnyPages,
1137 EfiBootServicesData,
1138 EFI_SIZE_TO_PAGES (TableSize),
1139 (VOID **)&Trb->AdmaDesc,
1140 0
1141 );
1142 if (EFI_ERROR (Status)) {
1143 return EFI_OUT_OF_RESOURCES;
1144 }
1145 ZeroMem (Trb->AdmaDesc, TableSize);
1146 Bytes = TableSize;
1147 Status = PciIo->Map (
1148 PciIo,
1149 EfiPciIoOperationBusMasterCommonBuffer,
1150 Trb->AdmaDesc,
1151 &Bytes,
1152 &Trb->AdmaDescPhy,
1153 &Trb->AdmaMap
1154 );
1155
1156 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1157 //
1158 // Map error or unable to map the whole RFis buffer into a contiguous region.
1159 //
1160 PciIo->FreeBuffer (
1161 PciIo,
1162 EFI_SIZE_TO_PAGES (TableSize),
1163 Trb->AdmaDesc
1164 );
1165 return EFI_OUT_OF_RESOURCES;
1166 }
1167
1168 if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1169 //
1170 // The ADMA doesn't support 64bit addressing.
1171 //
1172 PciIo->Unmap (
1173 PciIo,
1174 Trb->AdmaMap
1175 );
1176 PciIo->FreeBuffer (
1177 PciIo,
1178 EFI_SIZE_TO_PAGES (TableSize),
1179 Trb->AdmaDesc
1180 );
1181 return EFI_DEVICE_ERROR;
1182 }
1183
1184 Remaining = DataLen;
1185 Address = (UINT32)Data;
1186 for (Index = 0; Index < Entries; Index++) {
1187 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
1188 Trb->AdmaDesc[Index].Valid = 1;
1189 Trb->AdmaDesc[Index].Act = 2;
1190 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
1191 Trb->AdmaDesc[Index].Address = Address;
1192 break;
1193 } else {
1194 Trb->AdmaDesc[Index].Valid = 1;
1195 Trb->AdmaDesc[Index].Act = 2;
1196 Trb->AdmaDesc[Index].Length = 0;
1197 Trb->AdmaDesc[Index].Address = Address;
1198 }
1199
1200 Remaining -= ADMA_MAX_DATA_PER_LINE;
1201 Address += ADMA_MAX_DATA_PER_LINE;
1202 }
1203
1204 //
1205 // Set the last descriptor line as end of descriptor table
1206 //
1207 Trb->AdmaDesc[Index].End = 1;
1208 return EFI_SUCCESS;
1209 }
1210
1211 /**
1212 Create a new TRB for the SD/MMC cmd request.
1213
1214 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1215 @param[in] Slot The slot number of the SD card to send the command to.
1216 @param[in] Packet A pointer to the SD command data structure.
1217 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1218 not NULL, then nonblocking I/O is performed, and Event
1219 will be signaled when the Packet completes.
1220
1221 @return Created Trb or NULL.
1222
1223 **/
1224 SD_MMC_HC_TRB *
1225 SdMmcCreateTrb (
1226 IN SD_MMC_HC_PRIVATE_DATA *Private,
1227 IN UINT8 Slot,
1228 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1229 IN EFI_EVENT Event
1230 )
1231 {
1232 SD_MMC_HC_TRB *Trb;
1233 EFI_STATUS Status;
1234 EFI_TPL OldTpl;
1235 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1236 EFI_PCI_IO_PROTOCOL *PciIo;
1237 UINTN MapLength;
1238
1239 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1240 if (Trb == NULL) {
1241 return NULL;
1242 }
1243
1244 Trb->Signature = SD_MMC_HC_TRB_SIG;
1245 Trb->Slot = Slot;
1246 Trb->BlockSize = 0x200;
1247 Trb->Packet = Packet;
1248 Trb->Event = Event;
1249 Trb->Started = FALSE;
1250 Trb->Timeout = Packet->Timeout;
1251 Trb->Private = Private;
1252
1253 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1254 Trb->Data = Packet->InDataBuffer;
1255 Trb->DataLen = Packet->InTransferLength;
1256 Trb->Read = TRUE;
1257 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1258 Trb->Data = Packet->OutDataBuffer;
1259 Trb->DataLen = Packet->OutTransferLength;
1260 Trb->Read = FALSE;
1261 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1262 Trb->Data = NULL;
1263 Trb->DataLen = 0;
1264 } else {
1265 goto Error;
1266 }
1267
1268 if (Trb->Read) {
1269 Flag = EfiPciIoOperationBusMasterWrite;
1270 } else {
1271 Flag = EfiPciIoOperationBusMasterRead;
1272 }
1273
1274 PciIo = Private->PciIo;
1275 if (Trb->DataLen != 0) {
1276 MapLength = Trb->DataLen;
1277 Status = PciIo->Map (
1278 PciIo,
1279 Flag,
1280 Trb->Data,
1281 &MapLength,
1282 &Trb->DataPhy,
1283 &Trb->DataMap
1284 );
1285 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1286 Status = EFI_BAD_BUFFER_SIZE;
1287 goto Error;
1288 }
1289 }
1290
1291 if ((Trb->DataLen % Trb->BlockSize) != 0) {
1292 if (Trb->DataLen < Trb->BlockSize) {
1293 Trb->BlockSize = (UINT16)Trb->DataLen;
1294 }
1295 }
1296
1297 if (Trb->DataLen == 0) {
1298 Trb->Mode = SdMmcNoData;
1299 } else if (Private->Capability[Slot].Adma2 != 0) {
1300 Trb->Mode = SdMmcAdmaMode;
1301 Status = BuildAdmaDescTable (Trb);
1302 if (EFI_ERROR (Status)) {
1303 PciIo->Unmap (PciIo, Trb->DataMap);
1304 goto Error;
1305 }
1306 } else if (Private->Capability[Slot].Sdma != 0) {
1307 Trb->Mode = SdMmcSdmaMode;
1308 } else {
1309 Trb->Mode = SdMmcPioMode;
1310 }
1311
1312 if (Event != NULL) {
1313 OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
1314 InsertTailList (&Private->Queue, &Trb->TrbList);
1315 gBS->RestoreTPL (OldTpl);
1316 }
1317
1318 return Trb;
1319
1320 Error:
1321 SdMmcFreeTrb (Trb);
1322 return NULL;
1323 }
1324
1325 /**
1326 Free the resource used by the TRB.
1327
1328 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1329
1330 **/
1331 VOID
1332 SdMmcFreeTrb (
1333 IN SD_MMC_HC_TRB *Trb
1334 )
1335 {
1336 EFI_PCI_IO_PROTOCOL *PciIo;
1337
1338 PciIo = Trb->Private->PciIo;
1339
1340 if (Trb->AdmaMap != NULL) {
1341 PciIo->Unmap (
1342 PciIo,
1343 Trb->AdmaMap
1344 );
1345 }
1346 if (Trb->AdmaDesc != NULL) {
1347 PciIo->FreeBuffer (
1348 PciIo,
1349 Trb->AdmaPages,
1350 Trb->AdmaDesc
1351 );
1352 }
1353 if (Trb->DataMap != NULL) {
1354 PciIo->Unmap (
1355 PciIo,
1356 Trb->DataMap
1357 );
1358 }
1359 FreePool (Trb);
1360 return;
1361 }
1362
1363 /**
1364 Check if the env is ready for execute specified TRB.
1365
1366 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1367 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1368
1369 @retval EFI_SUCCESS The env is ready for TRB execution.
1370 @retval EFI_NOT_READY The env is not ready for TRB execution.
1371 @retval Others Some erros happen.
1372
1373 **/
1374 EFI_STATUS
1375 SdMmcCheckTrbEnv (
1376 IN SD_MMC_HC_PRIVATE_DATA *Private,
1377 IN SD_MMC_HC_TRB *Trb
1378 )
1379 {
1380 EFI_STATUS Status;
1381 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1382 EFI_PCI_IO_PROTOCOL *PciIo;
1383 UINT32 PresentState;
1384
1385 Packet = Trb->Packet;
1386
1387 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1388 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1389 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1390 //
1391 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1392 // the Present State register to be 0
1393 //
1394 PresentState = BIT0 | BIT1;
1395 //
1396 // For Send Tuning Block cmd, just wait for Command Inhibit (CMD) to be 0
1397 //
1398 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1399 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1400 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1401 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1402 PresentState = BIT0;
1403 }
1404 } else {
1405 //
1406 // Wait Command Inhibit (CMD) in the Present State register
1407 // to be 0
1408 //
1409 PresentState = BIT0;
1410 }
1411
1412 PciIo = Private->PciIo;
1413 Status = SdMmcHcCheckMmioSet (
1414 PciIo,
1415 Trb->Slot,
1416 SD_MMC_HC_PRESENT_STATE,
1417 sizeof (PresentState),
1418 PresentState,
1419 0
1420 );
1421
1422 return Status;
1423 }
1424
1425 /**
1426 Wait for the env to be ready for execute specified TRB.
1427
1428 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1429 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1430
1431 @retval EFI_SUCCESS The env is ready for TRB execution.
1432 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1433 @retval Others Some erros happen.
1434
1435 **/
1436 EFI_STATUS
1437 SdMmcWaitTrbEnv (
1438 IN SD_MMC_HC_PRIVATE_DATA *Private,
1439 IN SD_MMC_HC_TRB *Trb
1440 )
1441 {
1442 EFI_STATUS Status;
1443 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1444 UINT64 Timeout;
1445 BOOLEAN InfiniteWait;
1446
1447 //
1448 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1449 //
1450 Packet = Trb->Packet;
1451 Timeout = Packet->Timeout;
1452 if (Timeout == 0) {
1453 InfiniteWait = TRUE;
1454 } else {
1455 InfiniteWait = FALSE;
1456 }
1457
1458 while (InfiniteWait || (Timeout > 0)) {
1459 //
1460 // Check Trb execution result by reading Normal Interrupt Status register.
1461 //
1462 Status = SdMmcCheckTrbEnv (Private, Trb);
1463 if (Status != EFI_NOT_READY) {
1464 return Status;
1465 }
1466 //
1467 // Stall for 1 microsecond.
1468 //
1469 gBS->Stall (1);
1470
1471 Timeout--;
1472 }
1473
1474 return EFI_TIMEOUT;
1475 }
1476
1477 /**
1478 Execute the specified TRB.
1479
1480 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1481 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1482
1483 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1484 @retval Others Some erros happen when sending this request to the host controller.
1485
1486 **/
1487 EFI_STATUS
1488 SdMmcExecTrb (
1489 IN SD_MMC_HC_PRIVATE_DATA *Private,
1490 IN SD_MMC_HC_TRB *Trb
1491 )
1492 {
1493 EFI_STATUS Status;
1494 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1495 EFI_PCI_IO_PROTOCOL *PciIo;
1496 UINT16 Cmd;
1497 UINT16 IntStatus;
1498 UINT32 Argument;
1499 UINT16 BlkCount;
1500 UINT16 BlkSize;
1501 UINT16 TransMode;
1502 UINT8 HostCtrl1;
1503 UINT32 SdmaAddr;
1504 UINT64 AdmaAddr;
1505
1506 Packet = Trb->Packet;
1507 PciIo = Trb->Private->PciIo;
1508 //
1509 // Clear all bits in Error Interrupt Status Register
1510 //
1511 IntStatus = 0xFFFF;
1512 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1513 if (EFI_ERROR (Status)) {
1514 return Status;
1515 }
1516 //
1517 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1518 //
1519 IntStatus = 0xFF3F;
1520 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1521 if (EFI_ERROR (Status)) {
1522 return Status;
1523 }
1524 //
1525 // Set Host Control 1 register DMA Select field
1526 //
1527 if (Trb->Mode == SdMmcAdmaMode) {
1528 HostCtrl1 = BIT4;
1529 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1530 if (EFI_ERROR (Status)) {
1531 return Status;
1532 }
1533 }
1534
1535 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1536
1537 if (Trb->Mode == SdMmcSdmaMode) {
1538 if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
1539 return EFI_INVALID_PARAMETER;
1540 }
1541
1542 SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
1543 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
1544 if (EFI_ERROR (Status)) {
1545 return Status;
1546 }
1547 } else if (Trb->Mode == SdMmcAdmaMode) {
1548 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1549 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1550 if (EFI_ERROR (Status)) {
1551 return Status;
1552 }
1553 }
1554
1555 BlkSize = Trb->BlockSize;
1556 if (Trb->Mode == SdMmcSdmaMode) {
1557 //
1558 // Set SDMA boundary to be 512K bytes.
1559 //
1560 BlkSize |= 0x7000;
1561 }
1562
1563 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1564 if (EFI_ERROR (Status)) {
1565 return Status;
1566 }
1567
1568 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
1569 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
1570 if (EFI_ERROR (Status)) {
1571 return Status;
1572 }
1573
1574 Argument = Packet->SdMmcCmdBlk->CommandArgument;
1575 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1576 if (EFI_ERROR (Status)) {
1577 return Status;
1578 }
1579
1580 TransMode = 0;
1581 if (Trb->Mode != SdMmcNoData) {
1582 if (Trb->Mode != SdMmcPioMode) {
1583 TransMode |= BIT0;
1584 }
1585 if (Trb->Read) {
1586 TransMode |= BIT4;
1587 }
1588 if (BlkCount != 0) {
1589 TransMode |= BIT5 | BIT1;
1590 }
1591 //
1592 // Only SD memory card needs to use AUTO CMD12 feature.
1593 //
1594 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
1595 if (BlkCount > 1) {
1596 TransMode |= BIT2;
1597 }
1598 }
1599 }
1600
1601 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1602 if (EFI_ERROR (Status)) {
1603 return Status;
1604 }
1605
1606 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
1607 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
1608 Cmd |= BIT5;
1609 }
1610 //
1611 // Convert ResponseType to value
1612 //
1613 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1614 switch (Packet->SdMmcCmdBlk->ResponseType) {
1615 case SdMmcResponseTypeR1:
1616 case SdMmcResponseTypeR5:
1617 case SdMmcResponseTypeR6:
1618 case SdMmcResponseTypeR7:
1619 Cmd |= (BIT1 | BIT3 | BIT4);
1620 break;
1621 case SdMmcResponseTypeR2:
1622 Cmd |= (BIT0 | BIT3);
1623 break;
1624 case SdMmcResponseTypeR3:
1625 case SdMmcResponseTypeR4:
1626 Cmd |= BIT1;
1627 break;
1628 case SdMmcResponseTypeR1b:
1629 case SdMmcResponseTypeR5b:
1630 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
1631 break;
1632 default:
1633 ASSERT (FALSE);
1634 break;
1635 }
1636 }
1637 //
1638 // Execute cmd
1639 //
1640 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
1641 return Status;
1642 }
1643
1644 /**
1645 Check the TRB execution result.
1646
1647 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1648 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1649
1650 @retval EFI_SUCCESS The TRB is executed successfully.
1651 @retval EFI_NOT_READY The TRB is not completed for execution.
1652 @retval Others Some erros happen when executing this request.
1653
1654 **/
1655 EFI_STATUS
1656 SdMmcCheckTrbResult (
1657 IN SD_MMC_HC_PRIVATE_DATA *Private,
1658 IN SD_MMC_HC_TRB *Trb
1659 )
1660 {
1661 EFI_STATUS Status;
1662 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1663 UINT16 IntStatus;
1664 UINT32 Response[4];
1665 UINT32 SdmaAddr;
1666 UINT8 Index;
1667 UINT8 SwReset;
1668
1669 SwReset = 0;
1670 Packet = Trb->Packet;
1671 //
1672 // Check Trb execution result by reading Normal Interrupt Status register.
1673 //
1674 Status = SdMmcHcRwMmio (
1675 Private->PciIo,
1676 Trb->Slot,
1677 SD_MMC_HC_NOR_INT_STS,
1678 TRUE,
1679 sizeof (IntStatus),
1680 &IntStatus
1681 );
1682 if (EFI_ERROR (Status)) {
1683 goto Done;
1684 }
1685 //
1686 // Check Transfer Complete bit is set or not.
1687 //
1688 if ((IntStatus & BIT1) == BIT1) {
1689 if ((IntStatus & BIT15) == BIT15) {
1690 //
1691 // Read Error Interrupt Status register to check if the error is
1692 // Data Timeout Error.
1693 // If yes, treat it as success as Transfer Complete has higher
1694 // priority than Data Timeout Error.
1695 //
1696 Status = SdMmcHcRwMmio (
1697 Private->PciIo,
1698 Trb->Slot,
1699 SD_MMC_HC_ERR_INT_STS,
1700 TRUE,
1701 sizeof (IntStatus),
1702 &IntStatus
1703 );
1704 if (!EFI_ERROR (Status)) {
1705 if ((IntStatus & BIT4) == BIT4) {
1706 Status = EFI_SUCCESS;
1707 } else {
1708 Status = EFI_DEVICE_ERROR;
1709 }
1710 }
1711 }
1712
1713 goto Done;
1714 }
1715 //
1716 // Check if there is a error happened during cmd execution.
1717 // If yes, then do error recovery procedure to follow SD Host Controller
1718 // Simplified Spec 3.0 section 3.10.1.
1719 //
1720 if ((IntStatus & BIT15) == BIT15) {
1721 Status = SdMmcHcRwMmio (
1722 Private->PciIo,
1723 Trb->Slot,
1724 SD_MMC_HC_ERR_INT_STS,
1725 TRUE,
1726 sizeof (IntStatus),
1727 &IntStatus
1728 );
1729 if (EFI_ERROR (Status)) {
1730 goto Done;
1731 }
1732 if ((IntStatus & 0x0F) != 0) {
1733 SwReset |= BIT1;
1734 }
1735 if ((IntStatus & 0xF0) != 0) {
1736 SwReset |= BIT2;
1737 }
1738
1739 Status = SdMmcHcRwMmio (
1740 Private->PciIo,
1741 Trb->Slot,
1742 SD_MMC_HC_SW_RST,
1743 FALSE,
1744 sizeof (SwReset),
1745 &SwReset
1746 );
1747 if (EFI_ERROR (Status)) {
1748 goto Done;
1749 }
1750 Status = SdMmcHcWaitMmioSet (
1751 Private->PciIo,
1752 Trb->Slot,
1753 SD_MMC_HC_SW_RST,
1754 sizeof (SwReset),
1755 0xFF,
1756 0,
1757 SD_MMC_HC_GENERIC_TIMEOUT
1758 );
1759 if (EFI_ERROR (Status)) {
1760 goto Done;
1761 }
1762
1763 Status = EFI_DEVICE_ERROR;
1764 goto Done;
1765 }
1766 //
1767 // Check if DMA interrupt is signalled for the SDMA transfer.
1768 //
1769 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
1770 //
1771 // Clear DMA interrupt bit.
1772 //
1773 IntStatus = BIT3;
1774 Status = SdMmcHcRwMmio (
1775 Private->PciIo,
1776 Trb->Slot,
1777 SD_MMC_HC_NOR_INT_STS,
1778 FALSE,
1779 sizeof (IntStatus),
1780 &IntStatus
1781 );
1782 if (EFI_ERROR (Status)) {
1783 goto Done;
1784 }
1785 //
1786 // Update SDMA Address register.
1787 //
1788 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
1789 Status = SdMmcHcRwMmio (
1790 Private->PciIo,
1791 Trb->Slot,
1792 SD_MMC_HC_SDMA_ADDR,
1793 FALSE,
1794 sizeof (UINT32),
1795 &SdmaAddr
1796 );
1797 if (EFI_ERROR (Status)) {
1798 goto Done;
1799 }
1800 Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
1801 }
1802
1803 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
1804 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
1805 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
1806 if ((IntStatus & BIT0) == BIT0) {
1807 Status = EFI_SUCCESS;
1808 goto Done;
1809 }
1810 }
1811
1812 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1813 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1814 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1815 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1816 //
1817 // While performing tuning procedure (Execute Tuning is set to 1),
1818 // Transfer Completeis not set to 1
1819 // Refer to SD Host Controller Simplified Specification 3.0 table 2-23 for details.
1820 //
1821 Status = EFI_SUCCESS;
1822 goto Done;
1823 }
1824
1825 Status = EFI_NOT_READY;
1826 Done:
1827 //
1828 // Get response data when the cmd is executed successfully.
1829 //
1830 if (!EFI_ERROR (Status)) {
1831 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1832 for (Index = 0; Index < 4; Index++) {
1833 Status = SdMmcHcRwMmio (
1834 Private->PciIo,
1835 Trb->Slot,
1836 SD_MMC_HC_RESPONSE + Index * 4,
1837 TRUE,
1838 sizeof (UINT32),
1839 &Response[Index]
1840 );
1841 if (EFI_ERROR (Status)) {
1842 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
1843 return Status;
1844 }
1845 }
1846 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
1847 }
1848 }
1849
1850 if (Status != EFI_NOT_READY) {
1851 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
1852 }
1853
1854 return Status;
1855 }
1856
1857 /**
1858 Wait for the TRB execution result.
1859
1860 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1861 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1862
1863 @retval EFI_SUCCESS The TRB is executed successfully.
1864 @retval Others Some erros happen when executing this request.
1865
1866 **/
1867 EFI_STATUS
1868 SdMmcWaitTrbResult (
1869 IN SD_MMC_HC_PRIVATE_DATA *Private,
1870 IN SD_MMC_HC_TRB *Trb
1871 )
1872 {
1873 EFI_STATUS Status;
1874 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1875 UINT64 Timeout;
1876 BOOLEAN InfiniteWait;
1877
1878 Packet = Trb->Packet;
1879 //
1880 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1881 //
1882 Timeout = Packet->Timeout;
1883 if (Timeout == 0) {
1884 InfiniteWait = TRUE;
1885 } else {
1886 InfiniteWait = FALSE;
1887 }
1888
1889 while (InfiniteWait || (Timeout > 0)) {
1890 //
1891 // Check Trb execution result by reading Normal Interrupt Status register.
1892 //
1893 Status = SdMmcCheckTrbResult (Private, Trb);
1894 if (Status != EFI_NOT_READY) {
1895 return Status;
1896 }
1897 //
1898 // Stall for 1 microsecond.
1899 //
1900 gBS->Stall (1);
1901
1902 Timeout--;
1903 }
1904
1905 return EFI_TIMEOUT;
1906 }
1907
EFI Development Kit II mirror for PVE