2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
7 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include "SdMmcPciHcDxe.h"
21 Dump the content of SD/MMC host controller's Capability Register.
23 @param[in] Slot The slot number of the SD card to send the command to.
24 @param[in] Capability The buffer to store the capability data.
30 IN SD_MMC_HC_SLOT_CAP
*Capability
34 // Dump Capability Data
36 DEBUG ((EFI_D_INFO
, " == Slot [%d] Capability is 0x%x ==\n", Slot
, Capability
));
37 DEBUG ((EFI_D_INFO
, " Timeout Clk Freq %d%a\n", Capability
->TimeoutFreq
, (Capability
->TimeoutUnit
) ? "MHz" : "KHz"));
38 DEBUG ((EFI_D_INFO
, " Base Clk Freq %dMHz\n", Capability
->BaseClkFreq
));
39 DEBUG ((EFI_D_INFO
, " Max Blk Len %dbytes\n", 512 * (1 << Capability
->MaxBlkLen
)));
40 DEBUG ((EFI_D_INFO
, " 8-bit Support %a\n", Capability
->BusWidth8
? "TRUE" : "FALSE"));
41 DEBUG ((EFI_D_INFO
, " ADMA2 Support %a\n", Capability
->Adma2
? "TRUE" : "FALSE"));
42 DEBUG ((EFI_D_INFO
, " HighSpeed Support %a\n", Capability
->HighSpeed
? "TRUE" : "FALSE"));
43 DEBUG ((EFI_D_INFO
, " SDMA Support %a\n", Capability
->Sdma
? "TRUE" : "FALSE"));
44 DEBUG ((EFI_D_INFO
, " Suspend/Resume %a\n", Capability
->SuspRes
? "TRUE" : "FALSE"));
45 DEBUG ((EFI_D_INFO
, " Voltage 3.3 %a\n", Capability
->Voltage33
? "TRUE" : "FALSE"));
46 DEBUG ((EFI_D_INFO
, " Voltage 3.0 %a\n", Capability
->Voltage30
? "TRUE" : "FALSE"));
47 DEBUG ((EFI_D_INFO
, " Voltage 1.8 %a\n", Capability
->Voltage18
? "TRUE" : "FALSE"));
48 DEBUG ((EFI_D_INFO
, " 64-bit Sys Bus %a\n", Capability
->SysBus64
? "TRUE" : "FALSE"));
49 DEBUG ((EFI_D_INFO
, " Async Interrupt %a\n", Capability
->AsyncInt
? "TRUE" : "FALSE"));
50 DEBUG ((EFI_D_INFO
, " SlotType "));
51 if (Capability
->SlotType
== 0x00) {
52 DEBUG ((EFI_D_INFO
, "%a\n", "Removable Slot"));
53 } else if (Capability
->SlotType
== 0x01) {
54 DEBUG ((EFI_D_INFO
, "%a\n", "Embedded Slot"));
55 } else if (Capability
->SlotType
== 0x02) {
56 DEBUG ((EFI_D_INFO
, "%a\n", "Shared Bus Slot"));
58 DEBUG ((EFI_D_INFO
, "%a\n", "Reserved"));
60 DEBUG ((EFI_D_INFO
, " SDR50 Support %a\n", Capability
->Sdr50
? "TRUE" : "FALSE"));
61 DEBUG ((EFI_D_INFO
, " SDR104 Support %a\n", Capability
->Sdr104
? "TRUE" : "FALSE"));
62 DEBUG ((EFI_D_INFO
, " DDR50 Support %a\n", Capability
->Ddr50
? "TRUE" : "FALSE"));
63 DEBUG ((EFI_D_INFO
, " Driver Type A %a\n", Capability
->DriverTypeA
? "TRUE" : "FALSE"));
64 DEBUG ((EFI_D_INFO
, " Driver Type C %a\n", Capability
->DriverTypeC
? "TRUE" : "FALSE"));
65 DEBUG ((EFI_D_INFO
, " Driver Type D %a\n", Capability
->DriverTypeD
? "TRUE" : "FALSE"));
66 DEBUG ((EFI_D_INFO
, " Driver Type 4 %a\n", Capability
->DriverType4
? "TRUE" : "FALSE"));
67 if (Capability
->TimerCount
== 0) {
68 DEBUG ((EFI_D_INFO
, " Retuning TimerCnt Disabled\n", 2 * (Capability
->TimerCount
- 1)));
70 DEBUG ((EFI_D_INFO
, " Retuning TimerCnt %dseconds\n", 2 * (Capability
->TimerCount
- 1)));
72 DEBUG ((EFI_D_INFO
, " SDR50 Tuning %a\n", Capability
->TuningSDR50
? "TRUE" : "FALSE"));
73 DEBUG ((EFI_D_INFO
, " Retuning Mode Mode %d\n", Capability
->RetuningMod
+ 1));
74 DEBUG ((EFI_D_INFO
, " Clock Multiplier M = %d\n", Capability
->ClkMultiplier
+ 1));
75 DEBUG ((EFI_D_INFO
, " HS 400 %a\n", Capability
->Hs400
? "TRUE" : "FALSE"));
80 Read SlotInfo register from SD/MMC host controller pci config space.
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
93 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
99 SD_MMC_HC_SLOT_INFO SlotInfo
;
101 Status
= PciIo
->Pci
.Read (
104 SD_MMC_HC_SLOT_OFFSET
,
108 if (EFI_ERROR (Status
)) {
112 *FirstBar
= SlotInfo
.FirstBar
;
113 *SlotNum
= SlotInfo
.SlotNum
+ 1;
114 ASSERT ((*FirstBar
+ *SlotNum
) < SD_MMC_HC_MAX_SLOT
);
119 Read/Write specified SD/MMC host controller mmio register.
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
144 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
154 if ((PciIo
== NULL
) || (Data
== NULL
)) {
155 return EFI_INVALID_PARAMETER
;
158 if ((Count
!= 1) && (Count
!= 2) && (Count
!= 4) && (Count
!= 8)) {
159 return EFI_INVALID_PARAMETER
;
163 Status
= PciIo
->Mem
.Read (
172 Status
= PciIo
->Mem
.Write (
186 Do OR operation with the value of the specified SD/MMC host controller mmio register.
188 @param[in] PciIo The PCI IO protocol instance.
189 @param[in] BarIndex The BAR index of the standard PCI Configuration
190 header to use as the base address for the memory
191 operation to perform.
192 @param[in] Offset The offset within the selected BAR to start the
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2 , 4 or 8 bytes.
196 @param[in] OrData The pointer to the data used to do OR operation.
197 The caller is responsible for having ownership of
198 the data buffer and ensuring its size not less than
201 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
202 @retval EFI_SUCCESS The OR operation succeeds.
203 @retval Others The OR operation fails.
209 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
220 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
221 if (EFI_ERROR (Status
)) {
226 Or
= *(UINT8
*) OrData
;
227 } else if (Count
== 2) {
228 Or
= *(UINT16
*) OrData
;
229 } else if (Count
== 4) {
230 Or
= *(UINT32
*) OrData
;
231 } else if (Count
== 8) {
232 Or
= *(UINT64
*) OrData
;
234 return EFI_INVALID_PARAMETER
;
238 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
244 Do AND operation with the value of the specified SD/MMC host controller mmio register.
246 @param[in] PciIo The PCI IO protocol instance.
247 @param[in] BarIndex The BAR index of the standard PCI Configuration
248 header to use as the base address for the memory
249 operation to perform.
250 @param[in] Offset The offset within the selected BAR to start the
252 @param[in] Count The width of the mmio register in bytes.
253 Must be 1, 2 , 4 or 8 bytes.
254 @param[in] AndData The pointer to the data used to do AND operation.
255 The caller is responsible for having ownership of
256 the data buffer and ensuring its size not less than
259 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
260 @retval EFI_SUCCESS The AND operation succeeds.
261 @retval Others The AND operation fails.
267 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
278 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
279 if (EFI_ERROR (Status
)) {
284 And
= *(UINT8
*) AndData
;
285 } else if (Count
== 2) {
286 And
= *(UINT16
*) AndData
;
287 } else if (Count
== 4) {
288 And
= *(UINT32
*) AndData
;
289 } else if (Count
== 8) {
290 And
= *(UINT64
*) AndData
;
292 return EFI_INVALID_PARAMETER
;
296 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
302 Wait for the value of the specified MMIO register set to the test value.
304 @param[in] PciIo The PCI IO protocol instance.
305 @param[in] BarIndex The BAR index of the standard PCI Configuration
306 header to use as the base address for the memory
307 operation to perform.
308 @param[in] Offset The offset within the selected BAR to start the
310 @param[in] Count The width of the mmio register in bytes.
311 Must be 1, 2, 4 or 8 bytes.
312 @param[in] MaskValue The mask value of memory.
313 @param[in] TestValue The test value of memory.
315 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
316 @retval EFI_SUCCESS The MMIO register has expected value.
317 @retval Others The MMIO operation fails.
322 SdMmcHcCheckMmioSet (
323 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
335 // Access PCI MMIO space to see if the value is the tested one.
338 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Value
);
339 if (EFI_ERROR (Status
)) {
345 if (Value
== TestValue
) {
349 return EFI_NOT_READY
;
353 Wait for the value of the specified MMIO register set to the test value.
355 @param[in] PciIo The PCI IO protocol instance.
356 @param[in] BarIndex The BAR index of the standard PCI Configuration
357 header to use as the base address for the memory
358 operation to perform.
359 @param[in] Offset The offset within the selected BAR to start the
361 @param[in] Count The width of the mmio register in bytes.
362 Must be 1, 2, 4 or 8 bytes.
363 @param[in] MaskValue The mask value of memory.
364 @param[in] TestValue The test value of memory.
365 @param[in] Timeout The time out value for wait memory set, uses 1
366 microsecond as a unit.
368 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
370 @retval EFI_SUCCESS The MMIO register has expected value.
371 @retval Others The MMIO operation fails.
377 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
387 BOOLEAN InfiniteWait
;
392 InfiniteWait
= FALSE
;
395 while (InfiniteWait
|| (Timeout
> 0)) {
396 Status
= SdMmcHcCheckMmioSet (
404 if (Status
!= EFI_NOT_READY
) {
409 // Stall for 1 microsecond.
420 Software reset the specified SD/MMC host controller and enable all interrupts.
422 @param[in] PciIo The PCI IO protocol instance.
423 @param[in] Slot The slot number of the SD card to send the command to.
425 @retval EFI_SUCCESS The software reset executes successfully.
426 @retval Others The software reset fails.
431 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
439 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_SW_RST
, FALSE
, sizeof (SwReset
), &SwReset
);
441 if (EFI_ERROR (Status
)) {
442 DEBUG ((EFI_D_ERROR
, "SdMmcHcReset: write full 1 fails: %r\n", Status
));
446 Status
= SdMmcHcWaitMmioSet (
453 SD_MMC_HC_GENERIC_TIMEOUT
455 if (EFI_ERROR (Status
)) {
456 DEBUG ((EFI_D_INFO
, "SdMmcHcReset: reset done with %r\n", Status
));
460 // Enable all interrupt after reset all.
462 Status
= SdMmcHcEnableInterrupt (PciIo
, Slot
);
468 Set all interrupt status bits in Normal and Error Interrupt Status Enable
471 @param[in] PciIo The PCI IO protocol instance.
472 @param[in] Slot The slot number of the SD card to send the command to.
474 @retval EFI_SUCCESS The operation executes successfully.
475 @retval Others The operation fails.
479 SdMmcHcEnableInterrupt (
480 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
488 // Enable all bits in Error Interrupt Status Enable Register
491 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_ERR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
492 if (EFI_ERROR (Status
)) {
496 // Enable all bits in Normal Interrupt Status Enable Register
499 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
505 Get the capability data from the specified slot.
507 @param[in] PciIo The PCI IO protocol instance.
508 @param[in] Slot The slot number of the SD card to send the command to.
509 @param[out] Capability The buffer to store the capability data.
511 @retval EFI_SUCCESS The operation executes successfully.
512 @retval Others The operation fails.
516 SdMmcHcGetCapability (
517 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
519 OUT SD_MMC_HC_SLOT_CAP
*Capability
525 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CAP
, TRUE
, sizeof (Cap
), &Cap
);
526 if (EFI_ERROR (Status
)) {
530 CopyMem (Capability
, &Cap
, sizeof (Cap
));
536 Get the maximum current capability data from the specified slot.
538 @param[in] PciIo The PCI IO protocol instance.
539 @param[in] Slot The slot number of the SD card to send the command to.
540 @param[out] MaxCurrent The buffer to store the maximum current capability data.
542 @retval EFI_SUCCESS The operation executes successfully.
543 @retval Others The operation fails.
547 SdMmcHcGetMaxCurrent (
548 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
550 OUT UINT64
*MaxCurrent
555 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_MAX_CURRENT_CAP
, TRUE
, sizeof (UINT64
), MaxCurrent
);
561 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
564 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
566 @param[in] PciIo The PCI IO protocol instance.
567 @param[in] Slot The slot number of the SD card to send the command to.
568 @param[out] MediaPresent The pointer to the media present boolean value.
570 @retval EFI_SUCCESS There is no media change happened.
571 @retval EFI_MEDIA_CHANGED There is media change happened.
572 @retval Others The detection fails.
577 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
579 OUT BOOLEAN
*MediaPresent
587 // Check Present State Register to see if there is a card presented.
589 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_PRESENT_STATE
, TRUE
, sizeof (PresentState
), &PresentState
);
590 if (EFI_ERROR (Status
)) {
594 if ((PresentState
& BIT16
) != 0) {
595 *MediaPresent
= TRUE
;
597 *MediaPresent
= FALSE
;
601 // Check Normal Interrupt Status Register
603 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, TRUE
, sizeof (Data
), &Data
);
604 if (EFI_ERROR (Status
)) {
608 if ((Data
& (BIT6
| BIT7
)) != 0) {
610 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
613 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data
), &Data
);
614 if (EFI_ERROR (Status
)) {
618 return EFI_MEDIA_CHANGED
;
625 Stop SD/MMC card clock.
627 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
629 @param[in] PciIo The PCI IO protocol instance.
630 @param[in] Slot The slot number of the SD card to send the command to.
632 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
633 @retval Others Fail to stop SD/MMC clock.
638 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
647 // Ensure no SD transactions are occurring on the SD Bus by
648 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
649 // in the Present State register to be 0.
651 Status
= SdMmcHcWaitMmioSet (
654 SD_MMC_HC_PRESENT_STATE
,
655 sizeof (PresentState
),
658 SD_MMC_HC_GENERIC_TIMEOUT
660 if (EFI_ERROR (Status
)) {
665 // Set SD Clock Enable in the Clock Control register to 0
667 ClockCtrl
= (UINT16
)~BIT2
;
668 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
674 SD/MMC card clock supply.
676 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
678 @param[in] PciIo The PCI IO protocol instance.
679 @param[in] Slot The slot number of the SD card to send the command to.
680 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
681 @param[in] Capability The capability of the slot.
683 @retval EFI_SUCCESS The clock is supplied successfully.
684 @retval Others The clock isn't supplied successfully.
689 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
692 IN SD_MMC_HC_SLOT_CAP Capability
700 UINT16 ControllerVer
;
704 // Calculate a divisor for SD clock frequency
706 ASSERT (Capability
.BaseClkFreq
!= 0);
708 BaseClkFreq
= Capability
.BaseClkFreq
;
709 if ((ClockFreq
> (BaseClkFreq
* 1000)) || (ClockFreq
== 0)) {
710 return EFI_INVALID_PARAMETER
;
713 // Calculate the divisor of base frequency.
716 SettingFreq
= BaseClkFreq
* 1000;
717 while (ClockFreq
< SettingFreq
) {
720 SettingFreq
= (BaseClkFreq
* 1000) / (2 * Divisor
);
721 Remainder
= (BaseClkFreq
* 1000) % (2 * Divisor
);
722 if ((ClockFreq
== SettingFreq
) && (Remainder
== 0)) {
725 if ((ClockFreq
== SettingFreq
) && (Remainder
!= 0)) {
730 DEBUG ((EFI_D_INFO
, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq
, Divisor
, ClockFreq
));
732 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CTRL_VER
, TRUE
, sizeof (ControllerVer
), &ControllerVer
);
733 if (EFI_ERROR (Status
)) {
737 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
739 if ((ControllerVer
& 0xFF) == 2) {
740 ASSERT (Divisor
<= 0x3FF);
741 ClockCtrl
= ((Divisor
& 0xFF) << 8) | ((Divisor
& 0x300) >> 2);
742 } else if (((ControllerVer
& 0xFF) == 0) || ((ControllerVer
& 0xFF) == 1)) {
744 // Only the most significant bit can be used as divisor.
746 if (((Divisor
- 1) & Divisor
) != 0) {
747 Divisor
= 1 << (HighBitSet32 (Divisor
) + 1);
749 ASSERT (Divisor
<= 0x80);
750 ClockCtrl
= (Divisor
& 0xFF) << 8;
752 DEBUG ((EFI_D_ERROR
, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer
));
753 return EFI_UNSUPPORTED
;
757 // Stop bus clock at first
759 Status
= SdMmcHcStopClock (PciIo
, Slot
);
760 if (EFI_ERROR (Status
)) {
765 // Supply clock frequency with specified divisor
768 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, FALSE
, sizeof (ClockCtrl
), &ClockCtrl
);
769 if (EFI_ERROR (Status
)) {
770 DEBUG ((EFI_D_ERROR
, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
775 // Wait Internal Clock Stable in the Clock Control register to be 1
777 Status
= SdMmcHcWaitMmioSet (
780 SD_MMC_HC_CLOCK_CTRL
,
784 SD_MMC_HC_GENERIC_TIMEOUT
786 if (EFI_ERROR (Status
)) {
791 // Set SD Clock Enable in the Clock Control register to 1
794 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
800 SD/MMC bus power control.
802 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
804 @param[in] PciIo The PCI IO protocol instance.
805 @param[in] Slot The slot number of the SD card to send the command to.
806 @param[in] PowerCtrl The value setting to the power control register.
808 @retval TRUE There is a SD/MMC card attached.
809 @retval FALSE There is no a SD/MMC card attached.
813 SdMmcHcPowerControl (
814 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
824 PowerCtrl
&= (UINT8
)~BIT0
;
825 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
826 if (EFI_ERROR (Status
)) {
831 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
834 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
840 Set the SD/MMC bus width.
842 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
844 @param[in] PciIo The PCI IO protocol instance.
845 @param[in] Slot The slot number of the SD card to send the command to.
846 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
848 @retval EFI_SUCCESS The bus width is set successfully.
849 @retval Others The bus width isn't set successfully.
854 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
863 HostCtrl1
= (UINT8
)~(BIT5
| BIT1
);
864 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
865 } else if (BusWidth
== 4) {
866 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
867 if (EFI_ERROR (Status
)) {
871 HostCtrl1
&= (UINT8
)~BIT5
;
872 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
873 } else if (BusWidth
== 8) {
874 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
875 if (EFI_ERROR (Status
)) {
878 HostCtrl1
&= (UINT8
)~BIT1
;
880 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
883 return EFI_INVALID_PARAMETER
;
890 Supply SD/MMC card with lowest clock frequency at initialization.
892 @param[in] PciIo The PCI IO protocol instance.
893 @param[in] Slot The slot number of the SD card to send the command to.
894 @param[in] Capability The capability of the slot.
896 @retval EFI_SUCCESS The clock is supplied successfully.
897 @retval Others The clock isn't supplied successfully.
901 SdMmcHcInitClockFreq (
902 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
904 IN SD_MMC_HC_SLOT_CAP Capability
911 // Calculate a divisor for SD clock frequency
913 if (Capability
.BaseClkFreq
== 0) {
915 // Don't support get Base Clock Frequency information via another method
917 return EFI_UNSUPPORTED
;
920 // Supply 400KHz clock frequency at initialization phase.
923 Status
= SdMmcHcClockSupply (PciIo
, Slot
, InitFreq
, Capability
);
928 Supply SD/MMC card with maximum voltage at initialization.
930 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
932 @param[in] PciIo The PCI IO protocol instance.
933 @param[in] Slot The slot number of the SD card to send the command to.
934 @param[in] Capability The capability of the slot.
936 @retval EFI_SUCCESS The voltage is supplied successfully.
937 @retval Others The voltage isn't supplied successfully.
941 SdMmcHcInitPowerVoltage (
942 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
944 IN SD_MMC_HC_SLOT_CAP Capability
952 // Calculate supported maximum voltage according to SD Bus Voltage Select
954 if (Capability
.Voltage33
!= 0) {
959 } else if (Capability
.Voltage30
!= 0) {
964 } else if (Capability
.Voltage18
!= 0) {
970 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
972 if (EFI_ERROR (Status
)) {
977 return EFI_DEVICE_ERROR
;
981 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
983 Status
= SdMmcHcPowerControl (PciIo
, Slot
, MaxVoltage
);
989 Initialize the Timeout Control register with most conservative value at initialization.
991 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
993 @param[in] PciIo The PCI IO protocol instance.
994 @param[in] Slot The slot number of the SD card to send the command to.
996 @retval EFI_SUCCESS The timeout control register is configured successfully.
997 @retval Others The timeout control register isn't configured successfully.
1001 SdMmcHcInitTimeoutCtrl (
1002 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1010 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_TIMEOUT_CTRL
, FALSE
, sizeof (Timeout
), &Timeout
);
1016 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1019 @param[in] PciIo The PCI IO protocol instance.
1020 @param[in] Slot The slot number of the SD card to send the command to.
1021 @param[in] Capability The capability of the slot.
1023 @retval EFI_SUCCESS The host controller is initialized successfully.
1024 @retval Others The host controller isn't initialized successfully.
1029 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1031 IN SD_MMC_HC_SLOT_CAP Capability
1036 Status
= SdMmcHcInitClockFreq (PciIo
, Slot
, Capability
);
1037 if (EFI_ERROR (Status
)) {
1041 Status
= SdMmcHcInitPowerVoltage (PciIo
, Slot
, Capability
);
1042 if (EFI_ERROR (Status
)) {
1046 Status
= SdMmcHcInitTimeoutCtrl (PciIo
, Slot
);
1053 @param[in] PciIo The PCI IO protocol instance.
1054 @param[in] Slot The slot number of the SD card to send the command to.
1055 @param[in] On The boolean to turn on/off LED.
1057 @retval EFI_SUCCESS The LED is turned on/off successfully.
1058 @retval Others The LED isn't turned on/off successfully.
1063 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1073 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1075 HostCtrl1
= (UINT8
)~BIT0
;
1076 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1083 Build ADMA descriptor table for transfer.
1085 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
1087 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1089 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1090 @retval Others The ADMA descriptor table isn't created successfully.
1094 BuildAdmaDescTable (
1095 IN SD_MMC_HC_TRB
*Trb
1098 EFI_PHYSICAL_ADDRESS Data
;
1105 EFI_PCI_IO_PROTOCOL
*PciIo
;
1109 Data
= Trb
->DataPhy
;
1110 DataLen
= Trb
->DataLen
;
1111 PciIo
= Trb
->Private
->PciIo
;
1113 // Only support 32bit ADMA Descriptor Table
1115 if ((Data
>= 0x100000000ul
) || ((Data
+ DataLen
) > 0x100000000ul
)) {
1116 return EFI_INVALID_PARAMETER
;
1119 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1120 // for 32-bit address descriptor table.
1122 if ((Data
& (BIT0
| BIT1
)) != 0) {
1123 DEBUG ((EFI_D_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data
));
1126 Entries
= DivU64x32 ((DataLen
+ ADMA_MAX_DATA_PER_LINE
- 1), ADMA_MAX_DATA_PER_LINE
);
1127 TableSize
= (UINTN
)MultU64x32 (Entries
, sizeof (SD_MMC_HC_ADMA_DESC_LINE
));
1128 Trb
->AdmaPages
= (UINT32
)EFI_SIZE_TO_PAGES (TableSize
);
1129 Status
= PciIo
->AllocateBuffer (
1132 EfiBootServicesData
,
1133 EFI_SIZE_TO_PAGES (TableSize
),
1134 (VOID
**)&Trb
->AdmaDesc
,
1137 if (EFI_ERROR (Status
)) {
1138 return EFI_OUT_OF_RESOURCES
;
1140 ZeroMem (Trb
->AdmaDesc
, TableSize
);
1142 Status
= PciIo
->Map (
1144 EfiPciIoOperationBusMasterCommonBuffer
,
1151 if (EFI_ERROR (Status
) || (Bytes
!= TableSize
)) {
1153 // Map error or unable to map the whole RFis buffer into a contiguous region.
1157 EFI_SIZE_TO_PAGES (TableSize
),
1160 return EFI_OUT_OF_RESOURCES
;
1163 if ((UINT64
)(UINTN
)Trb
->AdmaDescPhy
> 0x100000000ul
) {
1165 // The ADMA doesn't support 64bit addressing.
1173 EFI_SIZE_TO_PAGES (TableSize
),
1176 return EFI_DEVICE_ERROR
;
1179 Remaining
= DataLen
;
1180 Address
= (UINT32
)Data
;
1181 for (Index
= 0; Index
< Entries
; Index
++) {
1182 if (Remaining
<= ADMA_MAX_DATA_PER_LINE
) {
1183 Trb
->AdmaDesc
[Index
].Valid
= 1;
1184 Trb
->AdmaDesc
[Index
].Act
= 2;
1185 Trb
->AdmaDesc
[Index
].Length
= (UINT16
)Remaining
;
1186 Trb
->AdmaDesc
[Index
].Address
= Address
;
1189 Trb
->AdmaDesc
[Index
].Valid
= 1;
1190 Trb
->AdmaDesc
[Index
].Act
= 2;
1191 Trb
->AdmaDesc
[Index
].Length
= 0;
1192 Trb
->AdmaDesc
[Index
].Address
= Address
;
1195 Remaining
-= ADMA_MAX_DATA_PER_LINE
;
1196 Address
+= ADMA_MAX_DATA_PER_LINE
;
1200 // Set the last descriptor line as end of descriptor table
1202 Trb
->AdmaDesc
[Index
].End
= 1;
1207 Create a new TRB for the SD/MMC cmd request.
1209 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1210 @param[in] Slot The slot number of the SD card to send the command to.
1211 @param[in] Packet A pointer to the SD command data structure.
1212 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1213 not NULL, then nonblocking I/O is performed, and Event
1214 will be signaled when the Packet completes.
1216 @return Created Trb or NULL.
1221 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1223 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
,
1230 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
1231 EFI_PCI_IO_PROTOCOL
*PciIo
;
1234 Trb
= AllocateZeroPool (sizeof (SD_MMC_HC_TRB
));
1239 Trb
->Signature
= SD_MMC_HC_TRB_SIG
;
1241 Trb
->BlockSize
= 0x200;
1242 Trb
->Packet
= Packet
;
1244 Trb
->Started
= FALSE
;
1245 Trb
->Timeout
= Packet
->Timeout
;
1246 Trb
->Private
= Private
;
1248 if ((Packet
->InTransferLength
!= 0) && (Packet
->InDataBuffer
!= NULL
)) {
1249 Trb
->Data
= Packet
->InDataBuffer
;
1250 Trb
->DataLen
= Packet
->InTransferLength
;
1252 } else if ((Packet
->OutTransferLength
!= 0) && (Packet
->OutDataBuffer
!= NULL
)) {
1253 Trb
->Data
= Packet
->OutDataBuffer
;
1254 Trb
->DataLen
= Packet
->OutTransferLength
;
1256 } else if ((Packet
->InTransferLength
== 0) && (Packet
->OutTransferLength
== 0)) {
1264 Flag
= EfiPciIoOperationBusMasterWrite
;
1266 Flag
= EfiPciIoOperationBusMasterRead
;
1269 PciIo
= Private
->PciIo
;
1270 if (Trb
->DataLen
!= 0) {
1271 MapLength
= Trb
->DataLen
;
1272 Status
= PciIo
->Map (
1280 if (EFI_ERROR (Status
) || (Trb
->DataLen
!= MapLength
)) {
1281 Status
= EFI_BAD_BUFFER_SIZE
;
1286 if ((Trb
->DataLen
% Trb
->BlockSize
) != 0) {
1287 if (Trb
->DataLen
< Trb
->BlockSize
) {
1288 Trb
->BlockSize
= (UINT16
)Trb
->DataLen
;
1292 if (Trb
->DataLen
== 0) {
1293 Trb
->Mode
= SdMmcNoData
;
1294 } else if (Private
->Capability
[Slot
].Adma2
!= 0) {
1295 Trb
->Mode
= SdMmcAdmaMode
;
1296 Status
= BuildAdmaDescTable (Trb
);
1297 if (EFI_ERROR (Status
)) {
1298 PciIo
->Unmap (PciIo
, Trb
->DataMap
);
1301 } else if (Private
->Capability
[Slot
].Sdma
!= 0) {
1302 Trb
->Mode
= SdMmcSdmaMode
;
1304 Trb
->Mode
= SdMmcPioMode
;
1307 if (Event
!= NULL
) {
1308 OldTpl
= gBS
->RaiseTPL (TPL_CALLBACK
);
1309 InsertTailList (&Private
->Queue
, &Trb
->TrbList
);
1310 gBS
->RestoreTPL (OldTpl
);
1321 Free the resource used by the TRB.
1323 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1328 IN SD_MMC_HC_TRB
*Trb
1331 EFI_PCI_IO_PROTOCOL
*PciIo
;
1333 PciIo
= Trb
->Private
->PciIo
;
1335 if (Trb
->AdmaMap
!= NULL
) {
1341 if (Trb
->AdmaDesc
!= NULL
) {
1348 if (Trb
->DataMap
!= NULL
) {
1359 Check if the env is ready for execute specified TRB.
1361 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1362 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1364 @retval EFI_SUCCESS The env is ready for TRB execution.
1365 @retval EFI_NOT_READY The env is not ready for TRB execution.
1366 @retval Others Some erros happen.
1371 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1372 IN SD_MMC_HC_TRB
*Trb
1376 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1377 EFI_PCI_IO_PROTOCOL
*PciIo
;
1378 UINT32 PresentState
;
1380 Packet
= Trb
->Packet
;
1382 if ((Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) ||
1383 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR1b
) ||
1384 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR5b
)) {
1386 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1387 // the Present State register to be 0
1389 PresentState
= BIT0
| BIT1
;
1391 // For Send Tuning Block cmd, just wait for Command Inhibit (CMD) to be 0
1393 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1394 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1395 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1396 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1397 PresentState
= BIT0
;
1401 // Wait Command Inhibit (CMD) in the Present State register
1404 PresentState
= BIT0
;
1407 PciIo
= Private
->PciIo
;
1408 Status
= SdMmcHcCheckMmioSet (
1411 SD_MMC_HC_PRESENT_STATE
,
1412 sizeof (PresentState
),
1421 Wait for the env to be ready for execute specified TRB.
1423 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1424 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1426 @retval EFI_SUCCESS The env is ready for TRB execution.
1427 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1428 @retval Others Some erros happen.
1433 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1434 IN SD_MMC_HC_TRB
*Trb
1438 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1440 BOOLEAN InfiniteWait
;
1443 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1445 Packet
= Trb
->Packet
;
1446 Timeout
= Packet
->Timeout
;
1448 InfiniteWait
= TRUE
;
1450 InfiniteWait
= FALSE
;
1453 while (InfiniteWait
|| (Timeout
> 0)) {
1455 // Check Trb execution result by reading Normal Interrupt Status register.
1457 Status
= SdMmcCheckTrbEnv (Private
, Trb
);
1458 if (Status
!= EFI_NOT_READY
) {
1462 // Stall for 1 microsecond.
1473 Execute the specified TRB.
1475 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1476 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1478 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1479 @retval Others Some erros happen when sending this request to the host controller.
1484 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1485 IN SD_MMC_HC_TRB
*Trb
1489 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1490 EFI_PCI_IO_PROTOCOL
*PciIo
;
1501 Packet
= Trb
->Packet
;
1502 PciIo
= Trb
->Private
->PciIo
;
1504 // Clear all bits in Error Interrupt Status Register
1507 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ERR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1508 if (EFI_ERROR (Status
)) {
1512 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1515 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1516 if (EFI_ERROR (Status
)) {
1520 // Set Host Control 1 register DMA Select field
1522 if (Trb
->Mode
== SdMmcAdmaMode
) {
1524 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1525 if (EFI_ERROR (Status
)) {
1530 SdMmcHcLedOnOff (PciIo
, Trb
->Slot
, TRUE
);
1532 if (Trb
->Mode
== SdMmcSdmaMode
) {
1533 if ((UINT64
)(UINTN
)Trb
->DataPhy
>= 0x100000000ul
) {
1534 return EFI_INVALID_PARAMETER
;
1537 SdmaAddr
= (UINT32
)(UINTN
)Trb
->DataPhy
;
1538 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (SdmaAddr
), &SdmaAddr
);
1539 if (EFI_ERROR (Status
)) {
1542 } else if (Trb
->Mode
== SdMmcAdmaMode
) {
1543 AdmaAddr
= (UINT64
)(UINTN
)Trb
->AdmaDescPhy
;
1544 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (AdmaAddr
), &AdmaAddr
);
1545 if (EFI_ERROR (Status
)) {
1550 BlkSize
= Trb
->BlockSize
;
1551 if (Trb
->Mode
== SdMmcSdmaMode
) {
1553 // Set SDMA boundary to be 512K bytes.
1558 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_SIZE
, FALSE
, sizeof (BlkSize
), &BlkSize
);
1559 if (EFI_ERROR (Status
)) {
1563 BlkCount
= (UINT16
)(Trb
->DataLen
/ Trb
->BlockSize
);
1564 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_COUNT
, FALSE
, sizeof (BlkCount
), &BlkCount
);
1565 if (EFI_ERROR (Status
)) {
1569 Argument
= Packet
->SdMmcCmdBlk
->CommandArgument
;
1570 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ARG1
, FALSE
, sizeof (Argument
), &Argument
);
1571 if (EFI_ERROR (Status
)) {
1576 if (Trb
->Mode
!= SdMmcNoData
) {
1577 if (Trb
->Mode
!= SdMmcPioMode
) {
1583 if (BlkCount
!= 0) {
1584 TransMode
|= BIT5
| BIT1
;
1587 // Only SD memory card needs to use AUTO CMD12 feature.
1589 if (Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) {
1596 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_TRANS_MOD
, FALSE
, sizeof (TransMode
), &TransMode
);
1597 if (EFI_ERROR (Status
)) {
1601 Cmd
= (UINT16
)LShiftU64(Packet
->SdMmcCmdBlk
->CommandIndex
, 8);
1602 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) {
1606 // Convert ResponseType to value
1608 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
1609 switch (Packet
->SdMmcCmdBlk
->ResponseType
) {
1610 case SdMmcResponseTypeR1
:
1611 case SdMmcResponseTypeR5
:
1612 case SdMmcResponseTypeR6
:
1613 case SdMmcResponseTypeR7
:
1614 Cmd
|= (BIT1
| BIT3
| BIT4
);
1616 case SdMmcResponseTypeR2
:
1617 Cmd
|= (BIT0
| BIT3
);
1619 case SdMmcResponseTypeR3
:
1620 case SdMmcResponseTypeR4
:
1623 case SdMmcResponseTypeR1b
:
1624 case SdMmcResponseTypeR5b
:
1625 Cmd
|= (BIT0
| BIT1
| BIT3
| BIT4
);
1635 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_COMMAND
, FALSE
, sizeof (Cmd
), &Cmd
);
1640 Check the TRB execution result.
1642 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1643 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1645 @retval EFI_SUCCESS The TRB is executed successfully.
1646 @retval EFI_NOT_READY The TRB is not completed for execution.
1647 @retval Others Some erros happen when executing this request.
1651 SdMmcCheckTrbResult (
1652 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1653 IN SD_MMC_HC_TRB
*Trb
1657 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1665 Packet
= Trb
->Packet
;
1667 // Check Trb execution result by reading Normal Interrupt Status register.
1669 Status
= SdMmcHcRwMmio (
1672 SD_MMC_HC_NOR_INT_STS
,
1677 if (EFI_ERROR (Status
)) {
1681 // Check Transfer Complete bit is set or not.
1683 if ((IntStatus
& BIT1
) == BIT1
) {
1684 if ((IntStatus
& BIT15
) == BIT15
) {
1686 // Read Error Interrupt Status register to check if the error is
1687 // Data Timeout Error.
1688 // If yes, treat it as success as Transfer Complete has higher
1689 // priority than Data Timeout Error.
1691 Status
= SdMmcHcRwMmio (
1694 SD_MMC_HC_ERR_INT_STS
,
1699 if (!EFI_ERROR (Status
)) {
1700 if ((IntStatus
& BIT4
) == BIT4
) {
1701 Status
= EFI_SUCCESS
;
1703 Status
= EFI_DEVICE_ERROR
;
1711 // Check if there is a error happened during cmd execution.
1712 // If yes, then do error recovery procedure to follow SD Host Controller
1713 // Simplified Spec 3.0 section 3.10.1.
1715 if ((IntStatus
& BIT15
) == BIT15
) {
1716 Status
= SdMmcHcRwMmio (
1719 SD_MMC_HC_ERR_INT_STS
,
1724 if (EFI_ERROR (Status
)) {
1727 if ((IntStatus
& 0x0F) != 0) {
1730 if ((IntStatus
& 0xF0) != 0) {
1734 Status
= SdMmcHcRwMmio (
1742 if (EFI_ERROR (Status
)) {
1745 Status
= SdMmcHcWaitMmioSet (
1752 SD_MMC_HC_GENERIC_TIMEOUT
1754 if (EFI_ERROR (Status
)) {
1758 Status
= EFI_DEVICE_ERROR
;
1762 // Check if DMA interrupt is signalled for the SDMA transfer.
1764 if ((Trb
->Mode
== SdMmcSdmaMode
) && ((IntStatus
& BIT3
) == BIT3
)) {
1766 // Clear DMA interrupt bit.
1769 Status
= SdMmcHcRwMmio (
1772 SD_MMC_HC_NOR_INT_STS
,
1777 if (EFI_ERROR (Status
)) {
1781 // Update SDMA Address register.
1783 SdmaAddr
= SD_MMC_SDMA_ROUND_UP ((UINT32
)(UINTN
)Trb
->DataPhy
, SD_MMC_SDMA_BOUNDARY
);
1784 Status
= SdMmcHcRwMmio (
1787 SD_MMC_HC_SDMA_ADDR
,
1792 if (EFI_ERROR (Status
)) {
1795 Trb
->DataPhy
= (UINT32
)(UINTN
)SdmaAddr
;
1798 if ((Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeAdtc
) &&
1799 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR1b
) &&
1800 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR5b
)) {
1801 if ((IntStatus
& BIT0
) == BIT0
) {
1802 Status
= EFI_SUCCESS
;
1807 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1808 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1809 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1810 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1812 // While performing tuning procedure (Execute Tuning is set to 1),
1813 // Transfer Completeis not set to 1
1814 // Refer to SD Host Controller Simplified Specification 3.0 table 2-23 for details.
1816 Status
= EFI_SUCCESS
;
1820 Status
= EFI_NOT_READY
;
1823 // Get response data when the cmd is executed successfully.
1825 if (!EFI_ERROR (Status
)) {
1826 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
1827 for (Index
= 0; Index
< 4; Index
++) {
1828 Status
= SdMmcHcRwMmio (
1831 SD_MMC_HC_RESPONSE
+ Index
* 4,
1836 if (EFI_ERROR (Status
)) {
1837 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
1841 CopyMem (Packet
->SdMmcStatusBlk
, Response
, sizeof (Response
));
1845 if (Status
!= EFI_NOT_READY
) {
1846 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
1853 Wait for the TRB execution result.
1855 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1856 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1858 @retval EFI_SUCCESS The TRB is executed successfully.
1859 @retval Others Some erros happen when executing this request.
1863 SdMmcWaitTrbResult (
1864 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1865 IN SD_MMC_HC_TRB
*Trb
1869 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1871 BOOLEAN InfiniteWait
;
1873 Packet
= Trb
->Packet
;
1875 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1877 Timeout
= Packet
->Timeout
;
1879 InfiniteWait
= TRUE
;
1881 InfiniteWait
= FALSE
;
1884 while (InfiniteWait
|| (Timeout
> 0)) {
1886 // Check Trb execution result by reading Normal Interrupt Status register.
1888 Status
= SdMmcCheckTrbResult (Private
, Trb
);
1889 if (Status
!= EFI_NOT_READY
) {
1893 // Stall for 1 microsecond.