2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
7 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include "SdMmcPciHcDxe.h"
21 Dump the content of SD/MMC host controller's Capability Register.
23 @param[in] Slot The slot number of the SD card to send the command to.
24 @param[in] Capability The buffer to store the capability data.
30 IN SD_MMC_HC_SLOT_CAP
*Capability
34 // Dump Capability Data
36 DEBUG ((EFI_D_INFO
, " == Slot [%d] Capability is 0x%x ==\n", Slot
, Capability
));
37 DEBUG ((EFI_D_INFO
, " Timeout Clk Freq %d%a\n", Capability
->TimeoutFreq
, (Capability
->TimeoutUnit
) ? "MHz" : "KHz"));
38 DEBUG ((EFI_D_INFO
, " Base Clk Freq %dMHz\n", Capability
->BaseClkFreq
));
39 DEBUG ((EFI_D_INFO
, " Max Blk Len %dbytes\n", 512 * (1 << Capability
->MaxBlkLen
)));
40 DEBUG ((EFI_D_INFO
, " 8-bit Support %a\n", Capability
->BusWidth8
? "TRUE" : "FALSE"));
41 DEBUG ((EFI_D_INFO
, " ADMA2 Support %a\n", Capability
->Adma2
? "TRUE" : "FALSE"));
42 DEBUG ((EFI_D_INFO
, " HighSpeed Support %a\n", Capability
->HighSpeed
? "TRUE" : "FALSE"));
43 DEBUG ((EFI_D_INFO
, " SDMA Support %a\n", Capability
->Sdma
? "TRUE" : "FALSE"));
44 DEBUG ((EFI_D_INFO
, " Suspend/Resume %a\n", Capability
->SuspRes
? "TRUE" : "FALSE"));
45 DEBUG ((EFI_D_INFO
, " Voltage 3.3 %a\n", Capability
->Voltage33
? "TRUE" : "FALSE"));
46 DEBUG ((EFI_D_INFO
, " Voltage 3.0 %a\n", Capability
->Voltage30
? "TRUE" : "FALSE"));
47 DEBUG ((EFI_D_INFO
, " Voltage 1.8 %a\n", Capability
->Voltage18
? "TRUE" : "FALSE"));
48 DEBUG ((EFI_D_INFO
, " 64-bit Sys Bus %a\n", Capability
->SysBus64
? "TRUE" : "FALSE"));
49 DEBUG ((EFI_D_INFO
, " Async Interrupt %a\n", Capability
->AsyncInt
? "TRUE" : "FALSE"));
50 DEBUG ((EFI_D_INFO
, " SlotType "));
51 if (Capability
->SlotType
== 0x00) {
52 DEBUG ((EFI_D_INFO
, "%a\n", "Removable Slot"));
53 } else if (Capability
->SlotType
== 0x01) {
54 DEBUG ((EFI_D_INFO
, "%a\n", "Embedded Slot"));
55 } else if (Capability
->SlotType
== 0x02) {
56 DEBUG ((EFI_D_INFO
, "%a\n", "Shared Bus Slot"));
58 DEBUG ((EFI_D_INFO
, "%a\n", "Reserved"));
60 DEBUG ((EFI_D_INFO
, " SDR50 Support %a\n", Capability
->Sdr50
? "TRUE" : "FALSE"));
61 DEBUG ((EFI_D_INFO
, " SDR104 Support %a\n", Capability
->Sdr104
? "TRUE" : "FALSE"));
62 DEBUG ((EFI_D_INFO
, " DDR50 Support %a\n", Capability
->Ddr50
? "TRUE" : "FALSE"));
63 DEBUG ((EFI_D_INFO
, " Driver Type A %a\n", Capability
->DriverTypeA
? "TRUE" : "FALSE"));
64 DEBUG ((EFI_D_INFO
, " Driver Type C %a\n", Capability
->DriverTypeC
? "TRUE" : "FALSE"));
65 DEBUG ((EFI_D_INFO
, " Driver Type D %a\n", Capability
->DriverTypeD
? "TRUE" : "FALSE"));
66 DEBUG ((EFI_D_INFO
, " Driver Type 4 %a\n", Capability
->DriverType4
? "TRUE" : "FALSE"));
67 if (Capability
->TimerCount
== 0) {
68 DEBUG ((EFI_D_INFO
, " Retuning TimerCnt Disabled\n", 2 * (Capability
->TimerCount
- 1)));
70 DEBUG ((EFI_D_INFO
, " Retuning TimerCnt %dseconds\n", 2 * (Capability
->TimerCount
- 1)));
72 DEBUG ((EFI_D_INFO
, " SDR50 Tuning %a\n", Capability
->TuningSDR50
? "TRUE" : "FALSE"));
73 DEBUG ((EFI_D_INFO
, " Retuning Mode Mode %d\n", Capability
->RetuningMod
+ 1));
74 DEBUG ((EFI_D_INFO
, " Clock Multiplier M = %d\n", Capability
->ClkMultiplier
+ 1));
75 DEBUG ((EFI_D_INFO
, " HS 400 %a\n", Capability
->Hs400
? "TRUE" : "FALSE"));
80 Read SlotInfo register from SD/MMC host controller pci config space.
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
93 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
99 SD_MMC_HC_SLOT_INFO SlotInfo
;
101 Status
= PciIo
->Pci
.Read (
104 SD_MMC_HC_SLOT_OFFSET
,
108 if (EFI_ERROR (Status
)) {
112 *FirstBar
= SlotInfo
.FirstBar
;
113 *SlotNum
= SlotInfo
.SlotNum
+ 1;
114 ASSERT ((*FirstBar
+ *SlotNum
) < SD_MMC_HC_MAX_SLOT
);
119 Read/Write specified SD/MMC host controller mmio register.
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
144 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
154 if ((PciIo
== NULL
) || (Data
== NULL
)) {
155 return EFI_INVALID_PARAMETER
;
158 if ((Count
!= 1) && (Count
!= 2) && (Count
!= 4) && (Count
!= 8)) {
159 return EFI_INVALID_PARAMETER
;
163 Status
= PciIo
->Mem
.Read (
172 Status
= PciIo
->Mem
.Write (
186 Do OR operation with the value of the specified SD/MMC host controller mmio register.
188 @param[in] PciIo The PCI IO protocol instance.
189 @param[in] BarIndex The BAR index of the standard PCI Configuration
190 header to use as the base address for the memory
191 operation to perform.
192 @param[in] Offset The offset within the selected BAR to start the
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2 , 4 or 8 bytes.
196 @param[in] OrData The pointer to the data used to do OR operation.
197 The caller is responsible for having ownership of
198 the data buffer and ensuring its size not less than
201 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
202 @retval EFI_SUCCESS The OR operation succeeds.
203 @retval Others The OR operation fails.
209 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
220 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
221 if (EFI_ERROR (Status
)) {
226 Or
= *(UINT8
*) OrData
;
227 } else if (Count
== 2) {
228 Or
= *(UINT16
*) OrData
;
229 } else if (Count
== 4) {
230 Or
= *(UINT32
*) OrData
;
231 } else if (Count
== 8) {
232 Or
= *(UINT64
*) OrData
;
234 return EFI_INVALID_PARAMETER
;
238 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
244 Do AND operation with the value of the specified SD/MMC host controller mmio register.
246 @param[in] PciIo The PCI IO protocol instance.
247 @param[in] BarIndex The BAR index of the standard PCI Configuration
248 header to use as the base address for the memory
249 operation to perform.
250 @param[in] Offset The offset within the selected BAR to start the
252 @param[in] Count The width of the mmio register in bytes.
253 Must be 1, 2 , 4 or 8 bytes.
254 @param[in] AndData The pointer to the data used to do AND operation.
255 The caller is responsible for having ownership of
256 the data buffer and ensuring its size not less than
259 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
260 @retval EFI_SUCCESS The AND operation succeeds.
261 @retval Others The AND operation fails.
267 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
278 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
279 if (EFI_ERROR (Status
)) {
284 And
= *(UINT8
*) AndData
;
285 } else if (Count
== 2) {
286 And
= *(UINT16
*) AndData
;
287 } else if (Count
== 4) {
288 And
= *(UINT32
*) AndData
;
289 } else if (Count
== 8) {
290 And
= *(UINT64
*) AndData
;
292 return EFI_INVALID_PARAMETER
;
296 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
302 Wait for the value of the specified MMIO register set to the test value.
304 @param[in] PciIo The PCI IO protocol instance.
305 @param[in] BarIndex The BAR index of the standard PCI Configuration
306 header to use as the base address for the memory
307 operation to perform.
308 @param[in] Offset The offset within the selected BAR to start the
310 @param[in] Count The width of the mmio register in bytes.
311 Must be 1, 2, 4 or 8 bytes.
312 @param[in] MaskValue The mask value of memory.
313 @param[in] TestValue The test value of memory.
315 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
316 @retval EFI_SUCCESS The MMIO register has expected value.
317 @retval Others The MMIO operation fails.
322 SdMmcHcCheckMmioSet (
323 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
335 // Access PCI MMIO space to see if the value is the tested one.
338 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Value
);
339 if (EFI_ERROR (Status
)) {
345 if (Value
== TestValue
) {
349 return EFI_NOT_READY
;
353 Wait for the value of the specified MMIO register set to the test value.
355 @param[in] PciIo The PCI IO protocol instance.
356 @param[in] BarIndex The BAR index of the standard PCI Configuration
357 header to use as the base address for the memory
358 operation to perform.
359 @param[in] Offset The offset within the selected BAR to start the
361 @param[in] Count The width of the mmio register in bytes.
362 Must be 1, 2, 4 or 8 bytes.
363 @param[in] MaskValue The mask value of memory.
364 @param[in] TestValue The test value of memory.
365 @param[in] Timeout The time out value for wait memory set, uses 1
366 microsecond as a unit.
368 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
370 @retval EFI_SUCCESS The MMIO register has expected value.
371 @retval Others The MMIO operation fails.
377 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
387 BOOLEAN InfiniteWait
;
392 InfiniteWait
= FALSE
;
395 while (InfiniteWait
|| (Timeout
> 0)) {
396 Status
= SdMmcHcCheckMmioSet (
404 if (Status
!= EFI_NOT_READY
) {
409 // Stall for 1 microsecond.
420 Software reset the specified SD/MMC host controller and enable all interrupts.
422 @param[in] PciIo The PCI IO protocol instance.
423 @param[in] Slot The slot number of the SD card to send the command to.
425 @retval EFI_SUCCESS The software reset executes successfully.
426 @retval Others The software reset fails.
431 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
439 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_SW_RST
, FALSE
, sizeof (SwReset
), &SwReset
);
441 if (EFI_ERROR (Status
)) {
442 DEBUG ((EFI_D_ERROR
, "SdMmcHcReset: write full 1 fails: %r\n", Status
));
446 Status
= SdMmcHcWaitMmioSet (
453 SD_MMC_HC_GENERIC_TIMEOUT
455 if (EFI_ERROR (Status
)) {
456 DEBUG ((EFI_D_INFO
, "SdMmcHcReset: reset done with %r\n", Status
));
460 // Enable all interrupt after reset all.
462 Status
= SdMmcHcEnableInterrupt (PciIo
, Slot
);
468 Set all interrupt status bits in Normal and Error Interrupt Status Enable
471 @param[in] PciIo The PCI IO protocol instance.
472 @param[in] Slot The slot number of the SD card to send the command to.
474 @retval EFI_SUCCESS The operation executes successfully.
475 @retval Others The operation fails.
479 SdMmcHcEnableInterrupt (
480 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
488 // Enable all bits in Error Interrupt Status Enable Register
491 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_ERR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
492 if (EFI_ERROR (Status
)) {
496 // Enable all bits in Normal Interrupt Status Enable Register
499 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
505 Get the capability data from the specified slot.
507 @param[in] PciIo The PCI IO protocol instance.
508 @param[in] Slot The slot number of the SD card to send the command to.
509 @param[out] Capability The buffer to store the capability data.
511 @retval EFI_SUCCESS The operation executes successfully.
512 @retval Others The operation fails.
516 SdMmcHcGetCapability (
517 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
519 OUT SD_MMC_HC_SLOT_CAP
*Capability
525 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CAP
, TRUE
, sizeof (Cap
), &Cap
);
526 if (EFI_ERROR (Status
)) {
530 CopyMem (Capability
, &Cap
, sizeof (Cap
));
536 Get the maximum current capability data from the specified slot.
538 @param[in] PciIo The PCI IO protocol instance.
539 @param[in] Slot The slot number of the SD card to send the command to.
540 @param[out] MaxCurrent The buffer to store the maximum current capability data.
542 @retval EFI_SUCCESS The operation executes successfully.
543 @retval Others The operation fails.
547 SdMmcHcGetMaxCurrent (
548 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
550 OUT UINT64
*MaxCurrent
555 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_MAX_CURRENT_CAP
, TRUE
, sizeof (UINT64
), MaxCurrent
);
561 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
564 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
566 @param[in] PciIo The PCI IO protocol instance.
567 @param[in] Slot The slot number of the SD card to send the command to.
568 @param[out] MediaPresent The pointer to the media present boolean value.
570 @retval EFI_SUCCESS There is no media change happened.
571 @retval EFI_MEDIA_CHANGED There is media change happened.
572 @retval Others The detection fails.
577 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
579 OUT BOOLEAN
*MediaPresent
587 // Check Normal Interrupt Status Register
589 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, TRUE
, sizeof (Data
), &Data
);
590 if (EFI_ERROR (Status
)) {
594 if ((Data
& (BIT6
| BIT7
)) != 0) {
596 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
599 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data
), &Data
);
600 if (EFI_ERROR (Status
)) {
605 // Check Present State Register to see if there is a card presented.
607 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_PRESENT_STATE
, TRUE
, sizeof (PresentState
), &PresentState
);
608 if (EFI_ERROR (Status
)) {
612 if ((PresentState
& BIT16
) != 0) {
613 *MediaPresent
= TRUE
;
615 *MediaPresent
= FALSE
;
617 return EFI_MEDIA_CHANGED
;
624 Stop SD/MMC card clock.
626 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
628 @param[in] PciIo The PCI IO protocol instance.
629 @param[in] Slot The slot number of the SD card to send the command to.
631 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
632 @retval Others Fail to stop SD/MMC clock.
637 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
646 // Ensure no SD transactions are occurring on the SD Bus by
647 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
648 // in the Present State register to be 0.
650 Status
= SdMmcHcWaitMmioSet (
653 SD_MMC_HC_PRESENT_STATE
,
654 sizeof (PresentState
),
657 SD_MMC_HC_GENERIC_TIMEOUT
659 if (EFI_ERROR (Status
)) {
664 // Set SD Clock Enable in the Clock Control register to 0
666 ClockCtrl
= (UINT16
)~BIT2
;
667 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
673 SD/MMC card clock supply.
675 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
677 @param[in] PciIo The PCI IO protocol instance.
678 @param[in] Slot The slot number of the SD card to send the command to.
679 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
680 @param[in] Capability The capability of the slot.
682 @retval EFI_SUCCESS The clock is supplied successfully.
683 @retval Others The clock isn't supplied successfully.
688 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
691 IN SD_MMC_HC_SLOT_CAP Capability
699 UINT16 ControllerVer
;
703 // Calculate a divisor for SD clock frequency
705 ASSERT (Capability
.BaseClkFreq
!= 0);
707 BaseClkFreq
= Capability
.BaseClkFreq
;
708 if ((ClockFreq
> (BaseClkFreq
* 1000)) || (ClockFreq
== 0)) {
709 return EFI_INVALID_PARAMETER
;
712 // Calculate the divisor of base frequency.
715 SettingFreq
= BaseClkFreq
* 1000;
716 while (ClockFreq
< SettingFreq
) {
719 SettingFreq
= (BaseClkFreq
* 1000) / (2 * Divisor
);
720 Remainder
= (BaseClkFreq
* 1000) % (2 * Divisor
);
721 if ((ClockFreq
== SettingFreq
) && (Remainder
== 0)) {
724 if ((ClockFreq
== SettingFreq
) && (Remainder
!= 0)) {
729 DEBUG ((EFI_D_INFO
, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq
, Divisor
, ClockFreq
));
731 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CTRL_VER
, TRUE
, sizeof (ControllerVer
), &ControllerVer
);
732 if (EFI_ERROR (Status
)) {
736 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
738 if ((ControllerVer
& 0xFF) == 2) {
739 ASSERT (Divisor
<= 0x3FF);
740 ClockCtrl
= ((Divisor
& 0xFF) << 8) | ((Divisor
& 0x300) >> 2);
741 } else if (((ControllerVer
& 0xFF) == 0) || ((ControllerVer
& 0xFF) == 1)) {
743 // Only the most significant bit can be used as divisor.
745 if (((Divisor
- 1) & Divisor
) != 0) {
746 Divisor
= 1 << (HighBitSet32 (Divisor
) + 1);
748 ASSERT (Divisor
<= 0x80);
749 ClockCtrl
= (Divisor
& 0xFF) << 8;
751 DEBUG ((EFI_D_ERROR
, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer
));
752 return EFI_UNSUPPORTED
;
756 // Stop bus clock at first
758 Status
= SdMmcHcStopClock (PciIo
, Slot
);
759 if (EFI_ERROR (Status
)) {
764 // Supply clock frequency with specified divisor
767 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, FALSE
, sizeof (ClockCtrl
), &ClockCtrl
);
768 if (EFI_ERROR (Status
)) {
769 DEBUG ((EFI_D_ERROR
, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
774 // Wait Internal Clock Stable in the Clock Control register to be 1
776 Status
= SdMmcHcWaitMmioSet (
779 SD_MMC_HC_CLOCK_CTRL
,
783 SD_MMC_HC_GENERIC_TIMEOUT
785 if (EFI_ERROR (Status
)) {
790 // Set SD Clock Enable in the Clock Control register to 1
793 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
799 SD/MMC bus power control.
801 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
803 @param[in] PciIo The PCI IO protocol instance.
804 @param[in] Slot The slot number of the SD card to send the command to.
805 @param[in] PowerCtrl The value setting to the power control register.
807 @retval TRUE There is a SD/MMC card attached.
808 @retval FALSE There is no a SD/MMC card attached.
812 SdMmcHcPowerControl (
813 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
823 PowerCtrl
&= (UINT8
)~BIT0
;
824 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
825 if (EFI_ERROR (Status
)) {
830 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
833 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
839 Set the SD/MMC bus width.
841 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
843 @param[in] PciIo The PCI IO protocol instance.
844 @param[in] Slot The slot number of the SD card to send the command to.
845 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
847 @retval EFI_SUCCESS The bus width is set successfully.
848 @retval Others The bus width isn't set successfully.
853 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
862 HostCtrl1
= (UINT8
)~(BIT5
| BIT1
);
863 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
864 } else if (BusWidth
== 4) {
865 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
866 if (EFI_ERROR (Status
)) {
870 HostCtrl1
&= (UINT8
)~BIT5
;
871 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
872 } else if (BusWidth
== 8) {
873 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
874 if (EFI_ERROR (Status
)) {
877 HostCtrl1
&= (UINT8
)~BIT1
;
879 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
882 return EFI_INVALID_PARAMETER
;
889 Supply SD/MMC card with lowest clock frequency at initialization.
891 @param[in] PciIo The PCI IO protocol instance.
892 @param[in] Slot The slot number of the SD card to send the command to.
893 @param[in] Capability The capability of the slot.
895 @retval EFI_SUCCESS The clock is supplied successfully.
896 @retval Others The clock isn't supplied successfully.
900 SdMmcHcInitClockFreq (
901 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
903 IN SD_MMC_HC_SLOT_CAP Capability
910 // Calculate a divisor for SD clock frequency
912 if (Capability
.BaseClkFreq
== 0) {
914 // Don't support get Base Clock Frequency information via another method
916 return EFI_UNSUPPORTED
;
919 // Supply 400KHz clock frequency at initialization phase.
922 Status
= SdMmcHcClockSupply (PciIo
, Slot
, InitFreq
, Capability
);
927 Supply SD/MMC card with maximum voltage at initialization.
929 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
931 @param[in] PciIo The PCI IO protocol instance.
932 @param[in] Slot The slot number of the SD card to send the command to.
933 @param[in] Capability The capability of the slot.
935 @retval EFI_SUCCESS The voltage is supplied successfully.
936 @retval Others The voltage isn't supplied successfully.
940 SdMmcHcInitPowerVoltage (
941 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
943 IN SD_MMC_HC_SLOT_CAP Capability
951 // Calculate supported maximum voltage according to SD Bus Voltage Select
953 if (Capability
.Voltage33
!= 0) {
958 } else if (Capability
.Voltage30
!= 0) {
963 } else if (Capability
.Voltage18
!= 0) {
969 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
971 if (EFI_ERROR (Status
)) {
976 return EFI_DEVICE_ERROR
;
980 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
982 Status
= SdMmcHcPowerControl (PciIo
, Slot
, MaxVoltage
);
988 Initialize the Timeout Control register with most conservative value at initialization.
990 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
992 @param[in] PciIo The PCI IO protocol instance.
993 @param[in] Slot The slot number of the SD card to send the command to.
995 @retval EFI_SUCCESS The timeout control register is configured successfully.
996 @retval Others The timeout control register isn't configured successfully.
1000 SdMmcHcInitTimeoutCtrl (
1001 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1009 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_TIMEOUT_CTRL
, FALSE
, sizeof (Timeout
), &Timeout
);
1015 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1018 @param[in] PciIo The PCI IO protocol instance.
1019 @param[in] Slot The slot number of the SD card to send the command to.
1020 @param[in] Capability The capability of the slot.
1022 @retval EFI_SUCCESS The host controller is initialized successfully.
1023 @retval Others The host controller isn't initialized successfully.
1028 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1030 IN SD_MMC_HC_SLOT_CAP Capability
1035 Status
= SdMmcHcInitClockFreq (PciIo
, Slot
, Capability
);
1036 if (EFI_ERROR (Status
)) {
1040 Status
= SdMmcHcInitPowerVoltage (PciIo
, Slot
, Capability
);
1041 if (EFI_ERROR (Status
)) {
1045 Status
= SdMmcHcInitTimeoutCtrl (PciIo
, Slot
);
1052 @param[in] PciIo The PCI IO protocol instance.
1053 @param[in] Slot The slot number of the SD card to send the command to.
1054 @param[in] On The boolean to turn on/off LED.
1056 @retval EFI_SUCCESS The LED is turned on/off successfully.
1057 @retval Others The LED isn't turned on/off successfully.
1062 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1072 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1074 HostCtrl1
= (UINT8
)~BIT0
;
1075 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1082 Build ADMA descriptor table for transfer.
1084 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
1086 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1088 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1089 @retval Others The ADMA descriptor table isn't created successfully.
1093 BuildAdmaDescTable (
1094 IN SD_MMC_HC_TRB
*Trb
1097 EFI_PHYSICAL_ADDRESS Data
;
1104 EFI_PCI_IO_PROTOCOL
*PciIo
;
1108 Data
= Trb
->DataPhy
;
1109 DataLen
= Trb
->DataLen
;
1110 PciIo
= Trb
->Private
->PciIo
;
1112 // Only support 32bit ADMA Descriptor Table
1114 if ((Data
>= 0x100000000ul
) || ((Data
+ DataLen
) > 0x100000000ul
)) {
1115 return EFI_INVALID_PARAMETER
;
1118 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1119 // for 32-bit address descriptor table.
1121 if ((Data
& (BIT0
| BIT1
)) != 0) {
1122 DEBUG ((EFI_D_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data
));
1125 Entries
= DivU64x32 ((DataLen
+ ADMA_MAX_DATA_PER_LINE
- 1), ADMA_MAX_DATA_PER_LINE
);
1126 TableSize
= (UINTN
)MultU64x32 (Entries
, sizeof (SD_MMC_HC_ADMA_DESC_LINE
));
1127 Trb
->AdmaPages
= (UINT32
)EFI_SIZE_TO_PAGES (TableSize
);
1128 Status
= PciIo
->AllocateBuffer (
1131 EfiBootServicesData
,
1132 EFI_SIZE_TO_PAGES (TableSize
),
1133 (VOID
**)&Trb
->AdmaDesc
,
1136 if (EFI_ERROR (Status
)) {
1137 return EFI_OUT_OF_RESOURCES
;
1139 ZeroMem (Trb
->AdmaDesc
, TableSize
);
1141 Status
= PciIo
->Map (
1143 EfiPciIoOperationBusMasterCommonBuffer
,
1150 if (EFI_ERROR (Status
) || (Bytes
!= TableSize
)) {
1152 // Map error or unable to map the whole RFis buffer into a contiguous region.
1156 EFI_SIZE_TO_PAGES (TableSize
),
1159 return EFI_OUT_OF_RESOURCES
;
1162 if ((UINT64
)(UINTN
)Trb
->AdmaDescPhy
> 0x100000000ul
) {
1164 // The ADMA doesn't support 64bit addressing.
1172 EFI_SIZE_TO_PAGES (TableSize
),
1175 return EFI_DEVICE_ERROR
;
1178 Remaining
= DataLen
;
1179 Address
= (UINT32
)Data
;
1180 for (Index
= 0; Index
< Entries
; Index
++) {
1181 if (Remaining
<= ADMA_MAX_DATA_PER_LINE
) {
1182 Trb
->AdmaDesc
[Index
].Valid
= 1;
1183 Trb
->AdmaDesc
[Index
].Act
= 2;
1184 Trb
->AdmaDesc
[Index
].Length
= (UINT16
)Remaining
;
1185 Trb
->AdmaDesc
[Index
].Address
= Address
;
1188 Trb
->AdmaDesc
[Index
].Valid
= 1;
1189 Trb
->AdmaDesc
[Index
].Act
= 2;
1190 Trb
->AdmaDesc
[Index
].Length
= 0;
1191 Trb
->AdmaDesc
[Index
].Address
= Address
;
1194 Remaining
-= ADMA_MAX_DATA_PER_LINE
;
1195 Address
+= ADMA_MAX_DATA_PER_LINE
;
1199 // Set the last descriptor line as end of descriptor table
1201 Trb
->AdmaDesc
[Index
].End
= 1;
1206 Create a new TRB for the SD/MMC cmd request.
1208 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1209 @param[in] Slot The slot number of the SD card to send the command to.
1210 @param[in] Packet A pointer to the SD command data structure.
1211 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1212 not NULL, then nonblocking I/O is performed, and Event
1213 will be signaled when the Packet completes.
1215 @return Created Trb or NULL.
1220 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1222 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
,
1229 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
1230 EFI_PCI_IO_PROTOCOL
*PciIo
;
1233 Trb
= AllocateZeroPool (sizeof (SD_MMC_HC_TRB
));
1238 Trb
->Signature
= SD_MMC_HC_TRB_SIG
;
1240 Trb
->BlockSize
= 0x200;
1241 Trb
->Packet
= Packet
;
1243 Trb
->Started
= FALSE
;
1244 Trb
->Timeout
= Packet
->Timeout
;
1245 Trb
->Private
= Private
;
1247 if ((Packet
->InTransferLength
!= 0) && (Packet
->InDataBuffer
!= NULL
)) {
1248 Trb
->Data
= Packet
->InDataBuffer
;
1249 Trb
->DataLen
= Packet
->InTransferLength
;
1251 } else if ((Packet
->OutTransferLength
!= 0) && (Packet
->OutDataBuffer
!= NULL
)) {
1252 Trb
->Data
= Packet
->OutDataBuffer
;
1253 Trb
->DataLen
= Packet
->OutTransferLength
;
1255 } else if ((Packet
->InTransferLength
== 0) && (Packet
->OutTransferLength
== 0)) {
1263 Flag
= EfiPciIoOperationBusMasterWrite
;
1265 Flag
= EfiPciIoOperationBusMasterRead
;
1268 PciIo
= Private
->PciIo
;
1269 if (Trb
->DataLen
!= 0) {
1270 MapLength
= Trb
->DataLen
;
1271 Status
= PciIo
->Map (
1279 if (EFI_ERROR (Status
) || (Trb
->DataLen
!= MapLength
)) {
1280 Status
= EFI_BAD_BUFFER_SIZE
;
1285 if ((Trb
->DataLen
% Trb
->BlockSize
) != 0) {
1286 if (Trb
->DataLen
< Trb
->BlockSize
) {
1287 Trb
->BlockSize
= (UINT16
)Trb
->DataLen
;
1291 if (Trb
->DataLen
== 0) {
1292 Trb
->Mode
= SdMmcNoData
;
1293 } else if (Private
->Capability
[Slot
].Adma2
!= 0) {
1294 Trb
->Mode
= SdMmcAdmaMode
;
1295 Status
= BuildAdmaDescTable (Trb
);
1296 if (EFI_ERROR (Status
)) {
1297 PciIo
->Unmap (PciIo
, Trb
->DataMap
);
1300 } else if (Private
->Capability
[Slot
].Sdma
!= 0) {
1301 Trb
->Mode
= SdMmcSdmaMode
;
1303 Trb
->Mode
= SdMmcPioMode
;
1306 if (Event
!= NULL
) {
1307 OldTpl
= gBS
->RaiseTPL (TPL_CALLBACK
);
1308 InsertTailList (&Private
->Queue
, &Trb
->TrbList
);
1309 gBS
->RestoreTPL (OldTpl
);
1320 Free the resource used by the TRB.
1322 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1327 IN SD_MMC_HC_TRB
*Trb
1330 EFI_PCI_IO_PROTOCOL
*PciIo
;
1332 PciIo
= Trb
->Private
->PciIo
;
1334 if (Trb
->AdmaMap
!= NULL
) {
1340 if (Trb
->AdmaDesc
!= NULL
) {
1347 if (Trb
->DataMap
!= NULL
) {
1358 Check if the env is ready for execute specified TRB.
1360 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1361 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1363 @retval EFI_SUCCESS The env is ready for TRB execution.
1364 @retval EFI_NOT_READY The env is not ready for TRB execution.
1365 @retval Others Some erros happen.
1370 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1371 IN SD_MMC_HC_TRB
*Trb
1375 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1376 EFI_PCI_IO_PROTOCOL
*PciIo
;
1377 UINT32 PresentState
;
1379 Packet
= Trb
->Packet
;
1381 if ((Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) ||
1382 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR1b
) ||
1383 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR5b
)) {
1385 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1386 // the Present State register to be 0
1388 PresentState
= BIT0
| BIT1
;
1390 // For Send Tuning Block cmd, just wait for Command Inhibit (CMD) to be 0
1392 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1393 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1394 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1395 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1396 PresentState
= BIT0
;
1400 // Wait Command Inhibit (CMD) in the Present State register
1403 PresentState
= BIT0
;
1406 PciIo
= Private
->PciIo
;
1407 Status
= SdMmcHcCheckMmioSet (
1410 SD_MMC_HC_PRESENT_STATE
,
1411 sizeof (PresentState
),
1420 Wait for the env to be ready for execute specified TRB.
1422 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1423 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1425 @retval EFI_SUCCESS The env is ready for TRB execution.
1426 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1427 @retval Others Some erros happen.
1432 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1433 IN SD_MMC_HC_TRB
*Trb
1437 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1439 BOOLEAN InfiniteWait
;
1442 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1444 Packet
= Trb
->Packet
;
1445 Timeout
= Packet
->Timeout
;
1447 InfiniteWait
= TRUE
;
1449 InfiniteWait
= FALSE
;
1452 while (InfiniteWait
|| (Timeout
> 0)) {
1454 // Check Trb execution result by reading Normal Interrupt Status register.
1456 Status
= SdMmcCheckTrbEnv (Private
, Trb
);
1457 if (Status
!= EFI_NOT_READY
) {
1461 // Stall for 1 microsecond.
1472 Execute the specified TRB.
1474 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1475 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1477 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1478 @retval Others Some erros happen when sending this request to the host controller.
1483 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1484 IN SD_MMC_HC_TRB
*Trb
1488 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1489 EFI_PCI_IO_PROTOCOL
*PciIo
;
1500 Packet
= Trb
->Packet
;
1501 PciIo
= Trb
->Private
->PciIo
;
1503 // Clear all bits in Error Interrupt Status Register
1506 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ERR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1507 if (EFI_ERROR (Status
)) {
1511 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1514 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1515 if (EFI_ERROR (Status
)) {
1519 // Set Host Control 1 register DMA Select field
1521 if (Trb
->Mode
== SdMmcAdmaMode
) {
1523 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1524 if (EFI_ERROR (Status
)) {
1529 SdMmcHcLedOnOff (PciIo
, Trb
->Slot
, TRUE
);
1531 if (Trb
->Mode
== SdMmcSdmaMode
) {
1532 if ((UINT64
)(UINTN
)Trb
->DataPhy
>= 0x100000000ul
) {
1533 return EFI_INVALID_PARAMETER
;
1536 SdmaAddr
= (UINT32
)(UINTN
)Trb
->DataPhy
;
1537 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (SdmaAddr
), &SdmaAddr
);
1538 if (EFI_ERROR (Status
)) {
1541 } else if (Trb
->Mode
== SdMmcAdmaMode
) {
1542 AdmaAddr
= (UINT64
)(UINTN
)Trb
->AdmaDescPhy
;
1543 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (AdmaAddr
), &AdmaAddr
);
1544 if (EFI_ERROR (Status
)) {
1549 BlkSize
= Trb
->BlockSize
;
1550 if (Trb
->Mode
== SdMmcSdmaMode
) {
1552 // Set SDMA boundary to be 512K bytes.
1557 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_SIZE
, FALSE
, sizeof (BlkSize
), &BlkSize
);
1558 if (EFI_ERROR (Status
)) {
1562 BlkCount
= (UINT16
)(Trb
->DataLen
/ Trb
->BlockSize
);
1563 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_COUNT
, FALSE
, sizeof (BlkCount
), &BlkCount
);
1564 if (EFI_ERROR (Status
)) {
1568 Argument
= Packet
->SdMmcCmdBlk
->CommandArgument
;
1569 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ARG1
, FALSE
, sizeof (Argument
), &Argument
);
1570 if (EFI_ERROR (Status
)) {
1575 if (Trb
->Mode
!= SdMmcNoData
) {
1576 if (Trb
->Mode
!= SdMmcPioMode
) {
1582 if (BlkCount
!= 0) {
1583 TransMode
|= BIT5
| BIT1
;
1586 // Only SD memory card needs to use AUTO CMD12 feature.
1588 if (Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) {
1595 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_TRANS_MOD
, FALSE
, sizeof (TransMode
), &TransMode
);
1596 if (EFI_ERROR (Status
)) {
1600 Cmd
= (UINT16
)LShiftU64(Packet
->SdMmcCmdBlk
->CommandIndex
, 8);
1601 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) {
1605 // Convert ResponseType to value
1607 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
1608 switch (Packet
->SdMmcCmdBlk
->ResponseType
) {
1609 case SdMmcResponseTypeR1
:
1610 case SdMmcResponseTypeR5
:
1611 case SdMmcResponseTypeR6
:
1612 case SdMmcResponseTypeR7
:
1613 Cmd
|= (BIT1
| BIT3
| BIT4
);
1615 case SdMmcResponseTypeR2
:
1616 Cmd
|= (BIT0
| BIT3
);
1618 case SdMmcResponseTypeR3
:
1619 case SdMmcResponseTypeR4
:
1622 case SdMmcResponseTypeR1b
:
1623 case SdMmcResponseTypeR5b
:
1624 Cmd
|= (BIT0
| BIT1
| BIT3
| BIT4
);
1634 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_COMMAND
, FALSE
, sizeof (Cmd
), &Cmd
);
1639 Check the TRB execution result.
1641 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1642 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1644 @retval EFI_SUCCESS The TRB is executed successfully.
1645 @retval EFI_NOT_READY The TRB is not completed for execution.
1646 @retval Others Some erros happen when executing this request.
1650 SdMmcCheckTrbResult (
1651 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1652 IN SD_MMC_HC_TRB
*Trb
1656 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1664 Packet
= Trb
->Packet
;
1666 // Check Trb execution result by reading Normal Interrupt Status register.
1668 Status
= SdMmcHcRwMmio (
1671 SD_MMC_HC_NOR_INT_STS
,
1676 if (EFI_ERROR (Status
)) {
1680 // Check Transfer Complete bit is set or not.
1682 if ((IntStatus
& BIT1
) == BIT1
) {
1683 if ((IntStatus
& BIT15
) == BIT15
) {
1685 // Read Error Interrupt Status register to check if the error is
1686 // Data Timeout Error.
1687 // If yes, treat it as success as Transfer Complete has higher
1688 // priority than Data Timeout Error.
1690 Status
= SdMmcHcRwMmio (
1693 SD_MMC_HC_ERR_INT_STS
,
1698 if (!EFI_ERROR (Status
)) {
1699 if ((IntStatus
& BIT4
) == BIT4
) {
1700 Status
= EFI_SUCCESS
;
1702 Status
= EFI_DEVICE_ERROR
;
1710 // Check if there is a error happened during cmd execution.
1711 // If yes, then do error recovery procedure to follow SD Host Controller
1712 // Simplified Spec 3.0 section 3.10.1.
1714 if ((IntStatus
& BIT15
) == BIT15
) {
1715 Status
= SdMmcHcRwMmio (
1718 SD_MMC_HC_ERR_INT_STS
,
1723 if (EFI_ERROR (Status
)) {
1726 if ((IntStatus
& 0x0F) != 0) {
1729 if ((IntStatus
& 0xF0) != 0) {
1733 Status
= SdMmcHcRwMmio (
1741 if (EFI_ERROR (Status
)) {
1744 Status
= SdMmcHcWaitMmioSet (
1751 SD_MMC_HC_GENERIC_TIMEOUT
1753 if (EFI_ERROR (Status
)) {
1757 Status
= EFI_DEVICE_ERROR
;
1761 // Check if DMA interrupt is signalled for the SDMA transfer.
1763 if ((Trb
->Mode
== SdMmcSdmaMode
) && ((IntStatus
& BIT3
) == BIT3
)) {
1765 // Clear DMA interrupt bit.
1768 Status
= SdMmcHcRwMmio (
1771 SD_MMC_HC_NOR_INT_STS
,
1776 if (EFI_ERROR (Status
)) {
1780 // Update SDMA Address register.
1782 SdmaAddr
= SD_MMC_SDMA_ROUND_UP ((UINT32
)(UINTN
)Trb
->DataPhy
, SD_MMC_SDMA_BOUNDARY
);
1783 Status
= SdMmcHcRwMmio (
1786 SD_MMC_HC_SDMA_ADDR
,
1791 if (EFI_ERROR (Status
)) {
1794 Trb
->DataPhy
= (UINT32
)(UINTN
)SdmaAddr
;
1797 if ((Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeAdtc
) &&
1798 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR1b
) &&
1799 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR5b
)) {
1800 if ((IntStatus
& BIT0
) == BIT0
) {
1801 Status
= EFI_SUCCESS
;
1806 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1807 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1808 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1809 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1811 // While performing tuning procedure (Execute Tuning is set to 1),
1812 // Transfer Completeis not set to 1
1813 // Refer to SD Host Controller Simplified Specification 3.0 table 2-23 for details.
1815 Status
= EFI_SUCCESS
;
1819 Status
= EFI_NOT_READY
;
1822 // Get response data when the cmd is executed successfully.
1824 if (!EFI_ERROR (Status
)) {
1825 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
1826 for (Index
= 0; Index
< 4; Index
++) {
1827 Status
= SdMmcHcRwMmio (
1830 SD_MMC_HC_RESPONSE
+ Index
* 4,
1835 if (EFI_ERROR (Status
)) {
1836 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
1840 CopyMem (Packet
->SdMmcStatusBlk
, Response
, sizeof (Response
));
1844 if (Status
!= EFI_NOT_READY
) {
1845 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
1852 Wait for the TRB execution result.
1854 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1855 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1857 @retval EFI_SUCCESS The TRB is executed successfully.
1858 @retval Others Some erros happen when executing this request.
1862 SdMmcWaitTrbResult (
1863 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1864 IN SD_MMC_HC_TRB
*Trb
1868 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1870 BOOLEAN InfiniteWait
;
1872 Packet
= Trb
->Packet
;
1874 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1876 Timeout
= Packet
->Timeout
;
1878 InfiniteWait
= TRUE
;
1880 InfiniteWait
= FALSE
;
1883 while (InfiniteWait
|| (Timeout
> 0)) {
1885 // Check Trb execution result by reading Normal Interrupt Status register.
1887 Status
= SdMmcCheckTrbResult (Private
, Trb
);
1888 if (Status
!= EFI_NOT_READY
) {
1892 // Stall for 1 microsecond.