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MdeModulePkg/SdMmcPciHcDxe: Add V3 64b DMA Support
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
5 4.20.
6
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
8
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
11 This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18
19 **/
20
21 #include "SdMmcPciHcDxe.h"
22
23 /**
24 Dump the content of SD/MMC host controller's Capability Register.
25
26 @param[in] Slot The slot number of the SD card to send the command to.
27 @param[in] Capability The buffer to store the capability data.
28
29 **/
30 VOID
31 DumpCapabilityReg (
32 IN UINT8 Slot,
33 IN SD_MMC_HC_SLOT_CAP *Capability
34 )
35 {
36 //
37 // Dump Capability Data
38 //
39 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
40 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
41 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
42 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
43 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
49 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
50 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
51 DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));
52 DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));
53 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
54 DEBUG ((DEBUG_INFO, " SlotType "));
55 if (Capability->SlotType == 0x00) {
56 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
57 } else if (Capability->SlotType == 0x01) {
58 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
59 } else if (Capability->SlotType == 0x02) {
60 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
61 } else {
62 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
63 }
64 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
66 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
67 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
68 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
69 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
70 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
71 if (Capability->TimerCount == 0) {
72 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
73 } else {
74 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
75 }
76 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
77 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
78 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
79 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
80 return;
81 }
82
83 /**
84 Read SlotInfo register from SD/MMC host controller pci config space.
85
86 @param[in] PciIo The PCI IO protocol instance.
87 @param[out] FirstBar The buffer to store the first BAR value.
88 @param[out] SlotNum The buffer to store the supported slot number.
89
90 @retval EFI_SUCCESS The operation succeeds.
91 @retval Others The operation fails.
92
93 **/
94 EFI_STATUS
95 EFIAPI
96 SdMmcHcGetSlotInfo (
97 IN EFI_PCI_IO_PROTOCOL *PciIo,
98 OUT UINT8 *FirstBar,
99 OUT UINT8 *SlotNum
100 )
101 {
102 EFI_STATUS Status;
103 SD_MMC_HC_SLOT_INFO SlotInfo;
104
105 Status = PciIo->Pci.Read (
106 PciIo,
107 EfiPciIoWidthUint8,
108 SD_MMC_HC_SLOT_OFFSET,
109 sizeof (SlotInfo),
110 &SlotInfo
111 );
112 if (EFI_ERROR (Status)) {
113 return Status;
114 }
115
116 *FirstBar = SlotInfo.FirstBar;
117 *SlotNum = SlotInfo.SlotNum + 1;
118 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
119 return EFI_SUCCESS;
120 }
121
122 /**
123 Read/Write specified SD/MMC host controller mmio register.
124
125 @param[in] PciIo The PCI IO protocol instance.
126 @param[in] BarIndex The BAR index of the standard PCI Configuration
127 header to use as the base address for the memory
128 operation to perform.
129 @param[in] Offset The offset within the selected BAR to start the
130 memory operation.
131 @param[in] Read A boolean to indicate it's read or write operation.
132 @param[in] Count The width of the mmio register in bytes.
133 Must be 1, 2 , 4 or 8 bytes.
134 @param[in, out] Data For read operations, the destination buffer to store
135 the results. For write operations, the source buffer
136 to write data from. The caller is responsible for
137 having ownership of the data buffer and ensuring its
138 size not less than Count bytes.
139
140 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
141 @retval EFI_SUCCESS The read/write operation succeeds.
142 @retval Others The read/write operation fails.
143
144 **/
145 EFI_STATUS
146 EFIAPI
147 SdMmcHcRwMmio (
148 IN EFI_PCI_IO_PROTOCOL *PciIo,
149 IN UINT8 BarIndex,
150 IN UINT32 Offset,
151 IN BOOLEAN Read,
152 IN UINT8 Count,
153 IN OUT VOID *Data
154 )
155 {
156 EFI_STATUS Status;
157 EFI_PCI_IO_PROTOCOL_WIDTH Width;
158
159 if ((PciIo == NULL) || (Data == NULL)) {
160 return EFI_INVALID_PARAMETER;
161 }
162
163 switch (Count) {
164 case 1:
165 Width = EfiPciIoWidthUint8;
166 break;
167 case 2:
168 Width = EfiPciIoWidthUint16;
169 Count = 1;
170 break;
171 case 4:
172 Width = EfiPciIoWidthUint32;
173 Count = 1;
174 break;
175 case 8:
176 Width = EfiPciIoWidthUint32;
177 Count = 2;
178 break;
179 default:
180 return EFI_INVALID_PARAMETER;
181 }
182
183 if (Read) {
184 Status = PciIo->Mem.Read (
185 PciIo,
186 Width,
187 BarIndex,
188 (UINT64) Offset,
189 Count,
190 Data
191 );
192 } else {
193 Status = PciIo->Mem.Write (
194 PciIo,
195 Width,
196 BarIndex,
197 (UINT64) Offset,
198 Count,
199 Data
200 );
201 }
202
203 return Status;
204 }
205
206 /**
207 Do OR operation with the value of the specified SD/MMC host controller mmio register.
208
209 @param[in] PciIo The PCI IO protocol instance.
210 @param[in] BarIndex The BAR index of the standard PCI Configuration
211 header to use as the base address for the memory
212 operation to perform.
213 @param[in] Offset The offset within the selected BAR to start the
214 memory operation.
215 @param[in] Count The width of the mmio register in bytes.
216 Must be 1, 2 , 4 or 8 bytes.
217 @param[in] OrData The pointer to the data used to do OR operation.
218 The caller is responsible for having ownership of
219 the data buffer and ensuring its size not less than
220 Count bytes.
221
222 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
223 @retval EFI_SUCCESS The OR operation succeeds.
224 @retval Others The OR operation fails.
225
226 **/
227 EFI_STATUS
228 EFIAPI
229 SdMmcHcOrMmio (
230 IN EFI_PCI_IO_PROTOCOL *PciIo,
231 IN UINT8 BarIndex,
232 IN UINT32 Offset,
233 IN UINT8 Count,
234 IN VOID *OrData
235 )
236 {
237 EFI_STATUS Status;
238 UINT64 Data;
239 UINT64 Or;
240
241 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
242 if (EFI_ERROR (Status)) {
243 return Status;
244 }
245
246 if (Count == 1) {
247 Or = *(UINT8*) OrData;
248 } else if (Count == 2) {
249 Or = *(UINT16*) OrData;
250 } else if (Count == 4) {
251 Or = *(UINT32*) OrData;
252 } else if (Count == 8) {
253 Or = *(UINT64*) OrData;
254 } else {
255 return EFI_INVALID_PARAMETER;
256 }
257
258 Data |= Or;
259 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
260
261 return Status;
262 }
263
264 /**
265 Do AND operation with the value of the specified SD/MMC host controller mmio register.
266
267 @param[in] PciIo The PCI IO protocol instance.
268 @param[in] BarIndex The BAR index of the standard PCI Configuration
269 header to use as the base address for the memory
270 operation to perform.
271 @param[in] Offset The offset within the selected BAR to start the
272 memory operation.
273 @param[in] Count The width of the mmio register in bytes.
274 Must be 1, 2 , 4 or 8 bytes.
275 @param[in] AndData The pointer to the data used to do AND operation.
276 The caller is responsible for having ownership of
277 the data buffer and ensuring its size not less than
278 Count bytes.
279
280 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
281 @retval EFI_SUCCESS The AND operation succeeds.
282 @retval Others The AND operation fails.
283
284 **/
285 EFI_STATUS
286 EFIAPI
287 SdMmcHcAndMmio (
288 IN EFI_PCI_IO_PROTOCOL *PciIo,
289 IN UINT8 BarIndex,
290 IN UINT32 Offset,
291 IN UINT8 Count,
292 IN VOID *AndData
293 )
294 {
295 EFI_STATUS Status;
296 UINT64 Data;
297 UINT64 And;
298
299 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
300 if (EFI_ERROR (Status)) {
301 return Status;
302 }
303
304 if (Count == 1) {
305 And = *(UINT8*) AndData;
306 } else if (Count == 2) {
307 And = *(UINT16*) AndData;
308 } else if (Count == 4) {
309 And = *(UINT32*) AndData;
310 } else if (Count == 8) {
311 And = *(UINT64*) AndData;
312 } else {
313 return EFI_INVALID_PARAMETER;
314 }
315
316 Data &= And;
317 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
318
319 return Status;
320 }
321
322 /**
323 Wait for the value of the specified MMIO register set to the test value.
324
325 @param[in] PciIo The PCI IO protocol instance.
326 @param[in] BarIndex The BAR index of the standard PCI Configuration
327 header to use as the base address for the memory
328 operation to perform.
329 @param[in] Offset The offset within the selected BAR to start the
330 memory operation.
331 @param[in] Count The width of the mmio register in bytes.
332 Must be 1, 2, 4 or 8 bytes.
333 @param[in] MaskValue The mask value of memory.
334 @param[in] TestValue The test value of memory.
335
336 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
337 @retval EFI_SUCCESS The MMIO register has expected value.
338 @retval Others The MMIO operation fails.
339
340 **/
341 EFI_STATUS
342 EFIAPI
343 SdMmcHcCheckMmioSet (
344 IN EFI_PCI_IO_PROTOCOL *PciIo,
345 IN UINT8 BarIndex,
346 IN UINT32 Offset,
347 IN UINT8 Count,
348 IN UINT64 MaskValue,
349 IN UINT64 TestValue
350 )
351 {
352 EFI_STATUS Status;
353 UINT64 Value;
354
355 //
356 // Access PCI MMIO space to see if the value is the tested one.
357 //
358 Value = 0;
359 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
360 if (EFI_ERROR (Status)) {
361 return Status;
362 }
363
364 Value &= MaskValue;
365
366 if (Value == TestValue) {
367 return EFI_SUCCESS;
368 }
369
370 return EFI_NOT_READY;
371 }
372
373 /**
374 Wait for the value of the specified MMIO register set to the test value.
375
376 @param[in] PciIo The PCI IO protocol instance.
377 @param[in] BarIndex The BAR index of the standard PCI Configuration
378 header to use as the base address for the memory
379 operation to perform.
380 @param[in] Offset The offset within the selected BAR to start the
381 memory operation.
382 @param[in] Count The width of the mmio register in bytes.
383 Must be 1, 2, 4 or 8 bytes.
384 @param[in] MaskValue The mask value of memory.
385 @param[in] TestValue The test value of memory.
386 @param[in] Timeout The time out value for wait memory set, uses 1
387 microsecond as a unit.
388
389 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
390 range.
391 @retval EFI_SUCCESS The MMIO register has expected value.
392 @retval Others The MMIO operation fails.
393
394 **/
395 EFI_STATUS
396 EFIAPI
397 SdMmcHcWaitMmioSet (
398 IN EFI_PCI_IO_PROTOCOL *PciIo,
399 IN UINT8 BarIndex,
400 IN UINT32 Offset,
401 IN UINT8 Count,
402 IN UINT64 MaskValue,
403 IN UINT64 TestValue,
404 IN UINT64 Timeout
405 )
406 {
407 EFI_STATUS Status;
408 BOOLEAN InfiniteWait;
409
410 if (Timeout == 0) {
411 InfiniteWait = TRUE;
412 } else {
413 InfiniteWait = FALSE;
414 }
415
416 while (InfiniteWait || (Timeout > 0)) {
417 Status = SdMmcHcCheckMmioSet (
418 PciIo,
419 BarIndex,
420 Offset,
421 Count,
422 MaskValue,
423 TestValue
424 );
425 if (Status != EFI_NOT_READY) {
426 return Status;
427 }
428
429 //
430 // Stall for 1 microsecond.
431 //
432 gBS->Stall (1);
433
434 Timeout--;
435 }
436
437 return EFI_TIMEOUT;
438 }
439
440 /**
441 Get the controller version information from the specified slot.
442
443 @param[in] PciIo The PCI IO protocol instance.
444 @param[in] Slot The slot number of the SD card to send the command to.
445 @param[out] Version The buffer to store the version information.
446
447 @retval EFI_SUCCESS The operation executes successfully.
448 @retval Others The operation fails.
449
450 **/
451 EFI_STATUS
452 SdMmcHcGetControllerVersion (
453 IN EFI_PCI_IO_PROTOCOL *PciIo,
454 IN UINT8 Slot,
455 OUT UINT16 *Version
456 )
457 {
458 EFI_STATUS Status;
459
460 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);
461 if (EFI_ERROR (Status)) {
462 return Status;
463 }
464
465 *Version &= 0xFF;
466
467 return EFI_SUCCESS;
468 }
469
470 /**
471 Software reset the specified SD/MMC host controller and enable all interrupts.
472
473 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
474 @param[in] Slot The slot number of the SD card to send the command to.
475
476 @retval EFI_SUCCESS The software reset executes successfully.
477 @retval Others The software reset fails.
478
479 **/
480 EFI_STATUS
481 SdMmcHcReset (
482 IN SD_MMC_HC_PRIVATE_DATA *Private,
483 IN UINT8 Slot
484 )
485 {
486 EFI_STATUS Status;
487 UINT8 SwReset;
488 EFI_PCI_IO_PROTOCOL *PciIo;
489
490 //
491 // Notify the SD/MMC override protocol that we are about to reset
492 // the SD/MMC host controller.
493 //
494 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
495 Status = mOverride->NotifyPhase (
496 Private->ControllerHandle,
497 Slot,
498 EdkiiSdMmcResetPre,
499 NULL);
500 if (EFI_ERROR (Status)) {
501 DEBUG ((DEBUG_WARN,
502 "%a: SD/MMC pre reset notifier callback failed - %r\n",
503 __FUNCTION__, Status));
504 return Status;
505 }
506 }
507
508 PciIo = Private->PciIo;
509 SwReset = BIT0;
510 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
511
512 if (EFI_ERROR (Status)) {
513 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
514 return Status;
515 }
516
517 Status = SdMmcHcWaitMmioSet (
518 PciIo,
519 Slot,
520 SD_MMC_HC_SW_RST,
521 sizeof (SwReset),
522 BIT0,
523 0x00,
524 SD_MMC_HC_GENERIC_TIMEOUT
525 );
526 if (EFI_ERROR (Status)) {
527 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
528 return Status;
529 }
530
531 //
532 // Enable all interrupt after reset all.
533 //
534 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
535 if (EFI_ERROR (Status)) {
536 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
537 Status));
538 return Status;
539 }
540
541 //
542 // Notify the SD/MMC override protocol that we have just reset
543 // the SD/MMC host controller.
544 //
545 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
546 Status = mOverride->NotifyPhase (
547 Private->ControllerHandle,
548 Slot,
549 EdkiiSdMmcResetPost,
550 NULL);
551 if (EFI_ERROR (Status)) {
552 DEBUG ((DEBUG_WARN,
553 "%a: SD/MMC post reset notifier callback failed - %r\n",
554 __FUNCTION__, Status));
555 }
556 }
557
558 return Status;
559 }
560
561 /**
562 Set all interrupt status bits in Normal and Error Interrupt Status Enable
563 register.
564
565 @param[in] PciIo The PCI IO protocol instance.
566 @param[in] Slot The slot number of the SD card to send the command to.
567
568 @retval EFI_SUCCESS The operation executes successfully.
569 @retval Others The operation fails.
570
571 **/
572 EFI_STATUS
573 SdMmcHcEnableInterrupt (
574 IN EFI_PCI_IO_PROTOCOL *PciIo,
575 IN UINT8 Slot
576 )
577 {
578 EFI_STATUS Status;
579 UINT16 IntStatus;
580
581 //
582 // Enable all bits in Error Interrupt Status Enable Register
583 //
584 IntStatus = 0xFFFF;
585 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
586 if (EFI_ERROR (Status)) {
587 return Status;
588 }
589 //
590 // Enable all bits in Normal Interrupt Status Enable Register
591 //
592 IntStatus = 0xFFFF;
593 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
594
595 return Status;
596 }
597
598 /**
599 Get the capability data from the specified slot.
600
601 @param[in] PciIo The PCI IO protocol instance.
602 @param[in] Slot The slot number of the SD card to send the command to.
603 @param[out] Capability The buffer to store the capability data.
604
605 @retval EFI_SUCCESS The operation executes successfully.
606 @retval Others The operation fails.
607
608 **/
609 EFI_STATUS
610 SdMmcHcGetCapability (
611 IN EFI_PCI_IO_PROTOCOL *PciIo,
612 IN UINT8 Slot,
613 OUT SD_MMC_HC_SLOT_CAP *Capability
614 )
615 {
616 EFI_STATUS Status;
617 UINT64 Cap;
618
619 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
620 if (EFI_ERROR (Status)) {
621 return Status;
622 }
623
624 CopyMem (Capability, &Cap, sizeof (Cap));
625
626 return EFI_SUCCESS;
627 }
628
629 /**
630 Get the maximum current capability data from the specified slot.
631
632 @param[in] PciIo The PCI IO protocol instance.
633 @param[in] Slot The slot number of the SD card to send the command to.
634 @param[out] MaxCurrent The buffer to store the maximum current capability data.
635
636 @retval EFI_SUCCESS The operation executes successfully.
637 @retval Others The operation fails.
638
639 **/
640 EFI_STATUS
641 SdMmcHcGetMaxCurrent (
642 IN EFI_PCI_IO_PROTOCOL *PciIo,
643 IN UINT8 Slot,
644 OUT UINT64 *MaxCurrent
645 )
646 {
647 EFI_STATUS Status;
648
649 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
650
651 return Status;
652 }
653
654 /**
655 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
656 slot.
657
658 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
659
660 @param[in] PciIo The PCI IO protocol instance.
661 @param[in] Slot The slot number of the SD card to send the command to.
662 @param[out] MediaPresent The pointer to the media present boolean value.
663
664 @retval EFI_SUCCESS There is no media change happened.
665 @retval EFI_MEDIA_CHANGED There is media change happened.
666 @retval Others The detection fails.
667
668 **/
669 EFI_STATUS
670 SdMmcHcCardDetect (
671 IN EFI_PCI_IO_PROTOCOL *PciIo,
672 IN UINT8 Slot,
673 OUT BOOLEAN *MediaPresent
674 )
675 {
676 EFI_STATUS Status;
677 UINT16 Data;
678 UINT32 PresentState;
679
680 //
681 // Check Present State Register to see if there is a card presented.
682 //
683 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
684 if (EFI_ERROR (Status)) {
685 return Status;
686 }
687
688 if ((PresentState & BIT16) != 0) {
689 *MediaPresent = TRUE;
690 } else {
691 *MediaPresent = FALSE;
692 }
693
694 //
695 // Check Normal Interrupt Status Register
696 //
697 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
698 if (EFI_ERROR (Status)) {
699 return Status;
700 }
701
702 if ((Data & (BIT6 | BIT7)) != 0) {
703 //
704 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
705 //
706 Data &= BIT6 | BIT7;
707 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
708 if (EFI_ERROR (Status)) {
709 return Status;
710 }
711
712 return EFI_MEDIA_CHANGED;
713 }
714
715 return EFI_SUCCESS;
716 }
717
718 /**
719 Stop SD/MMC card clock.
720
721 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
722
723 @param[in] PciIo The PCI IO protocol instance.
724 @param[in] Slot The slot number of the SD card to send the command to.
725
726 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
727 @retval Others Fail to stop SD/MMC clock.
728
729 **/
730 EFI_STATUS
731 SdMmcHcStopClock (
732 IN EFI_PCI_IO_PROTOCOL *PciIo,
733 IN UINT8 Slot
734 )
735 {
736 EFI_STATUS Status;
737 UINT32 PresentState;
738 UINT16 ClockCtrl;
739
740 //
741 // Ensure no SD transactions are occurring on the SD Bus by
742 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
743 // in the Present State register to be 0.
744 //
745 Status = SdMmcHcWaitMmioSet (
746 PciIo,
747 Slot,
748 SD_MMC_HC_PRESENT_STATE,
749 sizeof (PresentState),
750 BIT0 | BIT1,
751 0,
752 SD_MMC_HC_GENERIC_TIMEOUT
753 );
754 if (EFI_ERROR (Status)) {
755 return Status;
756 }
757
758 //
759 // Set SD Clock Enable in the Clock Control register to 0
760 //
761 ClockCtrl = (UINT16)~BIT2;
762 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
763
764 return Status;
765 }
766
767 /**
768 SD/MMC card clock supply.
769
770 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
771
772 @param[in] PciIo The PCI IO protocol instance.
773 @param[in] Slot The slot number of the SD card to send the command to.
774 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
775 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
776 @param[in] ControllerVer The version of host controller.
777
778 @retval EFI_SUCCESS The clock is supplied successfully.
779 @retval Others The clock isn't supplied successfully.
780
781 **/
782 EFI_STATUS
783 SdMmcHcClockSupply (
784 IN EFI_PCI_IO_PROTOCOL *PciIo,
785 IN UINT8 Slot,
786 IN UINT64 ClockFreq,
787 IN UINT32 BaseClkFreq,
788 IN UINT16 ControllerVer
789 )
790 {
791 EFI_STATUS Status;
792 UINT32 SettingFreq;
793 UINT32 Divisor;
794 UINT32 Remainder;
795 UINT16 ClockCtrl;
796
797 //
798 // Calculate a divisor for SD clock frequency
799 //
800 ASSERT (BaseClkFreq != 0);
801
802 if (ClockFreq == 0) {
803 return EFI_INVALID_PARAMETER;
804 }
805
806 if (ClockFreq > (BaseClkFreq * 1000)) {
807 ClockFreq = BaseClkFreq * 1000;
808 }
809
810 //
811 // Calculate the divisor of base frequency.
812 //
813 Divisor = 0;
814 SettingFreq = BaseClkFreq * 1000;
815 while (ClockFreq < SettingFreq) {
816 Divisor++;
817
818 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
819 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
820 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
821 break;
822 }
823 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
824 SettingFreq ++;
825 }
826 }
827
828 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
829
830 //
831 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
832 //
833 if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&
834 (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {
835 ASSERT (Divisor <= 0x3FF);
836 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
837 } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||
838 (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {
839 //
840 // Only the most significant bit can be used as divisor.
841 //
842 if (((Divisor - 1) & Divisor) != 0) {
843 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
844 }
845 ASSERT (Divisor <= 0x80);
846 ClockCtrl = (Divisor & 0xFF) << 8;
847 } else {
848 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
849 return EFI_UNSUPPORTED;
850 }
851
852 //
853 // Stop bus clock at first
854 //
855 Status = SdMmcHcStopClock (PciIo, Slot);
856 if (EFI_ERROR (Status)) {
857 return Status;
858 }
859
860 //
861 // Supply clock frequency with specified divisor
862 //
863 ClockCtrl |= BIT0;
864 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
865 if (EFI_ERROR (Status)) {
866 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
867 return Status;
868 }
869
870 //
871 // Wait Internal Clock Stable in the Clock Control register to be 1
872 //
873 Status = SdMmcHcWaitMmioSet (
874 PciIo,
875 Slot,
876 SD_MMC_HC_CLOCK_CTRL,
877 sizeof (ClockCtrl),
878 BIT1,
879 BIT1,
880 SD_MMC_HC_GENERIC_TIMEOUT
881 );
882 if (EFI_ERROR (Status)) {
883 return Status;
884 }
885
886 //
887 // Set SD Clock Enable in the Clock Control register to 1
888 //
889 ClockCtrl = BIT2;
890 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
891
892 return Status;
893 }
894
895 /**
896 SD/MMC bus power control.
897
898 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
899
900 @param[in] PciIo The PCI IO protocol instance.
901 @param[in] Slot The slot number of the SD card to send the command to.
902 @param[in] PowerCtrl The value setting to the power control register.
903
904 @retval TRUE There is a SD/MMC card attached.
905 @retval FALSE There is no a SD/MMC card attached.
906
907 **/
908 EFI_STATUS
909 SdMmcHcPowerControl (
910 IN EFI_PCI_IO_PROTOCOL *PciIo,
911 IN UINT8 Slot,
912 IN UINT8 PowerCtrl
913 )
914 {
915 EFI_STATUS Status;
916
917 //
918 // Clr SD Bus Power
919 //
920 PowerCtrl &= (UINT8)~BIT0;
921 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
922 if (EFI_ERROR (Status)) {
923 return Status;
924 }
925
926 //
927 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
928 //
929 PowerCtrl |= BIT0;
930 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
931
932 return Status;
933 }
934
935 /**
936 Set the SD/MMC bus width.
937
938 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
939
940 @param[in] PciIo The PCI IO protocol instance.
941 @param[in] Slot The slot number of the SD card to send the command to.
942 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
943
944 @retval EFI_SUCCESS The bus width is set successfully.
945 @retval Others The bus width isn't set successfully.
946
947 **/
948 EFI_STATUS
949 SdMmcHcSetBusWidth (
950 IN EFI_PCI_IO_PROTOCOL *PciIo,
951 IN UINT8 Slot,
952 IN UINT16 BusWidth
953 )
954 {
955 EFI_STATUS Status;
956 UINT8 HostCtrl1;
957
958 if (BusWidth == 1) {
959 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
960 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
961 } else if (BusWidth == 4) {
962 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
963 if (EFI_ERROR (Status)) {
964 return Status;
965 }
966 HostCtrl1 |= BIT1;
967 HostCtrl1 &= (UINT8)~BIT5;
968 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
969 } else if (BusWidth == 8) {
970 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
971 if (EFI_ERROR (Status)) {
972 return Status;
973 }
974 HostCtrl1 &= (UINT8)~BIT1;
975 HostCtrl1 |= BIT5;
976 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
977 } else {
978 ASSERT (FALSE);
979 return EFI_INVALID_PARAMETER;
980 }
981
982 return Status;
983 }
984
985 /**
986 Configure V4 controller enhancements at initialization.
987
988 @param[in] PciIo The PCI IO protocol instance.
989 @param[in] Slot The slot number of the SD card to send the command to.
990 @param[in] Capability The capability of the slot.
991 @param[in] ControllerVer The version of host controller.
992
993 @retval EFI_SUCCESS The clock is supplied successfully.
994
995 **/
996 EFI_STATUS
997 SdMmcHcInitV4Enhancements (
998 IN EFI_PCI_IO_PROTOCOL *PciIo,
999 IN UINT8 Slot,
1000 IN SD_MMC_HC_SLOT_CAP Capability,
1001 IN UINT16 ControllerVer
1002 )
1003 {
1004 EFI_STATUS Status;
1005 UINT16 HostCtrl2;
1006
1007 //
1008 // Check if controller version V4 or higher
1009 //
1010 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
1011 HostCtrl2 = SD_MMC_HC_V4_EN;
1012 //
1013 // Check if controller version V4.0
1014 //
1015 if (ControllerVer == SD_MMC_HC_CTRL_VER_400) {
1016 //
1017 // Check if 64bit support is available
1018 //
1019 if (Capability.SysBus64V3 != 0) {
1020 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1021 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1022 }
1023 }
1024 //
1025 // Check if controller version V4.10 or higher
1026 //
1027 else if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {
1028 //
1029 // Check if 64bit support is available
1030 //
1031 if (Capability.SysBus64V4 != 0) {
1032 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1033 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1034 }
1035 HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;
1036 DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));
1037 }
1038 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1039 if (EFI_ERROR (Status)) {
1040 return Status;
1041 }
1042 }
1043
1044 return EFI_SUCCESS;
1045 }
1046
1047 /**
1048 Supply SD/MMC card with lowest clock frequency at initialization.
1049
1050 @param[in] PciIo The PCI IO protocol instance.
1051 @param[in] Slot The slot number of the SD card to send the command to.
1052 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
1053 @param[in] ControllerVer The version of host controller.
1054
1055 @retval EFI_SUCCESS The clock is supplied successfully.
1056 @retval Others The clock isn't supplied successfully.
1057
1058 **/
1059 EFI_STATUS
1060 SdMmcHcInitClockFreq (
1061 IN EFI_PCI_IO_PROTOCOL *PciIo,
1062 IN UINT8 Slot,
1063 IN UINT32 BaseClkFreq,
1064 IN UINT16 ControllerVer
1065 )
1066 {
1067 EFI_STATUS Status;
1068 UINT32 InitFreq;
1069
1070 //
1071 // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
1072 // the Capability Register 1 can be zero, which means a need for obtaining
1073 // the clock frequency via another method. Fail in case it is not updated
1074 // by SW at this point.
1075 //
1076 if (BaseClkFreq == 0) {
1077 //
1078 // Don't support get Base Clock Frequency information via another method
1079 //
1080 return EFI_UNSUPPORTED;
1081 }
1082 //
1083 // Supply 400KHz clock frequency at initialization phase.
1084 //
1085 InitFreq = 400;
1086 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq, ControllerVer);
1087 return Status;
1088 }
1089
1090 /**
1091 Supply SD/MMC card with maximum voltage at initialization.
1092
1093 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1094
1095 @param[in] PciIo The PCI IO protocol instance.
1096 @param[in] Slot The slot number of the SD card to send the command to.
1097 @param[in] Capability The capability of the slot.
1098
1099 @retval EFI_SUCCESS The voltage is supplied successfully.
1100 @retval Others The voltage isn't supplied successfully.
1101
1102 **/
1103 EFI_STATUS
1104 SdMmcHcInitPowerVoltage (
1105 IN EFI_PCI_IO_PROTOCOL *PciIo,
1106 IN UINT8 Slot,
1107 IN SD_MMC_HC_SLOT_CAP Capability
1108 )
1109 {
1110 EFI_STATUS Status;
1111 UINT8 MaxVoltage;
1112 UINT8 HostCtrl2;
1113
1114 //
1115 // Calculate supported maximum voltage according to SD Bus Voltage Select
1116 //
1117 if (Capability.Voltage33 != 0) {
1118 //
1119 // Support 3.3V
1120 //
1121 MaxVoltage = 0x0E;
1122 } else if (Capability.Voltage30 != 0) {
1123 //
1124 // Support 3.0V
1125 //
1126 MaxVoltage = 0x0C;
1127 } else if (Capability.Voltage18 != 0) {
1128 //
1129 // Support 1.8V
1130 //
1131 MaxVoltage = 0x0A;
1132 HostCtrl2 = BIT3;
1133 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1134 gBS->Stall (5000);
1135 if (EFI_ERROR (Status)) {
1136 return Status;
1137 }
1138 } else {
1139 ASSERT (FALSE);
1140 return EFI_DEVICE_ERROR;
1141 }
1142
1143 //
1144 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1145 //
1146 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1147
1148 return Status;
1149 }
1150
1151 /**
1152 Initialize the Timeout Control register with most conservative value at initialization.
1153
1154 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1155
1156 @param[in] PciIo The PCI IO protocol instance.
1157 @param[in] Slot The slot number of the SD card to send the command to.
1158
1159 @retval EFI_SUCCESS The timeout control register is configured successfully.
1160 @retval Others The timeout control register isn't configured successfully.
1161
1162 **/
1163 EFI_STATUS
1164 SdMmcHcInitTimeoutCtrl (
1165 IN EFI_PCI_IO_PROTOCOL *PciIo,
1166 IN UINT8 Slot
1167 )
1168 {
1169 EFI_STATUS Status;
1170 UINT8 Timeout;
1171
1172 Timeout = 0x0E;
1173 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1174
1175 return Status;
1176 }
1177
1178 /**
1179 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1180 at initialization.
1181
1182 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1183 @param[in] Slot The slot number of the SD card to send the command to.
1184
1185 @retval EFI_SUCCESS The host controller is initialized successfully.
1186 @retval Others The host controller isn't initialized successfully.
1187
1188 **/
1189 EFI_STATUS
1190 SdMmcHcInitHost (
1191 IN SD_MMC_HC_PRIVATE_DATA *Private,
1192 IN UINT8 Slot
1193 )
1194 {
1195 EFI_STATUS Status;
1196 EFI_PCI_IO_PROTOCOL *PciIo;
1197 SD_MMC_HC_SLOT_CAP Capability;
1198
1199 //
1200 // Notify the SD/MMC override protocol that we are about to initialize
1201 // the SD/MMC host controller.
1202 //
1203 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1204 Status = mOverride->NotifyPhase (
1205 Private->ControllerHandle,
1206 Slot,
1207 EdkiiSdMmcInitHostPre,
1208 NULL);
1209 if (EFI_ERROR (Status)) {
1210 DEBUG ((DEBUG_WARN,
1211 "%a: SD/MMC pre init notifier callback failed - %r\n",
1212 __FUNCTION__, Status));
1213 return Status;
1214 }
1215 }
1216
1217 PciIo = Private->PciIo;
1218 Capability = Private->Capability[Slot];
1219
1220 Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);
1221 if (EFI_ERROR (Status)) {
1222 return Status;
1223 }
1224
1225 Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
1226 if (EFI_ERROR (Status)) {
1227 return Status;
1228 }
1229
1230 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1231 if (EFI_ERROR (Status)) {
1232 return Status;
1233 }
1234
1235 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1236 if (EFI_ERROR (Status)) {
1237 return Status;
1238 }
1239
1240 //
1241 // Notify the SD/MMC override protocol that we are have just initialized
1242 // the SD/MMC host controller.
1243 //
1244 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1245 Status = mOverride->NotifyPhase (
1246 Private->ControllerHandle,
1247 Slot,
1248 EdkiiSdMmcInitHostPost,
1249 NULL);
1250 if (EFI_ERROR (Status)) {
1251 DEBUG ((DEBUG_WARN,
1252 "%a: SD/MMC post init notifier callback failed - %r\n",
1253 __FUNCTION__, Status));
1254 }
1255 }
1256 return Status;
1257 }
1258
1259 /**
1260 Set SD Host Controler control 2 registry according to selected speed.
1261
1262 @param[in] ControllerHandle The handle of the controller.
1263 @param[in] PciIo The PCI IO protocol instance.
1264 @param[in] Slot The slot number of the SD card to send the command to.
1265 @param[in] Timing The timing to select.
1266
1267 @retval EFI_SUCCESS The timing is set successfully.
1268 @retval Others The timing isn't set successfully.
1269 **/
1270 EFI_STATUS
1271 SdMmcHcUhsSignaling (
1272 IN EFI_HANDLE ControllerHandle,
1273 IN EFI_PCI_IO_PROTOCOL *PciIo,
1274 IN UINT8 Slot,
1275 IN SD_MMC_BUS_MODE Timing
1276 )
1277 {
1278 EFI_STATUS Status;
1279 UINT8 HostCtrl2;
1280
1281 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
1282 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1283 if (EFI_ERROR (Status)) {
1284 return Status;
1285 }
1286
1287 switch (Timing) {
1288 case SdMmcUhsSdr12:
1289 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1290 break;
1291 case SdMmcUhsSdr25:
1292 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1293 break;
1294 case SdMmcUhsSdr50:
1295 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1296 break;
1297 case SdMmcUhsSdr104:
1298 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1299 break;
1300 case SdMmcUhsDdr50:
1301 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1302 break;
1303 case SdMmcMmcLegacy:
1304 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1305 break;
1306 case SdMmcMmcHsSdr:
1307 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1308 break;
1309 case SdMmcMmcHsDdr:
1310 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1311 break;
1312 case SdMmcMmcHs200:
1313 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1314 break;
1315 case SdMmcMmcHs400:
1316 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1317 break;
1318 default:
1319 HostCtrl2 = 0;
1320 break;
1321 }
1322 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1323 if (EFI_ERROR (Status)) {
1324 return Status;
1325 }
1326
1327 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1328 Status = mOverride->NotifyPhase (
1329 ControllerHandle,
1330 Slot,
1331 EdkiiSdMmcUhsSignaling,
1332 &Timing
1333 );
1334 if (EFI_ERROR (Status)) {
1335 DEBUG ((
1336 DEBUG_ERROR,
1337 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1338 __FUNCTION__,
1339 Status
1340 ));
1341 return Status;
1342 }
1343 }
1344
1345 return EFI_SUCCESS;
1346 }
1347
1348 /**
1349 Turn on/off LED.
1350
1351 @param[in] PciIo The PCI IO protocol instance.
1352 @param[in] Slot The slot number of the SD card to send the command to.
1353 @param[in] On The boolean to turn on/off LED.
1354
1355 @retval EFI_SUCCESS The LED is turned on/off successfully.
1356 @retval Others The LED isn't turned on/off successfully.
1357
1358 **/
1359 EFI_STATUS
1360 SdMmcHcLedOnOff (
1361 IN EFI_PCI_IO_PROTOCOL *PciIo,
1362 IN UINT8 Slot,
1363 IN BOOLEAN On
1364 )
1365 {
1366 EFI_STATUS Status;
1367 UINT8 HostCtrl1;
1368
1369 if (On) {
1370 HostCtrl1 = BIT0;
1371 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1372 } else {
1373 HostCtrl1 = (UINT8)~BIT0;
1374 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1375 }
1376
1377 return Status;
1378 }
1379
1380 /**
1381 Build ADMA descriptor table for transfer.
1382
1383 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1384
1385 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1386 @param[in] ControllerVer The version of host controller.
1387
1388 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1389 @retval Others The ADMA descriptor table isn't created successfully.
1390
1391 **/
1392 EFI_STATUS
1393 BuildAdmaDescTable (
1394 IN SD_MMC_HC_TRB *Trb,
1395 IN UINT16 ControllerVer
1396 )
1397 {
1398 EFI_PHYSICAL_ADDRESS Data;
1399 UINT64 DataLen;
1400 UINT64 Entries;
1401 UINT32 Index;
1402 UINT64 Remaining;
1403 UINT64 Address;
1404 UINTN TableSize;
1405 EFI_PCI_IO_PROTOCOL *PciIo;
1406 EFI_STATUS Status;
1407 UINTN Bytes;
1408 UINT32 AdmaMaxDataPerLine;
1409 UINT32 DescSize;
1410 VOID *AdmaDesc;
1411
1412 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;
1413 DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);
1414 AdmaDesc = NULL;
1415
1416 Data = Trb->DataPhy;
1417 DataLen = Trb->DataLen;
1418 PciIo = Trb->Private->PciIo;
1419
1420 //
1421 // Check for valid ranges in 32bit ADMA Descriptor Table
1422 //
1423 if ((Trb->Mode == SdMmcAdma32bMode) &&
1424 ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {
1425 return EFI_INVALID_PARAMETER;
1426 }
1427 //
1428 // Check address field alignment
1429 //
1430 if (Trb->Mode != SdMmcAdma32bMode) {
1431 //
1432 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1433 //
1434 if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {
1435 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));
1436 }
1437 } else {
1438 //
1439 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1440 //
1441 if ((Data & (BIT0 | BIT1)) != 0) {
1442 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1443 }
1444 }
1445
1446 //
1447 // Configure 64b ADMA.
1448 //
1449 if (Trb->Mode == SdMmcAdma64bV3Mode) {
1450 DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);
1451 }else if (Trb->Mode == SdMmcAdma64bV4Mode) {
1452 DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);
1453 }
1454 //
1455 // Configure 26b data length.
1456 //
1457 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1458 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;
1459 }
1460
1461 Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
1462 TableSize = (UINTN)MultU64x32 (Entries, DescSize);
1463 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1464 Status = PciIo->AllocateBuffer (
1465 PciIo,
1466 AllocateAnyPages,
1467 EfiBootServicesData,
1468 EFI_SIZE_TO_PAGES (TableSize),
1469 (VOID **)&AdmaDesc,
1470 0
1471 );
1472 if (EFI_ERROR (Status)) {
1473 return EFI_OUT_OF_RESOURCES;
1474 }
1475 ZeroMem (AdmaDesc, TableSize);
1476 Bytes = TableSize;
1477 Status = PciIo->Map (
1478 PciIo,
1479 EfiPciIoOperationBusMasterCommonBuffer,
1480 AdmaDesc,
1481 &Bytes,
1482 &Trb->AdmaDescPhy,
1483 &Trb->AdmaMap
1484 );
1485
1486 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1487 //
1488 // Map error or unable to map the whole RFis buffer into a contiguous region.
1489 //
1490 PciIo->FreeBuffer (
1491 PciIo,
1492 EFI_SIZE_TO_PAGES (TableSize),
1493 AdmaDesc
1494 );
1495 return EFI_OUT_OF_RESOURCES;
1496 }
1497
1498 if ((Trb->Mode == SdMmcAdma32bMode) &&
1499 (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1500 //
1501 // The ADMA doesn't support 64bit addressing.
1502 //
1503 PciIo->Unmap (
1504 PciIo,
1505 Trb->AdmaMap
1506 );
1507 PciIo->FreeBuffer (
1508 PciIo,
1509 EFI_SIZE_TO_PAGES (TableSize),
1510 AdmaDesc
1511 );
1512 return EFI_DEVICE_ERROR;
1513 }
1514
1515 Remaining = DataLen;
1516 Address = Data;
1517 if (Trb->Mode == SdMmcAdma32bMode) {
1518 Trb->Adma32Desc = AdmaDesc;
1519 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1520 Trb->Adma64V3Desc = AdmaDesc;
1521 } else {
1522 Trb->Adma64V4Desc = AdmaDesc;
1523 }
1524
1525 for (Index = 0; Index < Entries; Index++) {
1526 if (Trb->Mode == SdMmcAdma32bMode) {
1527 if (Remaining <= AdmaMaxDataPerLine) {
1528 Trb->Adma32Desc[Index].Valid = 1;
1529 Trb->Adma32Desc[Index].Act = 2;
1530 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1531 Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1532 }
1533 Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1534 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1535 break;
1536 } else {
1537 Trb->Adma32Desc[Index].Valid = 1;
1538 Trb->Adma32Desc[Index].Act = 2;
1539 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1540 Trb->Adma32Desc[Index].UpperLength = 0;
1541 }
1542 Trb->Adma32Desc[Index].LowerLength = 0;
1543 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1544 }
1545 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1546 if (Remaining <= AdmaMaxDataPerLine) {
1547 Trb->Adma64V3Desc[Index].Valid = 1;
1548 Trb->Adma64V3Desc[Index].Act = 2;
1549 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1550 Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1551 }
1552 Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1553 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1554 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1555 break;
1556 } else {
1557 Trb->Adma64V3Desc[Index].Valid = 1;
1558 Trb->Adma64V3Desc[Index].Act = 2;
1559 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1560 Trb->Adma64V3Desc[Index].UpperLength = 0;
1561 }
1562 Trb->Adma64V3Desc[Index].LowerLength = 0;
1563 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1564 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1565 }
1566 } else {
1567 if (Remaining <= AdmaMaxDataPerLine) {
1568 Trb->Adma64V4Desc[Index].Valid = 1;
1569 Trb->Adma64V4Desc[Index].Act = 2;
1570 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1571 Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1572 }
1573 Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1574 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1575 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1576 break;
1577 } else {
1578 Trb->Adma64V4Desc[Index].Valid = 1;
1579 Trb->Adma64V4Desc[Index].Act = 2;
1580 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1581 Trb->Adma64V4Desc[Index].UpperLength = 0;
1582 }
1583 Trb->Adma64V4Desc[Index].LowerLength = 0;
1584 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1585 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1586 }
1587 }
1588
1589 Remaining -= AdmaMaxDataPerLine;
1590 Address += AdmaMaxDataPerLine;
1591 }
1592
1593 //
1594 // Set the last descriptor line as end of descriptor table
1595 //
1596 if (Trb->Mode == SdMmcAdma32bMode) {
1597 Trb->Adma32Desc[Index].End = 1;
1598 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1599 Trb->Adma64V3Desc[Index].End = 1;
1600 } else {
1601 Trb->Adma64V4Desc[Index].End = 1;
1602 }
1603 return EFI_SUCCESS;
1604 }
1605
1606 /**
1607 Create a new TRB for the SD/MMC cmd request.
1608
1609 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1610 @param[in] Slot The slot number of the SD card to send the command to.
1611 @param[in] Packet A pointer to the SD command data structure.
1612 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1613 not NULL, then nonblocking I/O is performed, and Event
1614 will be signaled when the Packet completes.
1615
1616 @return Created Trb or NULL.
1617
1618 **/
1619 SD_MMC_HC_TRB *
1620 SdMmcCreateTrb (
1621 IN SD_MMC_HC_PRIVATE_DATA *Private,
1622 IN UINT8 Slot,
1623 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1624 IN EFI_EVENT Event
1625 )
1626 {
1627 SD_MMC_HC_TRB *Trb;
1628 EFI_STATUS Status;
1629 EFI_TPL OldTpl;
1630 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1631 EFI_PCI_IO_PROTOCOL *PciIo;
1632 UINTN MapLength;
1633
1634 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1635 if (Trb == NULL) {
1636 return NULL;
1637 }
1638
1639 Trb->Signature = SD_MMC_HC_TRB_SIG;
1640 Trb->Slot = Slot;
1641 Trb->BlockSize = 0x200;
1642 Trb->Packet = Packet;
1643 Trb->Event = Event;
1644 Trb->Started = FALSE;
1645 Trb->Timeout = Packet->Timeout;
1646 Trb->Private = Private;
1647
1648 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1649 Trb->Data = Packet->InDataBuffer;
1650 Trb->DataLen = Packet->InTransferLength;
1651 Trb->Read = TRUE;
1652 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1653 Trb->Data = Packet->OutDataBuffer;
1654 Trb->DataLen = Packet->OutTransferLength;
1655 Trb->Read = FALSE;
1656 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1657 Trb->Data = NULL;
1658 Trb->DataLen = 0;
1659 } else {
1660 goto Error;
1661 }
1662
1663 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1664 Trb->BlockSize = (UINT16)Trb->DataLen;
1665 }
1666
1667 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1668 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1669 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1670 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1671 Trb->Mode = SdMmcPioMode;
1672 } else {
1673 if (Trb->Read) {
1674 Flag = EfiPciIoOperationBusMasterWrite;
1675 } else {
1676 Flag = EfiPciIoOperationBusMasterRead;
1677 }
1678
1679 PciIo = Private->PciIo;
1680 if (Trb->DataLen != 0) {
1681 MapLength = Trb->DataLen;
1682 Status = PciIo->Map (
1683 PciIo,
1684 Flag,
1685 Trb->Data,
1686 &MapLength,
1687 &Trb->DataPhy,
1688 &Trb->DataMap
1689 );
1690 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1691 Status = EFI_BAD_BUFFER_SIZE;
1692 goto Error;
1693 }
1694 }
1695
1696 if (Trb->DataLen == 0) {
1697 Trb->Mode = SdMmcNoData;
1698 } else if (Private->Capability[Slot].Adma2 != 0) {
1699 Trb->Mode = SdMmcAdma32bMode;
1700 Trb->AdmaLengthMode = SdMmcAdmaLen16b;
1701 if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&
1702 (Private->Capability[Slot].SysBus64V3 == 1)) {
1703 Trb->Mode = SdMmcAdma64bV3Mode;
1704 } else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&
1705 (Private->Capability[Slot].SysBus64V3 == 1)) ||
1706 ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&
1707 (Private->Capability[Slot].SysBus64V4 == 1))) {
1708 Trb->Mode = SdMmcAdma64bV4Mode;
1709 }
1710 if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {
1711 Trb->AdmaLengthMode = SdMmcAdmaLen26b;
1712 }
1713 Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
1714 if (EFI_ERROR (Status)) {
1715 PciIo->Unmap (PciIo, Trb->DataMap);
1716 goto Error;
1717 }
1718 } else if (Private->Capability[Slot].Sdma != 0) {
1719 Trb->Mode = SdMmcSdmaMode;
1720 } else {
1721 Trb->Mode = SdMmcPioMode;
1722 }
1723 }
1724
1725 if (Event != NULL) {
1726 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1727 InsertTailList (&Private->Queue, &Trb->TrbList);
1728 gBS->RestoreTPL (OldTpl);
1729 }
1730
1731 return Trb;
1732
1733 Error:
1734 SdMmcFreeTrb (Trb);
1735 return NULL;
1736 }
1737
1738 /**
1739 Free the resource used by the TRB.
1740
1741 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1742
1743 **/
1744 VOID
1745 SdMmcFreeTrb (
1746 IN SD_MMC_HC_TRB *Trb
1747 )
1748 {
1749 EFI_PCI_IO_PROTOCOL *PciIo;
1750
1751 PciIo = Trb->Private->PciIo;
1752
1753 if (Trb->AdmaMap != NULL) {
1754 PciIo->Unmap (
1755 PciIo,
1756 Trb->AdmaMap
1757 );
1758 }
1759 if (Trb->Adma32Desc != NULL) {
1760 PciIo->FreeBuffer (
1761 PciIo,
1762 Trb->AdmaPages,
1763 Trb->Adma32Desc
1764 );
1765 }
1766 if (Trb->Adma64V3Desc != NULL) {
1767 PciIo->FreeBuffer (
1768 PciIo,
1769 Trb->AdmaPages,
1770 Trb->Adma64V3Desc
1771 );
1772 }
1773 if (Trb->Adma64V4Desc != NULL) {
1774 PciIo->FreeBuffer (
1775 PciIo,
1776 Trb->AdmaPages,
1777 Trb->Adma64V4Desc
1778 );
1779 }
1780 if (Trb->DataMap != NULL) {
1781 PciIo->Unmap (
1782 PciIo,
1783 Trb->DataMap
1784 );
1785 }
1786 FreePool (Trb);
1787 return;
1788 }
1789
1790 /**
1791 Check if the env is ready for execute specified TRB.
1792
1793 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1794 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1795
1796 @retval EFI_SUCCESS The env is ready for TRB execution.
1797 @retval EFI_NOT_READY The env is not ready for TRB execution.
1798 @retval Others Some erros happen.
1799
1800 **/
1801 EFI_STATUS
1802 SdMmcCheckTrbEnv (
1803 IN SD_MMC_HC_PRIVATE_DATA *Private,
1804 IN SD_MMC_HC_TRB *Trb
1805 )
1806 {
1807 EFI_STATUS Status;
1808 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1809 EFI_PCI_IO_PROTOCOL *PciIo;
1810 UINT32 PresentState;
1811
1812 Packet = Trb->Packet;
1813
1814 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1815 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1816 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1817 //
1818 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1819 // the Present State register to be 0
1820 //
1821 PresentState = BIT0 | BIT1;
1822 } else {
1823 //
1824 // Wait Command Inhibit (CMD) in the Present State register
1825 // to be 0
1826 //
1827 PresentState = BIT0;
1828 }
1829
1830 PciIo = Private->PciIo;
1831 Status = SdMmcHcCheckMmioSet (
1832 PciIo,
1833 Trb->Slot,
1834 SD_MMC_HC_PRESENT_STATE,
1835 sizeof (PresentState),
1836 PresentState,
1837 0
1838 );
1839
1840 return Status;
1841 }
1842
1843 /**
1844 Wait for the env to be ready for execute specified TRB.
1845
1846 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1847 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1848
1849 @retval EFI_SUCCESS The env is ready for TRB execution.
1850 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1851 @retval Others Some erros happen.
1852
1853 **/
1854 EFI_STATUS
1855 SdMmcWaitTrbEnv (
1856 IN SD_MMC_HC_PRIVATE_DATA *Private,
1857 IN SD_MMC_HC_TRB *Trb
1858 )
1859 {
1860 EFI_STATUS Status;
1861 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1862 UINT64 Timeout;
1863 BOOLEAN InfiniteWait;
1864
1865 //
1866 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1867 //
1868 Packet = Trb->Packet;
1869 Timeout = Packet->Timeout;
1870 if (Timeout == 0) {
1871 InfiniteWait = TRUE;
1872 } else {
1873 InfiniteWait = FALSE;
1874 }
1875
1876 while (InfiniteWait || (Timeout > 0)) {
1877 //
1878 // Check Trb execution result by reading Normal Interrupt Status register.
1879 //
1880 Status = SdMmcCheckTrbEnv (Private, Trb);
1881 if (Status != EFI_NOT_READY) {
1882 return Status;
1883 }
1884 //
1885 // Stall for 1 microsecond.
1886 //
1887 gBS->Stall (1);
1888
1889 Timeout--;
1890 }
1891
1892 return EFI_TIMEOUT;
1893 }
1894
1895 /**
1896 Execute the specified TRB.
1897
1898 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1899 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1900
1901 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1902 @retval Others Some erros happen when sending this request to the host controller.
1903
1904 **/
1905 EFI_STATUS
1906 SdMmcExecTrb (
1907 IN SD_MMC_HC_PRIVATE_DATA *Private,
1908 IN SD_MMC_HC_TRB *Trb
1909 )
1910 {
1911 EFI_STATUS Status;
1912 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1913 EFI_PCI_IO_PROTOCOL *PciIo;
1914 UINT16 Cmd;
1915 UINT16 IntStatus;
1916 UINT32 Argument;
1917 UINT32 BlkCount;
1918 UINT16 BlkSize;
1919 UINT16 TransMode;
1920 UINT8 HostCtrl1;
1921 UINT64 SdmaAddr;
1922 UINT64 AdmaAddr;
1923 BOOLEAN AddressingMode64;
1924
1925 AddressingMode64 = FALSE;
1926
1927 Packet = Trb->Packet;
1928 PciIo = Trb->Private->PciIo;
1929 //
1930 // Clear all bits in Error Interrupt Status Register
1931 //
1932 IntStatus = 0xFFFF;
1933 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1934 if (EFI_ERROR (Status)) {
1935 return Status;
1936 }
1937 //
1938 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1939 //
1940 IntStatus = 0xFF3F;
1941 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1942 if (EFI_ERROR (Status)) {
1943 return Status;
1944 }
1945
1946 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1947 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1948 SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_64_ADDR_EN);
1949 if (!EFI_ERROR (Status)) {
1950 AddressingMode64 = TRUE;
1951 }
1952 }
1953
1954 //
1955 // Set Host Control 1 register DMA Select field
1956 //
1957 if ((Trb->Mode == SdMmcAdma32bMode) ||
1958 (Trb->Mode == SdMmcAdma64bV4Mode)) {
1959 HostCtrl1 = BIT4;
1960 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1961 if (EFI_ERROR (Status)) {
1962 return Status;
1963 }
1964 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1965 HostCtrl1 = BIT4|BIT3;
1966 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1967 if (EFI_ERROR (Status)) {
1968 return Status;
1969 }
1970 }
1971
1972 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1973
1974 if (Trb->Mode == SdMmcSdmaMode) {
1975 if ((!AddressingMode64) &&
1976 ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {
1977 return EFI_INVALID_PARAMETER;
1978 }
1979
1980 SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;
1981
1982 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1983 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);
1984 } else {
1985 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);
1986 }
1987
1988 if (EFI_ERROR (Status)) {
1989 return Status;
1990 }
1991 } else if ((Trb->Mode == SdMmcAdma32bMode) ||
1992 (Trb->Mode == SdMmcAdma64bV3Mode) ||
1993 (Trb->Mode == SdMmcAdma64bV4Mode)) {
1994 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1995 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1996 if (EFI_ERROR (Status)) {
1997 return Status;
1998 }
1999 }
2000
2001 BlkSize = Trb->BlockSize;
2002 if (Trb->Mode == SdMmcSdmaMode) {
2003 //
2004 // Set SDMA boundary to be 512K bytes.
2005 //
2006 BlkSize |= 0x7000;
2007 }
2008
2009 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
2010 if (EFI_ERROR (Status)) {
2011 return Status;
2012 }
2013
2014 BlkCount = 0;
2015 if (Trb->Mode != SdMmcNoData) {
2016 //
2017 // Calcuate Block Count.
2018 //
2019 BlkCount = (Trb->DataLen / Trb->BlockSize);
2020 }
2021 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {
2022 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);
2023 } else {
2024 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);
2025 }
2026 if (EFI_ERROR (Status)) {
2027 return Status;
2028 }
2029
2030 Argument = Packet->SdMmcCmdBlk->CommandArgument;
2031 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
2032 if (EFI_ERROR (Status)) {
2033 return Status;
2034 }
2035
2036 TransMode = 0;
2037 if (Trb->Mode != SdMmcNoData) {
2038 if (Trb->Mode != SdMmcPioMode) {
2039 TransMode |= BIT0;
2040 }
2041 if (Trb->Read) {
2042 TransMode |= BIT4;
2043 }
2044 if (BlkCount > 1) {
2045 TransMode |= BIT5 | BIT1;
2046 }
2047 //
2048 // Only SD memory card needs to use AUTO CMD12 feature.
2049 //
2050 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
2051 if (BlkCount > 1) {
2052 TransMode |= BIT2;
2053 }
2054 }
2055 }
2056
2057 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
2058 if (EFI_ERROR (Status)) {
2059 return Status;
2060 }
2061
2062 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
2063 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
2064 Cmd |= BIT5;
2065 }
2066 //
2067 // Convert ResponseType to value
2068 //
2069 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2070 switch (Packet->SdMmcCmdBlk->ResponseType) {
2071 case SdMmcResponseTypeR1:
2072 case SdMmcResponseTypeR5:
2073 case SdMmcResponseTypeR6:
2074 case SdMmcResponseTypeR7:
2075 Cmd |= (BIT1 | BIT3 | BIT4);
2076 break;
2077 case SdMmcResponseTypeR2:
2078 Cmd |= (BIT0 | BIT3);
2079 break;
2080 case SdMmcResponseTypeR3:
2081 case SdMmcResponseTypeR4:
2082 Cmd |= BIT1;
2083 break;
2084 case SdMmcResponseTypeR1b:
2085 case SdMmcResponseTypeR5b:
2086 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
2087 break;
2088 default:
2089 ASSERT (FALSE);
2090 break;
2091 }
2092 }
2093 //
2094 // Execute cmd
2095 //
2096 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
2097 return Status;
2098 }
2099
2100 /**
2101 Check the TRB execution result.
2102
2103 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2104 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2105
2106 @retval EFI_SUCCESS The TRB is executed successfully.
2107 @retval EFI_NOT_READY The TRB is not completed for execution.
2108 @retval Others Some erros happen when executing this request.
2109
2110 **/
2111 EFI_STATUS
2112 SdMmcCheckTrbResult (
2113 IN SD_MMC_HC_PRIVATE_DATA *Private,
2114 IN SD_MMC_HC_TRB *Trb
2115 )
2116 {
2117 EFI_STATUS Status;
2118 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2119 UINT16 IntStatus;
2120 UINT32 Response[4];
2121 UINT64 SdmaAddr;
2122 UINT8 Index;
2123 UINT8 SwReset;
2124 UINT32 PioLength;
2125
2126 SwReset = 0;
2127 Packet = Trb->Packet;
2128 //
2129 // Check Trb execution result by reading Normal Interrupt Status register.
2130 //
2131 Status = SdMmcHcRwMmio (
2132 Private->PciIo,
2133 Trb->Slot,
2134 SD_MMC_HC_NOR_INT_STS,
2135 TRUE,
2136 sizeof (IntStatus),
2137 &IntStatus
2138 );
2139 if (EFI_ERROR (Status)) {
2140 goto Done;
2141 }
2142 //
2143 // Check Transfer Complete bit is set or not.
2144 //
2145 if ((IntStatus & BIT1) == BIT1) {
2146 if ((IntStatus & BIT15) == BIT15) {
2147 //
2148 // Read Error Interrupt Status register to check if the error is
2149 // Data Timeout Error.
2150 // If yes, treat it as success as Transfer Complete has higher
2151 // priority than Data Timeout Error.
2152 //
2153 Status = SdMmcHcRwMmio (
2154 Private->PciIo,
2155 Trb->Slot,
2156 SD_MMC_HC_ERR_INT_STS,
2157 TRUE,
2158 sizeof (IntStatus),
2159 &IntStatus
2160 );
2161 if (!EFI_ERROR (Status)) {
2162 if ((IntStatus & BIT4) == BIT4) {
2163 Status = EFI_SUCCESS;
2164 } else {
2165 Status = EFI_DEVICE_ERROR;
2166 }
2167 }
2168 }
2169
2170 goto Done;
2171 }
2172 //
2173 // Check if there is a error happened during cmd execution.
2174 // If yes, then do error recovery procedure to follow SD Host Controller
2175 // Simplified Spec 3.0 section 3.10.1.
2176 //
2177 if ((IntStatus & BIT15) == BIT15) {
2178 Status = SdMmcHcRwMmio (
2179 Private->PciIo,
2180 Trb->Slot,
2181 SD_MMC_HC_ERR_INT_STS,
2182 TRUE,
2183 sizeof (IntStatus),
2184 &IntStatus
2185 );
2186 if (EFI_ERROR (Status)) {
2187 goto Done;
2188 }
2189 if ((IntStatus & 0x0F) != 0) {
2190 SwReset |= BIT1;
2191 }
2192 if ((IntStatus & 0xF0) != 0) {
2193 SwReset |= BIT2;
2194 }
2195
2196 Status = SdMmcHcRwMmio (
2197 Private->PciIo,
2198 Trb->Slot,
2199 SD_MMC_HC_SW_RST,
2200 FALSE,
2201 sizeof (SwReset),
2202 &SwReset
2203 );
2204 if (EFI_ERROR (Status)) {
2205 goto Done;
2206 }
2207 Status = SdMmcHcWaitMmioSet (
2208 Private->PciIo,
2209 Trb->Slot,
2210 SD_MMC_HC_SW_RST,
2211 sizeof (SwReset),
2212 0xFF,
2213 0,
2214 SD_MMC_HC_GENERIC_TIMEOUT
2215 );
2216 if (EFI_ERROR (Status)) {
2217 goto Done;
2218 }
2219
2220 Status = EFI_DEVICE_ERROR;
2221 goto Done;
2222 }
2223 //
2224 // Check if DMA interrupt is signalled for the SDMA transfer.
2225 //
2226 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
2227 //
2228 // Clear DMA interrupt bit.
2229 //
2230 IntStatus = BIT3;
2231 Status = SdMmcHcRwMmio (
2232 Private->PciIo,
2233 Trb->Slot,
2234 SD_MMC_HC_NOR_INT_STS,
2235 FALSE,
2236 sizeof (IntStatus),
2237 &IntStatus
2238 );
2239 if (EFI_ERROR (Status)) {
2240 goto Done;
2241 }
2242 //
2243 // Update SDMA Address register.
2244 //
2245 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
2246
2247 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2248 Status = SdMmcHcRwMmio (
2249 Private->PciIo,
2250 Trb->Slot,
2251 SD_MMC_HC_ADMA_SYS_ADDR,
2252 FALSE,
2253 sizeof (UINT64),
2254 &SdmaAddr
2255 );
2256 } else {
2257 Status = SdMmcHcRwMmio (
2258 Private->PciIo,
2259 Trb->Slot,
2260 SD_MMC_HC_SDMA_ADDR,
2261 FALSE,
2262 sizeof (UINT32),
2263 &SdmaAddr
2264 );
2265 }
2266
2267 if (EFI_ERROR (Status)) {
2268 goto Done;
2269 }
2270 Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
2271 }
2272
2273 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
2274 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
2275 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
2276 if ((IntStatus & BIT0) == BIT0) {
2277 Status = EFI_SUCCESS;
2278 goto Done;
2279 }
2280 }
2281
2282 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
2283 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
2284 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
2285 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
2286 //
2287 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2288 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2289 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2290 //
2291 if ((IntStatus & BIT5) == BIT5) {
2292 //
2293 // Clear Buffer Read Ready interrupt at first.
2294 //
2295 IntStatus = BIT5;
2296 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2297 //
2298 // Read data out from Buffer Port register
2299 //
2300 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
2301 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
2302 }
2303 Status = EFI_SUCCESS;
2304 goto Done;
2305 }
2306 }
2307
2308 Status = EFI_NOT_READY;
2309 Done:
2310 //
2311 // Get response data when the cmd is executed successfully.
2312 //
2313 if (!EFI_ERROR (Status)) {
2314 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2315 for (Index = 0; Index < 4; Index++) {
2316 Status = SdMmcHcRwMmio (
2317 Private->PciIo,
2318 Trb->Slot,
2319 SD_MMC_HC_RESPONSE + Index * 4,
2320 TRUE,
2321 sizeof (UINT32),
2322 &Response[Index]
2323 );
2324 if (EFI_ERROR (Status)) {
2325 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2326 return Status;
2327 }
2328 }
2329 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2330 }
2331 }
2332
2333 if (Status != EFI_NOT_READY) {
2334 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2335 }
2336
2337 return Status;
2338 }
2339
2340 /**
2341 Wait for the TRB execution result.
2342
2343 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2344 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2345
2346 @retval EFI_SUCCESS The TRB is executed successfully.
2347 @retval Others Some erros happen when executing this request.
2348
2349 **/
2350 EFI_STATUS
2351 SdMmcWaitTrbResult (
2352 IN SD_MMC_HC_PRIVATE_DATA *Private,
2353 IN SD_MMC_HC_TRB *Trb
2354 )
2355 {
2356 EFI_STATUS Status;
2357 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2358 UINT64 Timeout;
2359 BOOLEAN InfiniteWait;
2360
2361 Packet = Trb->Packet;
2362 //
2363 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2364 //
2365 Timeout = Packet->Timeout;
2366 if (Timeout == 0) {
2367 InfiniteWait = TRUE;
2368 } else {
2369 InfiniteWait = FALSE;
2370 }
2371
2372 while (InfiniteWait || (Timeout > 0)) {
2373 //
2374 // Check Trb execution result by reading Normal Interrupt Status register.
2375 //
2376 Status = SdMmcCheckTrbResult (Private, Trb);
2377 if (Status != EFI_NOT_READY) {
2378 return Status;
2379 }
2380 //
2381 // Stall for 1 microsecond.
2382 //
2383 gBS->Stall (1);
2384
2385 Timeout--;
2386 }
2387
2388 return EFI_TIMEOUT;
2389 }
2390
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