2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
15 #include "SdMmcPciHcDxe.h"
18 Dump the content of SD/MMC host controller's Capability Register.
20 @param[in] Slot The slot number of the SD card to send the command to.
21 @param[in] Capability The buffer to store the capability data.
27 IN SD_MMC_HC_SLOT_CAP
*Capability
31 // Dump Capability Data
33 DEBUG ((DEBUG_INFO
, " == Slot [%d] Capability is 0x%x ==\n", Slot
, Capability
));
34 DEBUG ((DEBUG_INFO
, " Timeout Clk Freq %d%a\n", Capability
->TimeoutFreq
, (Capability
->TimeoutUnit
) ? "MHz" : "KHz"));
35 DEBUG ((DEBUG_INFO
, " Base Clk Freq %dMHz\n", Capability
->BaseClkFreq
));
36 DEBUG ((DEBUG_INFO
, " Max Blk Len %dbytes\n", 512 * (1 << Capability
->MaxBlkLen
)));
37 DEBUG ((DEBUG_INFO
, " 8-bit Support %a\n", Capability
->BusWidth8
? "TRUE" : "FALSE"));
38 DEBUG ((DEBUG_INFO
, " ADMA2 Support %a\n", Capability
->Adma2
? "TRUE" : "FALSE"));
39 DEBUG ((DEBUG_INFO
, " HighSpeed Support %a\n", Capability
->HighSpeed
? "TRUE" : "FALSE"));
40 DEBUG ((DEBUG_INFO
, " SDMA Support %a\n", Capability
->Sdma
? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO
, " Suspend/Resume %a\n", Capability
->SuspRes
? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO
, " Voltage 3.3 %a\n", Capability
->Voltage33
? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO
, " Voltage 3.0 %a\n", Capability
->Voltage30
? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO
, " Voltage 1.8 %a\n", Capability
->Voltage18
? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO
, " V4 64-bit Sys Bus %a\n", Capability
->SysBus64V4
? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO
, " V3 64-bit Sys Bus %a\n", Capability
->SysBus64V3
? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO
, " Async Interrupt %a\n", Capability
->AsyncInt
? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO
, " SlotType "));
49 if (Capability
->SlotType
== 0x00) {
50 DEBUG ((DEBUG_INFO
, "%a\n", "Removable Slot"));
51 } else if (Capability
->SlotType
== 0x01) {
52 DEBUG ((DEBUG_INFO
, "%a\n", "Embedded Slot"));
53 } else if (Capability
->SlotType
== 0x02) {
54 DEBUG ((DEBUG_INFO
, "%a\n", "Shared Bus Slot"));
56 DEBUG ((DEBUG_INFO
, "%a\n", "Reserved"));
58 DEBUG ((DEBUG_INFO
, " SDR50 Support %a\n", Capability
->Sdr50
? "TRUE" : "FALSE"));
59 DEBUG ((DEBUG_INFO
, " SDR104 Support %a\n", Capability
->Sdr104
? "TRUE" : "FALSE"));
60 DEBUG ((DEBUG_INFO
, " DDR50 Support %a\n", Capability
->Ddr50
? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO
, " Driver Type A %a\n", Capability
->DriverTypeA
? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO
, " Driver Type C %a\n", Capability
->DriverTypeC
? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO
, " Driver Type D %a\n", Capability
->DriverTypeD
? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO
, " Driver Type 4 %a\n", Capability
->DriverType4
? "TRUE" : "FALSE"));
65 if (Capability
->TimerCount
== 0) {
66 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt Disabled\n", 2 * (Capability
->TimerCount
- 1)));
68 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt %dseconds\n", 2 * (Capability
->TimerCount
- 1)));
70 DEBUG ((DEBUG_INFO
, " SDR50 Tuning %a\n", Capability
->TuningSDR50
? "TRUE" : "FALSE"));
71 DEBUG ((DEBUG_INFO
, " Retuning Mode Mode %d\n", Capability
->RetuningMod
+ 1));
72 DEBUG ((DEBUG_INFO
, " Clock Multiplier M = %d\n", Capability
->ClkMultiplier
+ 1));
73 DEBUG ((DEBUG_INFO
, " HS 400 %a\n", Capability
->Hs400
? "TRUE" : "FALSE"));
78 Read SlotInfo register from SD/MMC host controller pci config space.
80 @param[in] PciIo The PCI IO protocol instance.
81 @param[out] FirstBar The buffer to store the first BAR value.
82 @param[out] SlotNum The buffer to store the supported slot number.
84 @retval EFI_SUCCESS The operation succeeds.
85 @retval Others The operation fails.
91 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
97 SD_MMC_HC_SLOT_INFO SlotInfo
;
99 Status
= PciIo
->Pci
.Read (
102 SD_MMC_HC_SLOT_OFFSET
,
106 if (EFI_ERROR (Status
)) {
110 *FirstBar
= SlotInfo
.FirstBar
;
111 *SlotNum
= SlotInfo
.SlotNum
+ 1;
112 ASSERT ((*FirstBar
+ *SlotNum
) < SD_MMC_HC_MAX_SLOT
);
117 Read/Write specified SD/MMC host controller mmio register.
119 @param[in] PciIo The PCI IO protocol instance.
120 @param[in] BarIndex The BAR index of the standard PCI Configuration
121 header to use as the base address for the memory
122 operation to perform.
123 @param[in] Offset The offset within the selected BAR to start the
125 @param[in] Read A boolean to indicate it's read or write operation.
126 @param[in] Count The width of the mmio register in bytes.
127 Must be 1, 2 , 4 or 8 bytes.
128 @param[in, out] Data For read operations, the destination buffer to store
129 the results. For write operations, the source buffer
130 to write data from. The caller is responsible for
131 having ownership of the data buffer and ensuring its
132 size not less than Count bytes.
134 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
135 @retval EFI_SUCCESS The read/write operation succeeds.
136 @retval Others The read/write operation fails.
142 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
151 EFI_PCI_IO_PROTOCOL_WIDTH Width
;
153 if ((PciIo
== NULL
) || (Data
== NULL
)) {
154 return EFI_INVALID_PARAMETER
;
159 Width
= EfiPciIoWidthUint8
;
162 Width
= EfiPciIoWidthUint16
;
166 Width
= EfiPciIoWidthUint32
;
170 Width
= EfiPciIoWidthUint32
;
174 return EFI_INVALID_PARAMETER
;
178 Status
= PciIo
->Mem
.Read (
187 Status
= PciIo
->Mem
.Write (
201 Do OR operation with the value of the specified SD/MMC host controller mmio register.
203 @param[in] PciIo The PCI IO protocol instance.
204 @param[in] BarIndex The BAR index of the standard PCI Configuration
205 header to use as the base address for the memory
206 operation to perform.
207 @param[in] Offset The offset within the selected BAR to start the
209 @param[in] Count The width of the mmio register in bytes.
210 Must be 1, 2 , 4 or 8 bytes.
211 @param[in] OrData The pointer to the data used to do OR operation.
212 The caller is responsible for having ownership of
213 the data buffer and ensuring its size not less than
216 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
217 @retval EFI_SUCCESS The OR operation succeeds.
218 @retval Others The OR operation fails.
224 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
235 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
236 if (EFI_ERROR (Status
)) {
241 Or
= *(UINT8
*) OrData
;
242 } else if (Count
== 2) {
243 Or
= *(UINT16
*) OrData
;
244 } else if (Count
== 4) {
245 Or
= *(UINT32
*) OrData
;
246 } else if (Count
== 8) {
247 Or
= *(UINT64
*) OrData
;
249 return EFI_INVALID_PARAMETER
;
253 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
259 Do AND operation with the value of the specified SD/MMC host controller mmio register.
261 @param[in] PciIo The PCI IO protocol instance.
262 @param[in] BarIndex The BAR index of the standard PCI Configuration
263 header to use as the base address for the memory
264 operation to perform.
265 @param[in] Offset The offset within the selected BAR to start the
267 @param[in] Count The width of the mmio register in bytes.
268 Must be 1, 2 , 4 or 8 bytes.
269 @param[in] AndData The pointer to the data used to do AND operation.
270 The caller is responsible for having ownership of
271 the data buffer and ensuring its size not less than
274 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
275 @retval EFI_SUCCESS The AND operation succeeds.
276 @retval Others The AND operation fails.
282 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
293 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
294 if (EFI_ERROR (Status
)) {
299 And
= *(UINT8
*) AndData
;
300 } else if (Count
== 2) {
301 And
= *(UINT16
*) AndData
;
302 } else if (Count
== 4) {
303 And
= *(UINT32
*) AndData
;
304 } else if (Count
== 8) {
305 And
= *(UINT64
*) AndData
;
307 return EFI_INVALID_PARAMETER
;
311 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
317 Wait for the value of the specified MMIO register set to the test value.
319 @param[in] PciIo The PCI IO protocol instance.
320 @param[in] BarIndex The BAR index of the standard PCI Configuration
321 header to use as the base address for the memory
322 operation to perform.
323 @param[in] Offset The offset within the selected BAR to start the
325 @param[in] Count The width of the mmio register in bytes.
326 Must be 1, 2, 4 or 8 bytes.
327 @param[in] MaskValue The mask value of memory.
328 @param[in] TestValue The test value of memory.
330 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
331 @retval EFI_SUCCESS The MMIO register has expected value.
332 @retval Others The MMIO operation fails.
337 SdMmcHcCheckMmioSet (
338 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
350 // Access PCI MMIO space to see if the value is the tested one.
353 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Value
);
354 if (EFI_ERROR (Status
)) {
360 if (Value
== TestValue
) {
364 return EFI_NOT_READY
;
368 Wait for the value of the specified MMIO register set to the test value.
370 @param[in] PciIo The PCI IO protocol instance.
371 @param[in] BarIndex The BAR index of the standard PCI Configuration
372 header to use as the base address for the memory
373 operation to perform.
374 @param[in] Offset The offset within the selected BAR to start the
376 @param[in] Count The width of the mmio register in bytes.
377 Must be 1, 2, 4 or 8 bytes.
378 @param[in] MaskValue The mask value of memory.
379 @param[in] TestValue The test value of memory.
380 @param[in] Timeout The time out value for wait memory set, uses 1
381 microsecond as a unit.
383 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
385 @retval EFI_SUCCESS The MMIO register has expected value.
386 @retval Others The MMIO operation fails.
392 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
402 BOOLEAN InfiniteWait
;
407 InfiniteWait
= FALSE
;
410 while (InfiniteWait
|| (Timeout
> 0)) {
411 Status
= SdMmcHcCheckMmioSet (
419 if (Status
!= EFI_NOT_READY
) {
424 // Stall for 1 microsecond.
435 Get the controller version information from the specified slot.
437 @param[in] PciIo The PCI IO protocol instance.
438 @param[in] Slot The slot number of the SD card to send the command to.
439 @param[out] Version The buffer to store the version information.
441 @retval EFI_SUCCESS The operation executes successfully.
442 @retval Others The operation fails.
446 SdMmcHcGetControllerVersion (
447 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
454 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CTRL_VER
, TRUE
, sizeof (UINT16
), Version
);
455 if (EFI_ERROR (Status
)) {
465 Software reset the specified SD/MMC host controller and enable all interrupts.
467 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
468 @param[in] Slot The slot number of the SD card to send the command to.
470 @retval EFI_SUCCESS The software reset executes successfully.
471 @retval Others The software reset fails.
476 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
482 EFI_PCI_IO_PROTOCOL
*PciIo
;
485 // Notify the SD/MMC override protocol that we are about to reset
486 // the SD/MMC host controller.
488 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
489 Status
= mOverride
->NotifyPhase (
490 Private
->ControllerHandle
,
494 if (EFI_ERROR (Status
)) {
496 "%a: SD/MMC pre reset notifier callback failed - %r\n",
497 __FUNCTION__
, Status
));
502 PciIo
= Private
->PciIo
;
504 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_SW_RST
, sizeof (SwReset
), &SwReset
);
506 if (EFI_ERROR (Status
)) {
507 DEBUG ((DEBUG_ERROR
, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status
));
511 Status
= SdMmcHcWaitMmioSet (
518 SD_MMC_HC_GENERIC_TIMEOUT
520 if (EFI_ERROR (Status
)) {
521 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: reset done with %r\n", Status
));
526 // Enable all interrupt after reset all.
528 Status
= SdMmcHcEnableInterrupt (PciIo
, Slot
);
529 if (EFI_ERROR (Status
)) {
530 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
536 // Notify the SD/MMC override protocol that we have just reset
537 // the SD/MMC host controller.
539 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
540 Status
= mOverride
->NotifyPhase (
541 Private
->ControllerHandle
,
545 if (EFI_ERROR (Status
)) {
547 "%a: SD/MMC post reset notifier callback failed - %r\n",
548 __FUNCTION__
, Status
));
556 Set all interrupt status bits in Normal and Error Interrupt Status Enable
559 @param[in] PciIo The PCI IO protocol instance.
560 @param[in] Slot The slot number of the SD card to send the command to.
562 @retval EFI_SUCCESS The operation executes successfully.
563 @retval Others The operation fails.
567 SdMmcHcEnableInterrupt (
568 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
576 // Enable all bits in Error Interrupt Status Enable Register
579 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_ERR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
580 if (EFI_ERROR (Status
)) {
584 // Enable all bits in Normal Interrupt Status Enable Register
587 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
593 Get the capability data from the specified slot.
595 @param[in] PciIo The PCI IO protocol instance.
596 @param[in] Slot The slot number of the SD card to send the command to.
597 @param[out] Capability The buffer to store the capability data.
599 @retval EFI_SUCCESS The operation executes successfully.
600 @retval Others The operation fails.
604 SdMmcHcGetCapability (
605 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
607 OUT SD_MMC_HC_SLOT_CAP
*Capability
613 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CAP
, TRUE
, sizeof (Cap
), &Cap
);
614 if (EFI_ERROR (Status
)) {
618 CopyMem (Capability
, &Cap
, sizeof (Cap
));
624 Get the maximum current capability data from the specified slot.
626 @param[in] PciIo The PCI IO protocol instance.
627 @param[in] Slot The slot number of the SD card to send the command to.
628 @param[out] MaxCurrent The buffer to store the maximum current capability data.
630 @retval EFI_SUCCESS The operation executes successfully.
631 @retval Others The operation fails.
635 SdMmcHcGetMaxCurrent (
636 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
638 OUT UINT64
*MaxCurrent
643 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_MAX_CURRENT_CAP
, TRUE
, sizeof (UINT64
), MaxCurrent
);
649 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
652 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
654 @param[in] PciIo The PCI IO protocol instance.
655 @param[in] Slot The slot number of the SD card to send the command to.
656 @param[out] MediaPresent The pointer to the media present boolean value.
658 @retval EFI_SUCCESS There is no media change happened.
659 @retval EFI_MEDIA_CHANGED There is media change happened.
660 @retval Others The detection fails.
665 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
667 OUT BOOLEAN
*MediaPresent
675 // Check Present State Register to see if there is a card presented.
677 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_PRESENT_STATE
, TRUE
, sizeof (PresentState
), &PresentState
);
678 if (EFI_ERROR (Status
)) {
682 if ((PresentState
& BIT16
) != 0) {
683 *MediaPresent
= TRUE
;
685 *MediaPresent
= FALSE
;
689 // Check Normal Interrupt Status Register
691 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, TRUE
, sizeof (Data
), &Data
);
692 if (EFI_ERROR (Status
)) {
696 if ((Data
& (BIT6
| BIT7
)) != 0) {
698 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
701 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data
), &Data
);
702 if (EFI_ERROR (Status
)) {
706 return EFI_MEDIA_CHANGED
;
713 Stop SD/MMC card clock.
715 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
717 @param[in] PciIo The PCI IO protocol instance.
718 @param[in] Slot The slot number of the SD card to send the command to.
720 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
721 @retval Others Fail to stop SD/MMC clock.
726 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
735 // Ensure no SD transactions are occurring on the SD Bus by
736 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
737 // in the Present State register to be 0.
739 Status
= SdMmcHcWaitMmioSet (
742 SD_MMC_HC_PRESENT_STATE
,
743 sizeof (PresentState
),
746 SD_MMC_HC_GENERIC_TIMEOUT
748 if (EFI_ERROR (Status
)) {
753 // Set SD Clock Enable in the Clock Control register to 0
755 ClockCtrl
= (UINT16
)~BIT2
;
756 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
764 @param[in] PciIo The PCI IO protocol instance.
765 @param[in] Slot The slot number.
767 @retval EFI_SUCCESS Succeeded to start the SD clock.
768 @retval Others Failed to start the SD clock.
771 SdMmcHcStartSdClock (
772 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
779 // Set SD Clock Enable in the Clock Control register to 1
782 return SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
786 SD/MMC card clock supply.
788 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
790 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
791 @param[in] Slot The slot number of the SD card to send the command to.
792 @param[in] BusTiming BusTiming at which the frequency change is done.
793 @param[in] FirstTimeSetup Flag to indicate whether the clock is being setup for the first time.
794 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
796 @retval EFI_SUCCESS The clock is supplied successfully.
797 @retval Others The clock isn't supplied successfully.
802 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
804 IN SD_MMC_BUS_MODE BusTiming
,
805 IN BOOLEAN FirstTimeSetup
,
815 UINT16 ControllerVer
;
816 EFI_PCI_IO_PROTOCOL
*PciIo
;
818 PciIo
= Private
->PciIo
;
819 BaseClkFreq
= Private
->BaseClkFreq
[Slot
];
820 ControllerVer
= Private
->ControllerVersion
[Slot
];
822 if (BaseClkFreq
== 0 || ClockFreq
== 0) {
823 return EFI_INVALID_PARAMETER
;
826 if (ClockFreq
> (BaseClkFreq
* 1000)) {
827 ClockFreq
= BaseClkFreq
* 1000;
831 // Calculate the divisor of base frequency.
834 SettingFreq
= BaseClkFreq
* 1000;
835 while (ClockFreq
< SettingFreq
) {
838 SettingFreq
= (BaseClkFreq
* 1000) / (2 * Divisor
);
839 Remainder
= (BaseClkFreq
* 1000) % (2 * Divisor
);
840 if ((ClockFreq
== SettingFreq
) && (Remainder
== 0)) {
843 if ((ClockFreq
== SettingFreq
) && (Remainder
!= 0)) {
848 DEBUG ((DEBUG_INFO
, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq
, Divisor
, ClockFreq
));
851 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
853 if ((ControllerVer
>= SD_MMC_HC_CTRL_VER_300
) &&
854 (ControllerVer
<= SD_MMC_HC_CTRL_VER_420
)) {
855 ASSERT (Divisor
<= 0x3FF);
856 ClockCtrl
= ((Divisor
& 0xFF) << 8) | ((Divisor
& 0x300) >> 2);
857 } else if ((ControllerVer
== SD_MMC_HC_CTRL_VER_100
) ||
858 (ControllerVer
== SD_MMC_HC_CTRL_VER_200
)) {
860 // Only the most significant bit can be used as divisor.
862 if (((Divisor
- 1) & Divisor
) != 0) {
863 Divisor
= 1 << (HighBitSet32 (Divisor
) + 1);
865 ASSERT (Divisor
<= 0x80);
866 ClockCtrl
= (Divisor
& 0xFF) << 8;
868 DEBUG ((DEBUG_ERROR
, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer
));
869 return EFI_UNSUPPORTED
;
873 // Stop bus clock at first
875 Status
= SdMmcHcStopClock (PciIo
, Slot
);
876 if (EFI_ERROR (Status
)) {
881 // Supply clock frequency with specified divisor
884 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, FALSE
, sizeof (ClockCtrl
), &ClockCtrl
);
885 if (EFI_ERROR (Status
)) {
886 DEBUG ((DEBUG_ERROR
, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
891 // Wait Internal Clock Stable in the Clock Control register to be 1
893 Status
= SdMmcHcWaitMmioSet (
896 SD_MMC_HC_CLOCK_CTRL
,
900 SD_MMC_HC_GENERIC_TIMEOUT
902 if (EFI_ERROR (Status
)) {
906 Status
= SdMmcHcStartSdClock (PciIo
, Slot
);
907 if (EFI_ERROR (Status
)) {
912 // We don't notify the platform on first time setup to avoid changing
913 // legacy behavior. During first time setup we also don't know what type
914 // of the card slot it is and which enum value of BusTiming applies.
916 if (!FirstTimeSetup
&& mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
917 Status
= mOverride
->NotifyPhase (
918 Private
->ControllerHandle
,
920 EdkiiSdMmcSwitchClockFreqPost
,
923 if (EFI_ERROR (Status
)) {
926 "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
938 SD/MMC bus power control.
940 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
942 @param[in] PciIo The PCI IO protocol instance.
943 @param[in] Slot The slot number of the SD card to send the command to.
944 @param[in] PowerCtrl The value setting to the power control register.
946 @retval TRUE There is a SD/MMC card attached.
947 @retval FALSE There is no a SD/MMC card attached.
951 SdMmcHcPowerControl (
952 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
962 PowerCtrl
&= (UINT8
)~BIT0
;
963 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
964 if (EFI_ERROR (Status
)) {
969 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
972 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
978 Set the SD/MMC bus width.
980 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
982 @param[in] PciIo The PCI IO protocol instance.
983 @param[in] Slot The slot number of the SD card to send the command to.
984 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
986 @retval EFI_SUCCESS The bus width is set successfully.
987 @retval Others The bus width isn't set successfully.
992 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1000 if (BusWidth
== 1) {
1001 HostCtrl1
= (UINT8
)~(BIT5
| BIT1
);
1002 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1003 } else if (BusWidth
== 4) {
1004 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
1005 if (EFI_ERROR (Status
)) {
1009 HostCtrl1
&= (UINT8
)~BIT5
;
1010 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
1011 } else if (BusWidth
== 8) {
1012 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
1013 if (EFI_ERROR (Status
)) {
1016 HostCtrl1
&= (UINT8
)~BIT1
;
1018 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
1021 return EFI_INVALID_PARAMETER
;
1028 Configure V4 controller enhancements at initialization.
1030 @param[in] PciIo The PCI IO protocol instance.
1031 @param[in] Slot The slot number of the SD card to send the command to.
1032 @param[in] Capability The capability of the slot.
1033 @param[in] ControllerVer The version of host controller.
1035 @retval EFI_SUCCESS The clock is supplied successfully.
1039 SdMmcHcInitV4Enhancements (
1040 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1042 IN SD_MMC_HC_SLOT_CAP Capability
,
1043 IN UINT16 ControllerVer
1050 // Check if controller version V4 or higher
1052 if (ControllerVer
>= SD_MMC_HC_CTRL_VER_400
) {
1053 HostCtrl2
= SD_MMC_HC_V4_EN
;
1055 // Check if controller version V4.0
1057 if (ControllerVer
== SD_MMC_HC_CTRL_VER_400
) {
1059 // Check if 64bit support is available
1061 if (Capability
.SysBus64V3
!= 0) {
1062 HostCtrl2
|= SD_MMC_HC_64_ADDR_EN
;
1063 DEBUG ((DEBUG_INFO
, "Enabled V4 64 bit system bus support\n"));
1067 // Check if controller version V4.10 or higher
1069 else if (ControllerVer
>= SD_MMC_HC_CTRL_VER_410
) {
1071 // Check if 64bit support is available
1073 if (Capability
.SysBus64V4
!= 0) {
1074 HostCtrl2
|= SD_MMC_HC_64_ADDR_EN
;
1075 DEBUG ((DEBUG_INFO
, "Enabled V4 64 bit system bus support\n"));
1077 HostCtrl2
|= SD_MMC_HC_26_DATA_LEN_ADMA_EN
;
1078 DEBUG ((DEBUG_INFO
, "Enabled V4 26 bit data length ADMA support\n"));
1080 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1081 if (EFI_ERROR (Status
)) {
1090 Supply SD/MMC card with maximum voltage at initialization.
1092 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1094 @param[in] PciIo The PCI IO protocol instance.
1095 @param[in] Slot The slot number of the SD card to send the command to.
1096 @param[in] Capability The capability of the slot.
1098 @retval EFI_SUCCESS The voltage is supplied successfully.
1099 @retval Others The voltage isn't supplied successfully.
1103 SdMmcHcInitPowerVoltage (
1104 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1106 IN SD_MMC_HC_SLOT_CAP Capability
1114 // Calculate supported maximum voltage according to SD Bus Voltage Select
1116 if (Capability
.Voltage33
!= 0) {
1121 } else if (Capability
.Voltage30
!= 0) {
1126 } else if (Capability
.Voltage18
!= 0) {
1132 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1134 if (EFI_ERROR (Status
)) {
1139 return EFI_DEVICE_ERROR
;
1143 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1145 Status
= SdMmcHcPowerControl (PciIo
, Slot
, MaxVoltage
);
1151 Initialize the Timeout Control register with most conservative value at initialization.
1153 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1155 @param[in] PciIo The PCI IO protocol instance.
1156 @param[in] Slot The slot number of the SD card to send the command to.
1158 @retval EFI_SUCCESS The timeout control register is configured successfully.
1159 @retval Others The timeout control register isn't configured successfully.
1163 SdMmcHcInitTimeoutCtrl (
1164 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1172 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_TIMEOUT_CTRL
, FALSE
, sizeof (Timeout
), &Timeout
);
1178 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1181 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1182 @param[in] Slot The slot number of the SD card to send the command to.
1184 @retval EFI_SUCCESS The host controller is initialized successfully.
1185 @retval Others The host controller isn't initialized successfully.
1190 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1195 EFI_PCI_IO_PROTOCOL
*PciIo
;
1196 SD_MMC_HC_SLOT_CAP Capability
;
1199 // Notify the SD/MMC override protocol that we are about to initialize
1200 // the SD/MMC host controller.
1202 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1203 Status
= mOverride
->NotifyPhase (
1204 Private
->ControllerHandle
,
1206 EdkiiSdMmcInitHostPre
,
1208 if (EFI_ERROR (Status
)) {
1210 "%a: SD/MMC pre init notifier callback failed - %r\n",
1211 __FUNCTION__
, Status
));
1216 PciIo
= Private
->PciIo
;
1217 Capability
= Private
->Capability
[Slot
];
1219 Status
= SdMmcHcInitV4Enhancements (PciIo
, Slot
, Capability
, Private
->ControllerVersion
[Slot
]);
1220 if (EFI_ERROR (Status
)) {
1225 // Perform first time clock setup with 400 KHz frequency.
1226 // We send the 0 as the BusTiming value because at this time
1227 // we still do not know the slot type and which enum value will apply.
1228 // Since it is a first time setup SdMmcHcClockSupply won't notify
1229 // the platofrm driver anyway so it doesn't matter.
1231 Status
= SdMmcHcClockSupply (Private
, Slot
, 0, TRUE
, 400);
1232 if (EFI_ERROR (Status
)) {
1236 Status
= SdMmcHcInitPowerVoltage (PciIo
, Slot
, Capability
);
1237 if (EFI_ERROR (Status
)) {
1241 Status
= SdMmcHcInitTimeoutCtrl (PciIo
, Slot
);
1242 if (EFI_ERROR (Status
)) {
1247 // Notify the SD/MMC override protocol that we are have just initialized
1248 // the SD/MMC host controller.
1250 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1251 Status
= mOverride
->NotifyPhase (
1252 Private
->ControllerHandle
,
1254 EdkiiSdMmcInitHostPost
,
1256 if (EFI_ERROR (Status
)) {
1258 "%a: SD/MMC post init notifier callback failed - %r\n",
1259 __FUNCTION__
, Status
));
1266 Set SD Host Controler control 2 registry according to selected speed.
1268 @param[in] ControllerHandle The handle of the controller.
1269 @param[in] PciIo The PCI IO protocol instance.
1270 @param[in] Slot The slot number of the SD card to send the command to.
1271 @param[in] Timing The timing to select.
1273 @retval EFI_SUCCESS The timing is set successfully.
1274 @retval Others The timing isn't set successfully.
1277 SdMmcHcUhsSignaling (
1278 IN EFI_HANDLE ControllerHandle
,
1279 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1281 IN SD_MMC_BUS_MODE Timing
1287 HostCtrl2
= (UINT8
)~SD_MMC_HC_CTRL_UHS_MASK
;
1288 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1289 if (EFI_ERROR (Status
)) {
1295 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR12
;
1298 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR25
;
1301 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR50
;
1303 case SdMmcUhsSdr104
:
1304 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR104
;
1307 HostCtrl2
= SD_MMC_HC_CTRL_UHS_DDR50
;
1309 case SdMmcMmcLegacy
:
1310 HostCtrl2
= SD_MMC_HC_CTRL_MMC_LEGACY
;
1313 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_SDR
;
1316 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_DDR
;
1319 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS200
;
1322 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS400
;
1328 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1329 if (EFI_ERROR (Status
)) {
1333 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1334 Status
= mOverride
->NotifyPhase (
1337 EdkiiSdMmcUhsSignaling
,
1340 if (EFI_ERROR (Status
)) {
1343 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1355 Set driver strength in host controller.
1357 @param[in] PciIo The PCI IO protocol instance.
1358 @param[in] SlotIndex The slot index of the card.
1359 @param[in] DriverStrength DriverStrength to set in the controller.
1361 @retval EFI_SUCCESS Driver strength programmed successfully.
1362 @retval Others Failed to set driver strength.
1365 SdMmcSetDriverStrength (
1366 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1368 IN SD_DRIVER_STRENGTH_TYPE DriverStrength
1374 if (DriverStrength
== SdDriverStrengthIgnore
) {
1378 HostCtrl2
= (UINT16
)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK
;
1379 Status
= SdMmcHcAndMmio (PciIo
, SlotIndex
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1380 if (EFI_ERROR (Status
)) {
1384 HostCtrl2
= (DriverStrength
<< 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK
;
1385 return SdMmcHcOrMmio (PciIo
, SlotIndex
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1391 @param[in] PciIo The PCI IO protocol instance.
1392 @param[in] Slot The slot number of the SD card to send the command to.
1393 @param[in] On The boolean to turn on/off LED.
1395 @retval EFI_SUCCESS The LED is turned on/off successfully.
1396 @retval Others The LED isn't turned on/off successfully.
1401 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1411 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1413 HostCtrl1
= (UINT8
)~BIT0
;
1414 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1421 Build ADMA descriptor table for transfer.
1423 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1425 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1426 @param[in] ControllerVer The version of host controller.
1428 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1429 @retval Others The ADMA descriptor table isn't created successfully.
1433 BuildAdmaDescTable (
1434 IN SD_MMC_HC_TRB
*Trb
,
1435 IN UINT16 ControllerVer
1438 EFI_PHYSICAL_ADDRESS Data
;
1445 EFI_PCI_IO_PROTOCOL
*PciIo
;
1448 UINT32 AdmaMaxDataPerLine
;
1452 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_16B
;
1453 DescSize
= sizeof (SD_MMC_HC_ADMA_32_DESC_LINE
);
1456 Data
= Trb
->DataPhy
;
1457 DataLen
= Trb
->DataLen
;
1458 PciIo
= Trb
->Private
->PciIo
;
1461 // Check for valid ranges in 32bit ADMA Descriptor Table
1463 if ((Trb
->Mode
== SdMmcAdma32bMode
) &&
1464 ((Data
>= 0x100000000ul
) || ((Data
+ DataLen
) > 0x100000000ul
))) {
1465 return EFI_INVALID_PARAMETER
;
1468 // Check address field alignment
1470 if (Trb
->Mode
!= SdMmcAdma32bMode
) {
1472 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1474 if ((Data
& (BIT0
| BIT1
| BIT2
)) != 0) {
1475 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data
));
1479 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1481 if ((Data
& (BIT0
| BIT1
)) != 0) {
1482 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data
));
1487 // Configure 64b ADMA.
1489 if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1490 DescSize
= sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE
);
1491 }else if (Trb
->Mode
== SdMmcAdma64bV4Mode
) {
1492 DescSize
= sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE
);
1495 // Configure 26b data length.
1497 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1498 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_26B
;
1501 Entries
= DivU64x32 ((DataLen
+ AdmaMaxDataPerLine
- 1), AdmaMaxDataPerLine
);
1502 TableSize
= (UINTN
)MultU64x32 (Entries
, DescSize
);
1503 Trb
->AdmaPages
= (UINT32
)EFI_SIZE_TO_PAGES (TableSize
);
1504 Status
= PciIo
->AllocateBuffer (
1507 EfiBootServicesData
,
1508 EFI_SIZE_TO_PAGES (TableSize
),
1512 if (EFI_ERROR (Status
)) {
1513 return EFI_OUT_OF_RESOURCES
;
1515 ZeroMem (AdmaDesc
, TableSize
);
1517 Status
= PciIo
->Map (
1519 EfiPciIoOperationBusMasterCommonBuffer
,
1526 if (EFI_ERROR (Status
) || (Bytes
!= TableSize
)) {
1528 // Map error or unable to map the whole RFis buffer into a contiguous region.
1532 EFI_SIZE_TO_PAGES (TableSize
),
1535 return EFI_OUT_OF_RESOURCES
;
1538 if ((Trb
->Mode
== SdMmcAdma32bMode
) &&
1539 (UINT64
)(UINTN
)Trb
->AdmaDescPhy
> 0x100000000ul
) {
1541 // The ADMA doesn't support 64bit addressing.
1549 EFI_SIZE_TO_PAGES (TableSize
),
1552 return EFI_DEVICE_ERROR
;
1555 Remaining
= DataLen
;
1557 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1558 Trb
->Adma32Desc
= AdmaDesc
;
1559 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1560 Trb
->Adma64V3Desc
= AdmaDesc
;
1562 Trb
->Adma64V4Desc
= AdmaDesc
;
1565 for (Index
= 0; Index
< Entries
; Index
++) {
1566 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1567 if (Remaining
<= AdmaMaxDataPerLine
) {
1568 Trb
->Adma32Desc
[Index
].Valid
= 1;
1569 Trb
->Adma32Desc
[Index
].Act
= 2;
1570 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1571 Trb
->Adma32Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1573 Trb
->Adma32Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1574 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1577 Trb
->Adma32Desc
[Index
].Valid
= 1;
1578 Trb
->Adma32Desc
[Index
].Act
= 2;
1579 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1580 Trb
->Adma32Desc
[Index
].UpperLength
= 0;
1582 Trb
->Adma32Desc
[Index
].LowerLength
= 0;
1583 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1585 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1586 if (Remaining
<= AdmaMaxDataPerLine
) {
1587 Trb
->Adma64V3Desc
[Index
].Valid
= 1;
1588 Trb
->Adma64V3Desc
[Index
].Act
= 2;
1589 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1590 Trb
->Adma64V3Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1592 Trb
->Adma64V3Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1593 Trb
->Adma64V3Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1594 Trb
->Adma64V3Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1597 Trb
->Adma64V3Desc
[Index
].Valid
= 1;
1598 Trb
->Adma64V3Desc
[Index
].Act
= 2;
1599 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1600 Trb
->Adma64V3Desc
[Index
].UpperLength
= 0;
1602 Trb
->Adma64V3Desc
[Index
].LowerLength
= 0;
1603 Trb
->Adma64V3Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1604 Trb
->Adma64V3Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1607 if (Remaining
<= AdmaMaxDataPerLine
) {
1608 Trb
->Adma64V4Desc
[Index
].Valid
= 1;
1609 Trb
->Adma64V4Desc
[Index
].Act
= 2;
1610 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1611 Trb
->Adma64V4Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1613 Trb
->Adma64V4Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1614 Trb
->Adma64V4Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1615 Trb
->Adma64V4Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1618 Trb
->Adma64V4Desc
[Index
].Valid
= 1;
1619 Trb
->Adma64V4Desc
[Index
].Act
= 2;
1620 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1621 Trb
->Adma64V4Desc
[Index
].UpperLength
= 0;
1623 Trb
->Adma64V4Desc
[Index
].LowerLength
= 0;
1624 Trb
->Adma64V4Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1625 Trb
->Adma64V4Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1629 Remaining
-= AdmaMaxDataPerLine
;
1630 Address
+= AdmaMaxDataPerLine
;
1634 // Set the last descriptor line as end of descriptor table
1636 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1637 Trb
->Adma32Desc
[Index
].End
= 1;
1638 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1639 Trb
->Adma64V3Desc
[Index
].End
= 1;
1641 Trb
->Adma64V4Desc
[Index
].End
= 1;
1647 Create a new TRB for the SD/MMC cmd request.
1649 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1650 @param[in] Slot The slot number of the SD card to send the command to.
1651 @param[in] Packet A pointer to the SD command data structure.
1652 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1653 not NULL, then nonblocking I/O is performed, and Event
1654 will be signaled when the Packet completes.
1656 @return Created Trb or NULL.
1661 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1663 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
,
1670 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
1671 EFI_PCI_IO_PROTOCOL
*PciIo
;
1674 Trb
= AllocateZeroPool (sizeof (SD_MMC_HC_TRB
));
1679 Trb
->Signature
= SD_MMC_HC_TRB_SIG
;
1681 Trb
->BlockSize
= 0x200;
1682 Trb
->Packet
= Packet
;
1684 Trb
->Started
= FALSE
;
1685 Trb
->Timeout
= Packet
->Timeout
;
1686 Trb
->Private
= Private
;
1688 if ((Packet
->InTransferLength
!= 0) && (Packet
->InDataBuffer
!= NULL
)) {
1689 Trb
->Data
= Packet
->InDataBuffer
;
1690 Trb
->DataLen
= Packet
->InTransferLength
;
1692 } else if ((Packet
->OutTransferLength
!= 0) && (Packet
->OutDataBuffer
!= NULL
)) {
1693 Trb
->Data
= Packet
->OutDataBuffer
;
1694 Trb
->DataLen
= Packet
->OutTransferLength
;
1696 } else if ((Packet
->InTransferLength
== 0) && (Packet
->OutTransferLength
== 0)) {
1703 if ((Trb
->DataLen
!= 0) && (Trb
->DataLen
< Trb
->BlockSize
)) {
1704 Trb
->BlockSize
= (UINT16
)Trb
->DataLen
;
1707 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1708 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1709 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1710 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1711 Trb
->Mode
= SdMmcPioMode
;
1714 Flag
= EfiPciIoOperationBusMasterWrite
;
1716 Flag
= EfiPciIoOperationBusMasterRead
;
1719 PciIo
= Private
->PciIo
;
1720 if (Trb
->DataLen
!= 0) {
1721 MapLength
= Trb
->DataLen
;
1722 Status
= PciIo
->Map (
1730 if (EFI_ERROR (Status
) || (Trb
->DataLen
!= MapLength
)) {
1731 Status
= EFI_BAD_BUFFER_SIZE
;
1736 if (Trb
->DataLen
== 0) {
1737 Trb
->Mode
= SdMmcNoData
;
1738 } else if (Private
->Capability
[Slot
].Adma2
!= 0) {
1739 Trb
->Mode
= SdMmcAdma32bMode
;
1740 Trb
->AdmaLengthMode
= SdMmcAdmaLen16b
;
1741 if ((Private
->ControllerVersion
[Slot
] == SD_MMC_HC_CTRL_VER_300
) &&
1742 (Private
->Capability
[Slot
].SysBus64V3
== 1)) {
1743 Trb
->Mode
= SdMmcAdma64bV3Mode
;
1744 } else if (((Private
->ControllerVersion
[Slot
] == SD_MMC_HC_CTRL_VER_400
) &&
1745 (Private
->Capability
[Slot
].SysBus64V3
== 1)) ||
1746 ((Private
->ControllerVersion
[Slot
] >= SD_MMC_HC_CTRL_VER_410
) &&
1747 (Private
->Capability
[Slot
].SysBus64V4
== 1))) {
1748 Trb
->Mode
= SdMmcAdma64bV4Mode
;
1750 if (Private
->ControllerVersion
[Slot
] >= SD_MMC_HC_CTRL_VER_410
) {
1751 Trb
->AdmaLengthMode
= SdMmcAdmaLen26b
;
1753 Status
= BuildAdmaDescTable (Trb
, Private
->ControllerVersion
[Slot
]);
1754 if (EFI_ERROR (Status
)) {
1755 PciIo
->Unmap (PciIo
, Trb
->DataMap
);
1758 } else if (Private
->Capability
[Slot
].Sdma
!= 0) {
1759 Trb
->Mode
= SdMmcSdmaMode
;
1761 Trb
->Mode
= SdMmcPioMode
;
1765 if (Event
!= NULL
) {
1766 OldTpl
= gBS
->RaiseTPL (TPL_NOTIFY
);
1767 InsertTailList (&Private
->Queue
, &Trb
->TrbList
);
1768 gBS
->RestoreTPL (OldTpl
);
1779 Free the resource used by the TRB.
1781 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1786 IN SD_MMC_HC_TRB
*Trb
1789 EFI_PCI_IO_PROTOCOL
*PciIo
;
1791 PciIo
= Trb
->Private
->PciIo
;
1793 if (Trb
->AdmaMap
!= NULL
) {
1799 if (Trb
->Adma32Desc
!= NULL
) {
1806 if (Trb
->Adma64V3Desc
!= NULL
) {
1813 if (Trb
->Adma64V4Desc
!= NULL
) {
1820 if (Trb
->DataMap
!= NULL
) {
1831 Check if the env is ready for execute specified TRB.
1833 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1834 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1836 @retval EFI_SUCCESS The env is ready for TRB execution.
1837 @retval EFI_NOT_READY The env is not ready for TRB execution.
1838 @retval Others Some erros happen.
1843 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1844 IN SD_MMC_HC_TRB
*Trb
1848 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1849 EFI_PCI_IO_PROTOCOL
*PciIo
;
1850 UINT32 PresentState
;
1852 Packet
= Trb
->Packet
;
1854 if ((Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) ||
1855 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR1b
) ||
1856 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR5b
)) {
1858 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1859 // the Present State register to be 0
1861 PresentState
= BIT0
| BIT1
;
1864 // Wait Command Inhibit (CMD) in the Present State register
1867 PresentState
= BIT0
;
1870 PciIo
= Private
->PciIo
;
1871 Status
= SdMmcHcCheckMmioSet (
1874 SD_MMC_HC_PRESENT_STATE
,
1875 sizeof (PresentState
),
1884 Wait for the env to be ready for execute specified TRB.
1886 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1887 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1889 @retval EFI_SUCCESS The env is ready for TRB execution.
1890 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1891 @retval Others Some erros happen.
1896 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1897 IN SD_MMC_HC_TRB
*Trb
1901 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1903 BOOLEAN InfiniteWait
;
1906 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1908 Packet
= Trb
->Packet
;
1909 Timeout
= Packet
->Timeout
;
1911 InfiniteWait
= TRUE
;
1913 InfiniteWait
= FALSE
;
1916 while (InfiniteWait
|| (Timeout
> 0)) {
1918 // Check Trb execution result by reading Normal Interrupt Status register.
1920 Status
= SdMmcCheckTrbEnv (Private
, Trb
);
1921 if (Status
!= EFI_NOT_READY
) {
1925 // Stall for 1 microsecond.
1936 Execute the specified TRB.
1938 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1939 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1941 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1942 @retval Others Some erros happen when sending this request to the host controller.
1947 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1948 IN SD_MMC_HC_TRB
*Trb
1952 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1953 EFI_PCI_IO_PROTOCOL
*PciIo
;
1963 BOOLEAN AddressingMode64
;
1965 AddressingMode64
= FALSE
;
1967 Packet
= Trb
->Packet
;
1968 PciIo
= Trb
->Private
->PciIo
;
1970 // Clear all bits in Error Interrupt Status Register
1973 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ERR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1974 if (EFI_ERROR (Status
)) {
1978 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1981 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1982 if (EFI_ERROR (Status
)) {
1986 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
1987 Status
= SdMmcHcCheckMmioSet(PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof(UINT16
),
1988 SD_MMC_HC_64_ADDR_EN
, SD_MMC_HC_64_ADDR_EN
);
1989 if (!EFI_ERROR (Status
)) {
1990 AddressingMode64
= TRUE
;
1995 // Set Host Control 1 register DMA Select field
1997 if ((Trb
->Mode
== SdMmcAdma32bMode
) ||
1998 (Trb
->Mode
== SdMmcAdma64bV4Mode
)) {
2000 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
2001 if (EFI_ERROR (Status
)) {
2004 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
2005 HostCtrl1
= BIT4
|BIT3
;
2006 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
2007 if (EFI_ERROR (Status
)) {
2012 SdMmcHcLedOnOff (PciIo
, Trb
->Slot
, TRUE
);
2014 if (Trb
->Mode
== SdMmcSdmaMode
) {
2015 if ((!AddressingMode64
) &&
2016 ((UINT64
)(UINTN
)Trb
->DataPhy
>= 0x100000000ul
)) {
2017 return EFI_INVALID_PARAMETER
;
2020 SdmaAddr
= (UINT64
)(UINTN
)Trb
->DataPhy
;
2022 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2023 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (UINT64
), &SdmaAddr
);
2025 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &SdmaAddr
);
2028 if (EFI_ERROR (Status
)) {
2031 } else if ((Trb
->Mode
== SdMmcAdma32bMode
) ||
2032 (Trb
->Mode
== SdMmcAdma64bV3Mode
) ||
2033 (Trb
->Mode
== SdMmcAdma64bV4Mode
)) {
2034 AdmaAddr
= (UINT64
)(UINTN
)Trb
->AdmaDescPhy
;
2035 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (AdmaAddr
), &AdmaAddr
);
2036 if (EFI_ERROR (Status
)) {
2041 BlkSize
= Trb
->BlockSize
;
2042 if (Trb
->Mode
== SdMmcSdmaMode
) {
2044 // Set SDMA boundary to be 512K bytes.
2049 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_SIZE
, FALSE
, sizeof (BlkSize
), &BlkSize
);
2050 if (EFI_ERROR (Status
)) {
2055 if (Trb
->Mode
!= SdMmcNoData
) {
2057 // Calcuate Block Count.
2059 BlkCount
= (Trb
->DataLen
/ Trb
->BlockSize
);
2061 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_410
) {
2062 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &BlkCount
);
2064 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_COUNT
, FALSE
, sizeof (UINT16
), &BlkCount
);
2066 if (EFI_ERROR (Status
)) {
2070 Argument
= Packet
->SdMmcCmdBlk
->CommandArgument
;
2071 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ARG1
, FALSE
, sizeof (Argument
), &Argument
);
2072 if (EFI_ERROR (Status
)) {
2077 if (Trb
->Mode
!= SdMmcNoData
) {
2078 if (Trb
->Mode
!= SdMmcPioMode
) {
2085 TransMode
|= BIT5
| BIT1
;
2088 // Only SD memory card needs to use AUTO CMD12 feature.
2090 if (Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) {
2097 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_TRANS_MOD
, FALSE
, sizeof (TransMode
), &TransMode
);
2098 if (EFI_ERROR (Status
)) {
2102 Cmd
= (UINT16
)LShiftU64(Packet
->SdMmcCmdBlk
->CommandIndex
, 8);
2103 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) {
2107 // Convert ResponseType to value
2109 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
2110 switch (Packet
->SdMmcCmdBlk
->ResponseType
) {
2111 case SdMmcResponseTypeR1
:
2112 case SdMmcResponseTypeR5
:
2113 case SdMmcResponseTypeR6
:
2114 case SdMmcResponseTypeR7
:
2115 Cmd
|= (BIT1
| BIT3
| BIT4
);
2117 case SdMmcResponseTypeR2
:
2118 Cmd
|= (BIT0
| BIT3
);
2120 case SdMmcResponseTypeR3
:
2121 case SdMmcResponseTypeR4
:
2124 case SdMmcResponseTypeR1b
:
2125 case SdMmcResponseTypeR5b
:
2126 Cmd
|= (BIT0
| BIT1
| BIT3
| BIT4
);
2136 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_COMMAND
, FALSE
, sizeof (Cmd
), &Cmd
);
2141 Performs SW reset based on passed error status mask.
2143 @param[in] Private Pointer to driver private data.
2144 @param[in] Slot Index of the slot to reset.
2145 @param[in] ErrIntStatus Error interrupt status mask.
2147 @retval EFI_SUCCESS Software reset performed successfully.
2148 @retval Other Software reset failed.
2151 SdMmcSoftwareReset (
2152 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2154 IN UINT16 ErrIntStatus
2161 if ((ErrIntStatus
& 0x0F) != 0) {
2164 if ((ErrIntStatus
& 0x70) != 0) {
2168 Status
= SdMmcHcRwMmio (
2176 if (EFI_ERROR (Status
)) {
2180 Status
= SdMmcHcWaitMmioSet (
2187 SD_MMC_HC_GENERIC_TIMEOUT
2189 if (EFI_ERROR (Status
)) {
2197 Checks the error status in error status register
2198 and issues appropriate software reset as described in
2199 SD specification section 3.10.
2201 @param[in] Private Pointer to driver private data.
2202 @param[in] Trb Pointer to currently executing TRB.
2203 @param[in] IntStatus Normal interrupt status mask.
2205 @retval EFI_CRC_ERROR CRC error happened during CMD execution.
2206 @retval EFI_SUCCESS No error reported.
2207 @retval Others Some other error happened.
2211 SdMmcCheckAndRecoverErrors (
2212 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2217 UINT16 ErrIntStatus
;
2219 EFI_STATUS ErrorStatus
;
2221 if ((IntStatus
& BIT15
) == 0) {
2225 Status
= SdMmcHcRwMmio (
2228 SD_MMC_HC_ERR_INT_STS
,
2230 sizeof (ErrIntStatus
),
2233 if (EFI_ERROR (Status
)) {
2238 // If the data timeout error is reported
2239 // but data transfer is signaled as completed we
2240 // have to ignore data timeout. We also assume that no
2241 // other error is present on the link since data transfer
2242 // completed successfully. Error interrupt status
2243 // register is going to be reset when the next command
2246 if (((ErrIntStatus
& BIT4
) != 0) && ((IntStatus
& BIT1
) != 0)) {
2251 // We treat both CMD and DAT CRC errors and
2252 // end bits errors as EFI_CRC_ERROR. This will
2253 // let higher layer know that the error possibly
2254 // happened due to random bus condition and the
2255 // command can be retried.
2257 if ((ErrIntStatus
& (BIT1
| BIT2
| BIT5
| BIT6
)) != 0) {
2258 ErrorStatus
= EFI_CRC_ERROR
;
2260 ErrorStatus
= EFI_DEVICE_ERROR
;
2263 Status
= SdMmcSoftwareReset (Private
, Slot
, ErrIntStatus
);
2264 if (EFI_ERROR (Status
)) {
2272 Check the TRB execution result.
2274 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2275 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2277 @retval EFI_SUCCESS The TRB is executed successfully.
2278 @retval EFI_NOT_READY The TRB is not completed for execution.
2279 @retval Others Some erros happen when executing this request.
2283 SdMmcCheckTrbResult (
2284 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2285 IN SD_MMC_HC_TRB
*Trb
2289 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2296 Packet
= Trb
->Packet
;
2298 // Check Trb execution result by reading Normal Interrupt Status register.
2300 Status
= SdMmcHcRwMmio (
2303 SD_MMC_HC_NOR_INT_STS
,
2308 if (EFI_ERROR (Status
)) {
2313 // Check if there are any errors reported by host controller
2314 // and if neccessary recover the controller before next command is executed.
2316 Status
= SdMmcCheckAndRecoverErrors (Private
, Trb
->Slot
, IntStatus
);
2317 if (EFI_ERROR (Status
)) {
2322 // Check Transfer Complete bit is set or not.
2324 if ((IntStatus
& BIT1
) == BIT1
) {
2329 // Check if DMA interrupt is signalled for the SDMA transfer.
2331 if ((Trb
->Mode
== SdMmcSdmaMode
) && ((IntStatus
& BIT3
) == BIT3
)) {
2333 // Clear DMA interrupt bit.
2336 Status
= SdMmcHcRwMmio (
2339 SD_MMC_HC_NOR_INT_STS
,
2344 if (EFI_ERROR (Status
)) {
2348 // Update SDMA Address register.
2350 SdmaAddr
= SD_MMC_SDMA_ROUND_UP ((UINTN
)Trb
->DataPhy
, SD_MMC_SDMA_BOUNDARY
);
2352 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2353 Status
= SdMmcHcRwMmio (
2356 SD_MMC_HC_ADMA_SYS_ADDR
,
2362 Status
= SdMmcHcRwMmio (
2365 SD_MMC_HC_SDMA_ADDR
,
2372 if (EFI_ERROR (Status
)) {
2375 Trb
->DataPhy
= (UINT64
)(UINTN
)SdmaAddr
;
2378 if ((Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeAdtc
) &&
2379 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR1b
) &&
2380 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR5b
)) {
2381 if ((IntStatus
& BIT0
) == BIT0
) {
2382 Status
= EFI_SUCCESS
;
2387 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
2388 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
2389 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
2390 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
2392 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2393 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2394 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2396 if ((IntStatus
& BIT5
) == BIT5
) {
2398 // Clear Buffer Read Ready interrupt at first.
2401 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
2403 // Read data out from Buffer Port register
2405 for (PioLength
= 0; PioLength
< Trb
->DataLen
; PioLength
+= 4) {
2406 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_BUF_DAT_PORT
, TRUE
, 4, (UINT8
*)Trb
->Data
+ PioLength
);
2408 Status
= EFI_SUCCESS
;
2413 Status
= EFI_NOT_READY
;
2416 // Get response data when the cmd is executed successfully.
2418 if (!EFI_ERROR (Status
)) {
2419 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
2420 for (Index
= 0; Index
< 4; Index
++) {
2421 Status
= SdMmcHcRwMmio (
2424 SD_MMC_HC_RESPONSE
+ Index
* 4,
2429 if (EFI_ERROR (Status
)) {
2430 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
2434 CopyMem (Packet
->SdMmcStatusBlk
, Response
, sizeof (Response
));
2438 if (Status
!= EFI_NOT_READY
) {
2439 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
2446 Wait for the TRB execution result.
2448 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2449 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2451 @retval EFI_SUCCESS The TRB is executed successfully.
2452 @retval Others Some erros happen when executing this request.
2456 SdMmcWaitTrbResult (
2457 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2458 IN SD_MMC_HC_TRB
*Trb
2462 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2464 BOOLEAN InfiniteWait
;
2466 Packet
= Trb
->Packet
;
2468 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2470 Timeout
= Packet
->Timeout
;
2472 InfiniteWait
= TRUE
;
2474 InfiniteWait
= FALSE
;
2477 while (InfiniteWait
|| (Timeout
> 0)) {
2479 // Check Trb execution result by reading Normal Interrupt Status register.
2481 Status
= SdMmcCheckTrbResult (Private
, Trb
);
2482 if (Status
!= EFI_NOT_READY
) {
2486 // Stall for 1 microsecond.