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MdeModulePkg/SdMmcPciHcDxe: Allow additional SDHCI versions
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
4
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
6
7 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include "SdMmcPciHcDxe.h"
19
20 /**
21 Dump the content of SD/MMC host controller's Capability Register.
22
23 @param[in] Slot The slot number of the SD card to send the command to.
24 @param[in] Capability The buffer to store the capability data.
25
26 **/
27 VOID
28 DumpCapabilityReg (
29 IN UINT8 Slot,
30 IN SD_MMC_HC_SLOT_CAP *Capability
31 )
32 {
33 //
34 // Dump Capability Data
35 //
36 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
37 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
38 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
39 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
40 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));
49 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
50 DEBUG ((DEBUG_INFO, " SlotType "));
51 if (Capability->SlotType == 0x00) {
52 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
53 } else if (Capability->SlotType == 0x01) {
54 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
55 } else if (Capability->SlotType == 0x02) {
56 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
57 } else {
58 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
59 }
60 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
66 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
67 if (Capability->TimerCount == 0) {
68 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
69 } else {
70 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
71 }
72 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
73 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
74 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
75 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
76 return;
77 }
78
79 /**
80 Read SlotInfo register from SD/MMC host controller pci config space.
81
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
85
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
88
89 **/
90 EFI_STATUS
91 EFIAPI
92 SdMmcHcGetSlotInfo (
93 IN EFI_PCI_IO_PROTOCOL *PciIo,
94 OUT UINT8 *FirstBar,
95 OUT UINT8 *SlotNum
96 )
97 {
98 EFI_STATUS Status;
99 SD_MMC_HC_SLOT_INFO SlotInfo;
100
101 Status = PciIo->Pci.Read (
102 PciIo,
103 EfiPciIoWidthUint8,
104 SD_MMC_HC_SLOT_OFFSET,
105 sizeof (SlotInfo),
106 &SlotInfo
107 );
108 if (EFI_ERROR (Status)) {
109 return Status;
110 }
111
112 *FirstBar = SlotInfo.FirstBar;
113 *SlotNum = SlotInfo.SlotNum + 1;
114 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
115 return EFI_SUCCESS;
116 }
117
118 /**
119 Read/Write specified SD/MMC host controller mmio register.
120
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
126 memory operation.
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
135
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
139
140 **/
141 EFI_STATUS
142 EFIAPI
143 SdMmcHcRwMmio (
144 IN EFI_PCI_IO_PROTOCOL *PciIo,
145 IN UINT8 BarIndex,
146 IN UINT32 Offset,
147 IN BOOLEAN Read,
148 IN UINT8 Count,
149 IN OUT VOID *Data
150 )
151 {
152 EFI_STATUS Status;
153
154 if ((PciIo == NULL) || (Data == NULL)) {
155 return EFI_INVALID_PARAMETER;
156 }
157
158 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
159 return EFI_INVALID_PARAMETER;
160 }
161
162 if (Read) {
163 Status = PciIo->Mem.Read (
164 PciIo,
165 EfiPciIoWidthUint8,
166 BarIndex,
167 (UINT64) Offset,
168 Count,
169 Data
170 );
171 } else {
172 Status = PciIo->Mem.Write (
173 PciIo,
174 EfiPciIoWidthUint8,
175 BarIndex,
176 (UINT64) Offset,
177 Count,
178 Data
179 );
180 }
181
182 return Status;
183 }
184
185 /**
186 Do OR operation with the value of the specified SD/MMC host controller mmio register.
187
188 @param[in] PciIo The PCI IO protocol instance.
189 @param[in] BarIndex The BAR index of the standard PCI Configuration
190 header to use as the base address for the memory
191 operation to perform.
192 @param[in] Offset The offset within the selected BAR to start the
193 memory operation.
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2 , 4 or 8 bytes.
196 @param[in] OrData The pointer to the data used to do OR operation.
197 The caller is responsible for having ownership of
198 the data buffer and ensuring its size not less than
199 Count bytes.
200
201 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
202 @retval EFI_SUCCESS The OR operation succeeds.
203 @retval Others The OR operation fails.
204
205 **/
206 EFI_STATUS
207 EFIAPI
208 SdMmcHcOrMmio (
209 IN EFI_PCI_IO_PROTOCOL *PciIo,
210 IN UINT8 BarIndex,
211 IN UINT32 Offset,
212 IN UINT8 Count,
213 IN VOID *OrData
214 )
215 {
216 EFI_STATUS Status;
217 UINT64 Data;
218 UINT64 Or;
219
220 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
221 if (EFI_ERROR (Status)) {
222 return Status;
223 }
224
225 if (Count == 1) {
226 Or = *(UINT8*) OrData;
227 } else if (Count == 2) {
228 Or = *(UINT16*) OrData;
229 } else if (Count == 4) {
230 Or = *(UINT32*) OrData;
231 } else if (Count == 8) {
232 Or = *(UINT64*) OrData;
233 } else {
234 return EFI_INVALID_PARAMETER;
235 }
236
237 Data |= Or;
238 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
239
240 return Status;
241 }
242
243 /**
244 Do AND operation with the value of the specified SD/MMC host controller mmio register.
245
246 @param[in] PciIo The PCI IO protocol instance.
247 @param[in] BarIndex The BAR index of the standard PCI Configuration
248 header to use as the base address for the memory
249 operation to perform.
250 @param[in] Offset The offset within the selected BAR to start the
251 memory operation.
252 @param[in] Count The width of the mmio register in bytes.
253 Must be 1, 2 , 4 or 8 bytes.
254 @param[in] AndData The pointer to the data used to do AND operation.
255 The caller is responsible for having ownership of
256 the data buffer and ensuring its size not less than
257 Count bytes.
258
259 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
260 @retval EFI_SUCCESS The AND operation succeeds.
261 @retval Others The AND operation fails.
262
263 **/
264 EFI_STATUS
265 EFIAPI
266 SdMmcHcAndMmio (
267 IN EFI_PCI_IO_PROTOCOL *PciIo,
268 IN UINT8 BarIndex,
269 IN UINT32 Offset,
270 IN UINT8 Count,
271 IN VOID *AndData
272 )
273 {
274 EFI_STATUS Status;
275 UINT64 Data;
276 UINT64 And;
277
278 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
279 if (EFI_ERROR (Status)) {
280 return Status;
281 }
282
283 if (Count == 1) {
284 And = *(UINT8*) AndData;
285 } else if (Count == 2) {
286 And = *(UINT16*) AndData;
287 } else if (Count == 4) {
288 And = *(UINT32*) AndData;
289 } else if (Count == 8) {
290 And = *(UINT64*) AndData;
291 } else {
292 return EFI_INVALID_PARAMETER;
293 }
294
295 Data &= And;
296 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
297
298 return Status;
299 }
300
301 /**
302 Wait for the value of the specified MMIO register set to the test value.
303
304 @param[in] PciIo The PCI IO protocol instance.
305 @param[in] BarIndex The BAR index of the standard PCI Configuration
306 header to use as the base address for the memory
307 operation to perform.
308 @param[in] Offset The offset within the selected BAR to start the
309 memory operation.
310 @param[in] Count The width of the mmio register in bytes.
311 Must be 1, 2, 4 or 8 bytes.
312 @param[in] MaskValue The mask value of memory.
313 @param[in] TestValue The test value of memory.
314
315 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
316 @retval EFI_SUCCESS The MMIO register has expected value.
317 @retval Others The MMIO operation fails.
318
319 **/
320 EFI_STATUS
321 EFIAPI
322 SdMmcHcCheckMmioSet (
323 IN EFI_PCI_IO_PROTOCOL *PciIo,
324 IN UINT8 BarIndex,
325 IN UINT32 Offset,
326 IN UINT8 Count,
327 IN UINT64 MaskValue,
328 IN UINT64 TestValue
329 )
330 {
331 EFI_STATUS Status;
332 UINT64 Value;
333
334 //
335 // Access PCI MMIO space to see if the value is the tested one.
336 //
337 Value = 0;
338 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
339 if (EFI_ERROR (Status)) {
340 return Status;
341 }
342
343 Value &= MaskValue;
344
345 if (Value == TestValue) {
346 return EFI_SUCCESS;
347 }
348
349 return EFI_NOT_READY;
350 }
351
352 /**
353 Wait for the value of the specified MMIO register set to the test value.
354
355 @param[in] PciIo The PCI IO protocol instance.
356 @param[in] BarIndex The BAR index of the standard PCI Configuration
357 header to use as the base address for the memory
358 operation to perform.
359 @param[in] Offset The offset within the selected BAR to start the
360 memory operation.
361 @param[in] Count The width of the mmio register in bytes.
362 Must be 1, 2, 4 or 8 bytes.
363 @param[in] MaskValue The mask value of memory.
364 @param[in] TestValue The test value of memory.
365 @param[in] Timeout The time out value for wait memory set, uses 1
366 microsecond as a unit.
367
368 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
369 range.
370 @retval EFI_SUCCESS The MMIO register has expected value.
371 @retval Others The MMIO operation fails.
372
373 **/
374 EFI_STATUS
375 EFIAPI
376 SdMmcHcWaitMmioSet (
377 IN EFI_PCI_IO_PROTOCOL *PciIo,
378 IN UINT8 BarIndex,
379 IN UINT32 Offset,
380 IN UINT8 Count,
381 IN UINT64 MaskValue,
382 IN UINT64 TestValue,
383 IN UINT64 Timeout
384 )
385 {
386 EFI_STATUS Status;
387 BOOLEAN InfiniteWait;
388
389 if (Timeout == 0) {
390 InfiniteWait = TRUE;
391 } else {
392 InfiniteWait = FALSE;
393 }
394
395 while (InfiniteWait || (Timeout > 0)) {
396 Status = SdMmcHcCheckMmioSet (
397 PciIo,
398 BarIndex,
399 Offset,
400 Count,
401 MaskValue,
402 TestValue
403 );
404 if (Status != EFI_NOT_READY) {
405 return Status;
406 }
407
408 //
409 // Stall for 1 microsecond.
410 //
411 gBS->Stall (1);
412
413 Timeout--;
414 }
415
416 return EFI_TIMEOUT;
417 }
418
419 /**
420 Software reset the specified SD/MMC host controller and enable all interrupts.
421
422 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
423 @param[in] Slot The slot number of the SD card to send the command to.
424
425 @retval EFI_SUCCESS The software reset executes successfully.
426 @retval Others The software reset fails.
427
428 **/
429 EFI_STATUS
430 SdMmcHcReset (
431 IN SD_MMC_HC_PRIVATE_DATA *Private,
432 IN UINT8 Slot
433 )
434 {
435 EFI_STATUS Status;
436 UINT8 SwReset;
437 EFI_PCI_IO_PROTOCOL *PciIo;
438
439 //
440 // Notify the SD/MMC override protocol that we are about to reset
441 // the SD/MMC host controller.
442 //
443 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
444 Status = mOverride->NotifyPhase (
445 Private->ControllerHandle,
446 Slot,
447 EdkiiSdMmcResetPre);
448 if (EFI_ERROR (Status)) {
449 DEBUG ((DEBUG_WARN,
450 "%a: SD/MMC pre reset notifier callback failed - %r\n",
451 __FUNCTION__, Status));
452 return Status;
453 }
454 }
455
456 PciIo = Private->PciIo;
457 SwReset = BIT0;
458 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
459
460 if (EFI_ERROR (Status)) {
461 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
462 return Status;
463 }
464
465 Status = SdMmcHcWaitMmioSet (
466 PciIo,
467 Slot,
468 SD_MMC_HC_SW_RST,
469 sizeof (SwReset),
470 BIT0,
471 0x00,
472 SD_MMC_HC_GENERIC_TIMEOUT
473 );
474 if (EFI_ERROR (Status)) {
475 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
476 return Status;
477 }
478
479 //
480 // Enable all interrupt after reset all.
481 //
482 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
483 if (EFI_ERROR (Status)) {
484 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
485 Status));
486 return Status;
487 }
488
489 //
490 // Notify the SD/MMC override protocol that we have just reset
491 // the SD/MMC host controller.
492 //
493 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
494 Status = mOverride->NotifyPhase (
495 Private->ControllerHandle,
496 Slot,
497 EdkiiSdMmcResetPost);
498 if (EFI_ERROR (Status)) {
499 DEBUG ((DEBUG_WARN,
500 "%a: SD/MMC post reset notifier callback failed - %r\n",
501 __FUNCTION__, Status));
502 }
503 }
504
505 return Status;
506 }
507
508 /**
509 Set all interrupt status bits in Normal and Error Interrupt Status Enable
510 register.
511
512 @param[in] PciIo The PCI IO protocol instance.
513 @param[in] Slot The slot number of the SD card to send the command to.
514
515 @retval EFI_SUCCESS The operation executes successfully.
516 @retval Others The operation fails.
517
518 **/
519 EFI_STATUS
520 SdMmcHcEnableInterrupt (
521 IN EFI_PCI_IO_PROTOCOL *PciIo,
522 IN UINT8 Slot
523 )
524 {
525 EFI_STATUS Status;
526 UINT16 IntStatus;
527
528 //
529 // Enable all bits in Error Interrupt Status Enable Register
530 //
531 IntStatus = 0xFFFF;
532 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
533 if (EFI_ERROR (Status)) {
534 return Status;
535 }
536 //
537 // Enable all bits in Normal Interrupt Status Enable Register
538 //
539 IntStatus = 0xFFFF;
540 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
541
542 return Status;
543 }
544
545 /**
546 Get the capability data from the specified slot.
547
548 @param[in] PciIo The PCI IO protocol instance.
549 @param[in] Slot The slot number of the SD card to send the command to.
550 @param[out] Capability The buffer to store the capability data.
551
552 @retval EFI_SUCCESS The operation executes successfully.
553 @retval Others The operation fails.
554
555 **/
556 EFI_STATUS
557 SdMmcHcGetCapability (
558 IN EFI_PCI_IO_PROTOCOL *PciIo,
559 IN UINT8 Slot,
560 OUT SD_MMC_HC_SLOT_CAP *Capability
561 )
562 {
563 EFI_STATUS Status;
564 UINT64 Cap;
565
566 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
567 if (EFI_ERROR (Status)) {
568 return Status;
569 }
570
571 CopyMem (Capability, &Cap, sizeof (Cap));
572
573 return EFI_SUCCESS;
574 }
575
576 /**
577 Get the maximum current capability data from the specified slot.
578
579 @param[in] PciIo The PCI IO protocol instance.
580 @param[in] Slot The slot number of the SD card to send the command to.
581 @param[out] MaxCurrent The buffer to store the maximum current capability data.
582
583 @retval EFI_SUCCESS The operation executes successfully.
584 @retval Others The operation fails.
585
586 **/
587 EFI_STATUS
588 SdMmcHcGetMaxCurrent (
589 IN EFI_PCI_IO_PROTOCOL *PciIo,
590 IN UINT8 Slot,
591 OUT UINT64 *MaxCurrent
592 )
593 {
594 EFI_STATUS Status;
595
596 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
597
598 return Status;
599 }
600
601 /**
602 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
603 slot.
604
605 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
606
607 @param[in] PciIo The PCI IO protocol instance.
608 @param[in] Slot The slot number of the SD card to send the command to.
609 @param[out] MediaPresent The pointer to the media present boolean value.
610
611 @retval EFI_SUCCESS There is no media change happened.
612 @retval EFI_MEDIA_CHANGED There is media change happened.
613 @retval Others The detection fails.
614
615 **/
616 EFI_STATUS
617 SdMmcHcCardDetect (
618 IN EFI_PCI_IO_PROTOCOL *PciIo,
619 IN UINT8 Slot,
620 OUT BOOLEAN *MediaPresent
621 )
622 {
623 EFI_STATUS Status;
624 UINT16 Data;
625 UINT32 PresentState;
626
627 //
628 // Check Present State Register to see if there is a card presented.
629 //
630 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
631 if (EFI_ERROR (Status)) {
632 return Status;
633 }
634
635 if ((PresentState & BIT16) != 0) {
636 *MediaPresent = TRUE;
637 } else {
638 *MediaPresent = FALSE;
639 }
640
641 //
642 // Check Normal Interrupt Status Register
643 //
644 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
645 if (EFI_ERROR (Status)) {
646 return Status;
647 }
648
649 if ((Data & (BIT6 | BIT7)) != 0) {
650 //
651 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
652 //
653 Data &= BIT6 | BIT7;
654 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
655 if (EFI_ERROR (Status)) {
656 return Status;
657 }
658
659 return EFI_MEDIA_CHANGED;
660 }
661
662 return EFI_SUCCESS;
663 }
664
665 /**
666 Stop SD/MMC card clock.
667
668 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
669
670 @param[in] PciIo The PCI IO protocol instance.
671 @param[in] Slot The slot number of the SD card to send the command to.
672
673 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
674 @retval Others Fail to stop SD/MMC clock.
675
676 **/
677 EFI_STATUS
678 SdMmcHcStopClock (
679 IN EFI_PCI_IO_PROTOCOL *PciIo,
680 IN UINT8 Slot
681 )
682 {
683 EFI_STATUS Status;
684 UINT32 PresentState;
685 UINT16 ClockCtrl;
686
687 //
688 // Ensure no SD transactions are occurring on the SD Bus by
689 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
690 // in the Present State register to be 0.
691 //
692 Status = SdMmcHcWaitMmioSet (
693 PciIo,
694 Slot,
695 SD_MMC_HC_PRESENT_STATE,
696 sizeof (PresentState),
697 BIT0 | BIT1,
698 0,
699 SD_MMC_HC_GENERIC_TIMEOUT
700 );
701 if (EFI_ERROR (Status)) {
702 return Status;
703 }
704
705 //
706 // Set SD Clock Enable in the Clock Control register to 0
707 //
708 ClockCtrl = (UINT16)~BIT2;
709 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
710
711 return Status;
712 }
713
714 /**
715 SD/MMC card clock supply.
716
717 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
718
719 @param[in] PciIo The PCI IO protocol instance.
720 @param[in] Slot The slot number of the SD card to send the command to.
721 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
722 @param[in] Capability The capability of the slot.
723
724 @retval EFI_SUCCESS The clock is supplied successfully.
725 @retval Others The clock isn't supplied successfully.
726
727 **/
728 EFI_STATUS
729 SdMmcHcClockSupply (
730 IN EFI_PCI_IO_PROTOCOL *PciIo,
731 IN UINT8 Slot,
732 IN UINT64 ClockFreq,
733 IN SD_MMC_HC_SLOT_CAP Capability
734 )
735 {
736 EFI_STATUS Status;
737 UINT32 BaseClkFreq;
738 UINT32 SettingFreq;
739 UINT32 Divisor;
740 UINT32 Remainder;
741 UINT16 ControllerVer;
742 UINT16 ClockCtrl;
743
744 //
745 // Calculate a divisor for SD clock frequency
746 //
747 ASSERT (Capability.BaseClkFreq != 0);
748
749 BaseClkFreq = Capability.BaseClkFreq;
750 if (ClockFreq == 0) {
751 return EFI_INVALID_PARAMETER;
752 }
753
754 if (ClockFreq > (BaseClkFreq * 1000)) {
755 ClockFreq = BaseClkFreq * 1000;
756 }
757
758 //
759 // Calculate the divisor of base frequency.
760 //
761 Divisor = 0;
762 SettingFreq = BaseClkFreq * 1000;
763 while (ClockFreq < SettingFreq) {
764 Divisor++;
765
766 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
767 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
768 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
769 break;
770 }
771 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
772 SettingFreq ++;
773 }
774 }
775
776 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
777
778 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
779 if (EFI_ERROR (Status)) {
780 return Status;
781 }
782 //
783 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
784 //
785 if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) &&
786 ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) {
787 ASSERT (Divisor <= 0x3FF);
788 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
789 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
790 //
791 // Only the most significant bit can be used as divisor.
792 //
793 if (((Divisor - 1) & Divisor) != 0) {
794 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
795 }
796 ASSERT (Divisor <= 0x80);
797 ClockCtrl = (Divisor & 0xFF) << 8;
798 } else {
799 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
800 return EFI_UNSUPPORTED;
801 }
802
803 //
804 // Stop bus clock at first
805 //
806 Status = SdMmcHcStopClock (PciIo, Slot);
807 if (EFI_ERROR (Status)) {
808 return Status;
809 }
810
811 //
812 // Supply clock frequency with specified divisor
813 //
814 ClockCtrl |= BIT0;
815 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
816 if (EFI_ERROR (Status)) {
817 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
818 return Status;
819 }
820
821 //
822 // Wait Internal Clock Stable in the Clock Control register to be 1
823 //
824 Status = SdMmcHcWaitMmioSet (
825 PciIo,
826 Slot,
827 SD_MMC_HC_CLOCK_CTRL,
828 sizeof (ClockCtrl),
829 BIT1,
830 BIT1,
831 SD_MMC_HC_GENERIC_TIMEOUT
832 );
833 if (EFI_ERROR (Status)) {
834 return Status;
835 }
836
837 //
838 // Set SD Clock Enable in the Clock Control register to 1
839 //
840 ClockCtrl = BIT2;
841 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
842
843 return Status;
844 }
845
846 /**
847 SD/MMC bus power control.
848
849 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
850
851 @param[in] PciIo The PCI IO protocol instance.
852 @param[in] Slot The slot number of the SD card to send the command to.
853 @param[in] PowerCtrl The value setting to the power control register.
854
855 @retval TRUE There is a SD/MMC card attached.
856 @retval FALSE There is no a SD/MMC card attached.
857
858 **/
859 EFI_STATUS
860 SdMmcHcPowerControl (
861 IN EFI_PCI_IO_PROTOCOL *PciIo,
862 IN UINT8 Slot,
863 IN UINT8 PowerCtrl
864 )
865 {
866 EFI_STATUS Status;
867
868 //
869 // Clr SD Bus Power
870 //
871 PowerCtrl &= (UINT8)~BIT0;
872 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
873 if (EFI_ERROR (Status)) {
874 return Status;
875 }
876
877 //
878 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
879 //
880 PowerCtrl |= BIT0;
881 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
882
883 return Status;
884 }
885
886 /**
887 Set the SD/MMC bus width.
888
889 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
890
891 @param[in] PciIo The PCI IO protocol instance.
892 @param[in] Slot The slot number of the SD card to send the command to.
893 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
894
895 @retval EFI_SUCCESS The bus width is set successfully.
896 @retval Others The bus width isn't set successfully.
897
898 **/
899 EFI_STATUS
900 SdMmcHcSetBusWidth (
901 IN EFI_PCI_IO_PROTOCOL *PciIo,
902 IN UINT8 Slot,
903 IN UINT16 BusWidth
904 )
905 {
906 EFI_STATUS Status;
907 UINT8 HostCtrl1;
908
909 if (BusWidth == 1) {
910 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
911 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
912 } else if (BusWidth == 4) {
913 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
914 if (EFI_ERROR (Status)) {
915 return Status;
916 }
917 HostCtrl1 |= BIT1;
918 HostCtrl1 &= (UINT8)~BIT5;
919 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
920 } else if (BusWidth == 8) {
921 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
922 if (EFI_ERROR (Status)) {
923 return Status;
924 }
925 HostCtrl1 &= (UINT8)~BIT1;
926 HostCtrl1 |= BIT5;
927 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
928 } else {
929 ASSERT (FALSE);
930 return EFI_INVALID_PARAMETER;
931 }
932
933 return Status;
934 }
935
936 /**
937 Supply SD/MMC card with lowest clock frequency at initialization.
938
939 @param[in] PciIo The PCI IO protocol instance.
940 @param[in] Slot The slot number of the SD card to send the command to.
941 @param[in] Capability The capability of the slot.
942
943 @retval EFI_SUCCESS The clock is supplied successfully.
944 @retval Others The clock isn't supplied successfully.
945
946 **/
947 EFI_STATUS
948 SdMmcHcInitClockFreq (
949 IN EFI_PCI_IO_PROTOCOL *PciIo,
950 IN UINT8 Slot,
951 IN SD_MMC_HC_SLOT_CAP Capability
952 )
953 {
954 EFI_STATUS Status;
955 UINT32 InitFreq;
956
957 //
958 // Calculate a divisor for SD clock frequency
959 //
960 if (Capability.BaseClkFreq == 0) {
961 //
962 // Don't support get Base Clock Frequency information via another method
963 //
964 return EFI_UNSUPPORTED;
965 }
966 //
967 // Supply 400KHz clock frequency at initialization phase.
968 //
969 InitFreq = 400;
970 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
971 return Status;
972 }
973
974 /**
975 Supply SD/MMC card with maximum voltage at initialization.
976
977 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
978
979 @param[in] PciIo The PCI IO protocol instance.
980 @param[in] Slot The slot number of the SD card to send the command to.
981 @param[in] Capability The capability of the slot.
982
983 @retval EFI_SUCCESS The voltage is supplied successfully.
984 @retval Others The voltage isn't supplied successfully.
985
986 **/
987 EFI_STATUS
988 SdMmcHcInitPowerVoltage (
989 IN EFI_PCI_IO_PROTOCOL *PciIo,
990 IN UINT8 Slot,
991 IN SD_MMC_HC_SLOT_CAP Capability
992 )
993 {
994 EFI_STATUS Status;
995 UINT8 MaxVoltage;
996 UINT8 HostCtrl2;
997
998 //
999 // Calculate supported maximum voltage according to SD Bus Voltage Select
1000 //
1001 if (Capability.Voltage33 != 0) {
1002 //
1003 // Support 3.3V
1004 //
1005 MaxVoltage = 0x0E;
1006 } else if (Capability.Voltage30 != 0) {
1007 //
1008 // Support 3.0V
1009 //
1010 MaxVoltage = 0x0C;
1011 } else if (Capability.Voltage18 != 0) {
1012 //
1013 // Support 1.8V
1014 //
1015 MaxVoltage = 0x0A;
1016 HostCtrl2 = BIT3;
1017 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1018 gBS->Stall (5000);
1019 if (EFI_ERROR (Status)) {
1020 return Status;
1021 }
1022 } else {
1023 ASSERT (FALSE);
1024 return EFI_DEVICE_ERROR;
1025 }
1026
1027 //
1028 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1029 //
1030 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1031
1032 return Status;
1033 }
1034
1035 /**
1036 Initialize the Timeout Control register with most conservative value at initialization.
1037
1038 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1039
1040 @param[in] PciIo The PCI IO protocol instance.
1041 @param[in] Slot The slot number of the SD card to send the command to.
1042
1043 @retval EFI_SUCCESS The timeout control register is configured successfully.
1044 @retval Others The timeout control register isn't configured successfully.
1045
1046 **/
1047 EFI_STATUS
1048 SdMmcHcInitTimeoutCtrl (
1049 IN EFI_PCI_IO_PROTOCOL *PciIo,
1050 IN UINT8 Slot
1051 )
1052 {
1053 EFI_STATUS Status;
1054 UINT8 Timeout;
1055
1056 Timeout = 0x0E;
1057 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1058
1059 return Status;
1060 }
1061
1062 /**
1063 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1064 at initialization.
1065
1066 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1067 @param[in] Slot The slot number of the SD card to send the command to.
1068
1069 @retval EFI_SUCCESS The host controller is initialized successfully.
1070 @retval Others The host controller isn't initialized successfully.
1071
1072 **/
1073 EFI_STATUS
1074 SdMmcHcInitHost (
1075 IN SD_MMC_HC_PRIVATE_DATA *Private,
1076 IN UINT8 Slot
1077 )
1078 {
1079 EFI_STATUS Status;
1080 EFI_PCI_IO_PROTOCOL *PciIo;
1081 SD_MMC_HC_SLOT_CAP Capability;
1082
1083 //
1084 // Notify the SD/MMC override protocol that we are about to initialize
1085 // the SD/MMC host controller.
1086 //
1087 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1088 Status = mOverride->NotifyPhase (
1089 Private->ControllerHandle,
1090 Slot,
1091 EdkiiSdMmcInitHostPre);
1092 if (EFI_ERROR (Status)) {
1093 DEBUG ((DEBUG_WARN,
1094 "%a: SD/MMC pre init notifier callback failed - %r\n",
1095 __FUNCTION__, Status));
1096 return Status;
1097 }
1098 }
1099
1100 PciIo = Private->PciIo;
1101 Capability = Private->Capability[Slot];
1102
1103 Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
1104 if (EFI_ERROR (Status)) {
1105 return Status;
1106 }
1107
1108 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1109 if (EFI_ERROR (Status)) {
1110 return Status;
1111 }
1112
1113 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1114 if (EFI_ERROR (Status)) {
1115 return Status;
1116 }
1117
1118 //
1119 // Notify the SD/MMC override protocol that we are have just initialized
1120 // the SD/MMC host controller.
1121 //
1122 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1123 Status = mOverride->NotifyPhase (
1124 Private->ControllerHandle,
1125 Slot,
1126 EdkiiSdMmcInitHostPost);
1127 if (EFI_ERROR (Status)) {
1128 DEBUG ((DEBUG_WARN,
1129 "%a: SD/MMC post init notifier callback failed - %r\n",
1130 __FUNCTION__, Status));
1131 }
1132 }
1133 return Status;
1134 }
1135
1136 /**
1137 Turn on/off LED.
1138
1139 @param[in] PciIo The PCI IO protocol instance.
1140 @param[in] Slot The slot number of the SD card to send the command to.
1141 @param[in] On The boolean to turn on/off LED.
1142
1143 @retval EFI_SUCCESS The LED is turned on/off successfully.
1144 @retval Others The LED isn't turned on/off successfully.
1145
1146 **/
1147 EFI_STATUS
1148 SdMmcHcLedOnOff (
1149 IN EFI_PCI_IO_PROTOCOL *PciIo,
1150 IN UINT8 Slot,
1151 IN BOOLEAN On
1152 )
1153 {
1154 EFI_STATUS Status;
1155 UINT8 HostCtrl1;
1156
1157 if (On) {
1158 HostCtrl1 = BIT0;
1159 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1160 } else {
1161 HostCtrl1 = (UINT8)~BIT0;
1162 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1163 }
1164
1165 return Status;
1166 }
1167
1168 /**
1169 Build ADMA descriptor table for transfer.
1170
1171 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
1172
1173 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1174
1175 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1176 @retval Others The ADMA descriptor table isn't created successfully.
1177
1178 **/
1179 EFI_STATUS
1180 BuildAdmaDescTable (
1181 IN SD_MMC_HC_TRB *Trb
1182 )
1183 {
1184 EFI_PHYSICAL_ADDRESS Data;
1185 UINT64 DataLen;
1186 UINT64 Entries;
1187 UINT32 Index;
1188 UINT64 Remaining;
1189 UINT32 Address;
1190 UINTN TableSize;
1191 EFI_PCI_IO_PROTOCOL *PciIo;
1192 EFI_STATUS Status;
1193 UINTN Bytes;
1194
1195 Data = Trb->DataPhy;
1196 DataLen = Trb->DataLen;
1197 PciIo = Trb->Private->PciIo;
1198 //
1199 // Only support 32bit ADMA Descriptor Table
1200 //
1201 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
1202 return EFI_INVALID_PARAMETER;
1203 }
1204 //
1205 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1206 // for 32-bit address descriptor table.
1207 //
1208 if ((Data & (BIT0 | BIT1)) != 0) {
1209 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1210 }
1211
1212 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
1213 TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));
1214 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1215 Status = PciIo->AllocateBuffer (
1216 PciIo,
1217 AllocateAnyPages,
1218 EfiBootServicesData,
1219 EFI_SIZE_TO_PAGES (TableSize),
1220 (VOID **)&Trb->AdmaDesc,
1221 0
1222 );
1223 if (EFI_ERROR (Status)) {
1224 return EFI_OUT_OF_RESOURCES;
1225 }
1226 ZeroMem (Trb->AdmaDesc, TableSize);
1227 Bytes = TableSize;
1228 Status = PciIo->Map (
1229 PciIo,
1230 EfiPciIoOperationBusMasterCommonBuffer,
1231 Trb->AdmaDesc,
1232 &Bytes,
1233 &Trb->AdmaDescPhy,
1234 &Trb->AdmaMap
1235 );
1236
1237 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1238 //
1239 // Map error or unable to map the whole RFis buffer into a contiguous region.
1240 //
1241 PciIo->FreeBuffer (
1242 PciIo,
1243 EFI_SIZE_TO_PAGES (TableSize),
1244 Trb->AdmaDesc
1245 );
1246 return EFI_OUT_OF_RESOURCES;
1247 }
1248
1249 if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1250 //
1251 // The ADMA doesn't support 64bit addressing.
1252 //
1253 PciIo->Unmap (
1254 PciIo,
1255 Trb->AdmaMap
1256 );
1257 PciIo->FreeBuffer (
1258 PciIo,
1259 EFI_SIZE_TO_PAGES (TableSize),
1260 Trb->AdmaDesc
1261 );
1262 return EFI_DEVICE_ERROR;
1263 }
1264
1265 Remaining = DataLen;
1266 Address = (UINT32)Data;
1267 for (Index = 0; Index < Entries; Index++) {
1268 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
1269 Trb->AdmaDesc[Index].Valid = 1;
1270 Trb->AdmaDesc[Index].Act = 2;
1271 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
1272 Trb->AdmaDesc[Index].Address = Address;
1273 break;
1274 } else {
1275 Trb->AdmaDesc[Index].Valid = 1;
1276 Trb->AdmaDesc[Index].Act = 2;
1277 Trb->AdmaDesc[Index].Length = 0;
1278 Trb->AdmaDesc[Index].Address = Address;
1279 }
1280
1281 Remaining -= ADMA_MAX_DATA_PER_LINE;
1282 Address += ADMA_MAX_DATA_PER_LINE;
1283 }
1284
1285 //
1286 // Set the last descriptor line as end of descriptor table
1287 //
1288 Trb->AdmaDesc[Index].End = 1;
1289 return EFI_SUCCESS;
1290 }
1291
1292 /**
1293 Create a new TRB for the SD/MMC cmd request.
1294
1295 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1296 @param[in] Slot The slot number of the SD card to send the command to.
1297 @param[in] Packet A pointer to the SD command data structure.
1298 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1299 not NULL, then nonblocking I/O is performed, and Event
1300 will be signaled when the Packet completes.
1301
1302 @return Created Trb or NULL.
1303
1304 **/
1305 SD_MMC_HC_TRB *
1306 SdMmcCreateTrb (
1307 IN SD_MMC_HC_PRIVATE_DATA *Private,
1308 IN UINT8 Slot,
1309 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1310 IN EFI_EVENT Event
1311 )
1312 {
1313 SD_MMC_HC_TRB *Trb;
1314 EFI_STATUS Status;
1315 EFI_TPL OldTpl;
1316 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1317 EFI_PCI_IO_PROTOCOL *PciIo;
1318 UINTN MapLength;
1319
1320 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1321 if (Trb == NULL) {
1322 return NULL;
1323 }
1324
1325 Trb->Signature = SD_MMC_HC_TRB_SIG;
1326 Trb->Slot = Slot;
1327 Trb->BlockSize = 0x200;
1328 Trb->Packet = Packet;
1329 Trb->Event = Event;
1330 Trb->Started = FALSE;
1331 Trb->Timeout = Packet->Timeout;
1332 Trb->Private = Private;
1333
1334 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1335 Trb->Data = Packet->InDataBuffer;
1336 Trb->DataLen = Packet->InTransferLength;
1337 Trb->Read = TRUE;
1338 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1339 Trb->Data = Packet->OutDataBuffer;
1340 Trb->DataLen = Packet->OutTransferLength;
1341 Trb->Read = FALSE;
1342 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1343 Trb->Data = NULL;
1344 Trb->DataLen = 0;
1345 } else {
1346 goto Error;
1347 }
1348
1349 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1350 Trb->BlockSize = (UINT16)Trb->DataLen;
1351 }
1352
1353 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1354 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1355 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1356 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1357 Trb->Mode = SdMmcPioMode;
1358 } else {
1359 if (Trb->Read) {
1360 Flag = EfiPciIoOperationBusMasterWrite;
1361 } else {
1362 Flag = EfiPciIoOperationBusMasterRead;
1363 }
1364
1365 PciIo = Private->PciIo;
1366 if (Trb->DataLen != 0) {
1367 MapLength = Trb->DataLen;
1368 Status = PciIo->Map (
1369 PciIo,
1370 Flag,
1371 Trb->Data,
1372 &MapLength,
1373 &Trb->DataPhy,
1374 &Trb->DataMap
1375 );
1376 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1377 Status = EFI_BAD_BUFFER_SIZE;
1378 goto Error;
1379 }
1380 }
1381
1382 if (Trb->DataLen == 0) {
1383 Trb->Mode = SdMmcNoData;
1384 } else if (Private->Capability[Slot].Adma2 != 0) {
1385 Trb->Mode = SdMmcAdmaMode;
1386 Status = BuildAdmaDescTable (Trb);
1387 if (EFI_ERROR (Status)) {
1388 PciIo->Unmap (PciIo, Trb->DataMap);
1389 goto Error;
1390 }
1391 } else if (Private->Capability[Slot].Sdma != 0) {
1392 Trb->Mode = SdMmcSdmaMode;
1393 } else {
1394 Trb->Mode = SdMmcPioMode;
1395 }
1396 }
1397
1398 if (Event != NULL) {
1399 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1400 InsertTailList (&Private->Queue, &Trb->TrbList);
1401 gBS->RestoreTPL (OldTpl);
1402 }
1403
1404 return Trb;
1405
1406 Error:
1407 SdMmcFreeTrb (Trb);
1408 return NULL;
1409 }
1410
1411 /**
1412 Free the resource used by the TRB.
1413
1414 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1415
1416 **/
1417 VOID
1418 SdMmcFreeTrb (
1419 IN SD_MMC_HC_TRB *Trb
1420 )
1421 {
1422 EFI_PCI_IO_PROTOCOL *PciIo;
1423
1424 PciIo = Trb->Private->PciIo;
1425
1426 if (Trb->AdmaMap != NULL) {
1427 PciIo->Unmap (
1428 PciIo,
1429 Trb->AdmaMap
1430 );
1431 }
1432 if (Trb->AdmaDesc != NULL) {
1433 PciIo->FreeBuffer (
1434 PciIo,
1435 Trb->AdmaPages,
1436 Trb->AdmaDesc
1437 );
1438 }
1439 if (Trb->DataMap != NULL) {
1440 PciIo->Unmap (
1441 PciIo,
1442 Trb->DataMap
1443 );
1444 }
1445 FreePool (Trb);
1446 return;
1447 }
1448
1449 /**
1450 Check if the env is ready for execute specified TRB.
1451
1452 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1453 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1454
1455 @retval EFI_SUCCESS The env is ready for TRB execution.
1456 @retval EFI_NOT_READY The env is not ready for TRB execution.
1457 @retval Others Some erros happen.
1458
1459 **/
1460 EFI_STATUS
1461 SdMmcCheckTrbEnv (
1462 IN SD_MMC_HC_PRIVATE_DATA *Private,
1463 IN SD_MMC_HC_TRB *Trb
1464 )
1465 {
1466 EFI_STATUS Status;
1467 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1468 EFI_PCI_IO_PROTOCOL *PciIo;
1469 UINT32 PresentState;
1470
1471 Packet = Trb->Packet;
1472
1473 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1474 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1475 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1476 //
1477 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1478 // the Present State register to be 0
1479 //
1480 PresentState = BIT0 | BIT1;
1481 } else {
1482 //
1483 // Wait Command Inhibit (CMD) in the Present State register
1484 // to be 0
1485 //
1486 PresentState = BIT0;
1487 }
1488
1489 PciIo = Private->PciIo;
1490 Status = SdMmcHcCheckMmioSet (
1491 PciIo,
1492 Trb->Slot,
1493 SD_MMC_HC_PRESENT_STATE,
1494 sizeof (PresentState),
1495 PresentState,
1496 0
1497 );
1498
1499 return Status;
1500 }
1501
1502 /**
1503 Wait for the env to be ready for execute specified TRB.
1504
1505 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1506 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1507
1508 @retval EFI_SUCCESS The env is ready for TRB execution.
1509 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1510 @retval Others Some erros happen.
1511
1512 **/
1513 EFI_STATUS
1514 SdMmcWaitTrbEnv (
1515 IN SD_MMC_HC_PRIVATE_DATA *Private,
1516 IN SD_MMC_HC_TRB *Trb
1517 )
1518 {
1519 EFI_STATUS Status;
1520 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1521 UINT64 Timeout;
1522 BOOLEAN InfiniteWait;
1523
1524 //
1525 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1526 //
1527 Packet = Trb->Packet;
1528 Timeout = Packet->Timeout;
1529 if (Timeout == 0) {
1530 InfiniteWait = TRUE;
1531 } else {
1532 InfiniteWait = FALSE;
1533 }
1534
1535 while (InfiniteWait || (Timeout > 0)) {
1536 //
1537 // Check Trb execution result by reading Normal Interrupt Status register.
1538 //
1539 Status = SdMmcCheckTrbEnv (Private, Trb);
1540 if (Status != EFI_NOT_READY) {
1541 return Status;
1542 }
1543 //
1544 // Stall for 1 microsecond.
1545 //
1546 gBS->Stall (1);
1547
1548 Timeout--;
1549 }
1550
1551 return EFI_TIMEOUT;
1552 }
1553
1554 /**
1555 Execute the specified TRB.
1556
1557 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1558 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1559
1560 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1561 @retval Others Some erros happen when sending this request to the host controller.
1562
1563 **/
1564 EFI_STATUS
1565 SdMmcExecTrb (
1566 IN SD_MMC_HC_PRIVATE_DATA *Private,
1567 IN SD_MMC_HC_TRB *Trb
1568 )
1569 {
1570 EFI_STATUS Status;
1571 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1572 EFI_PCI_IO_PROTOCOL *PciIo;
1573 UINT16 Cmd;
1574 UINT16 IntStatus;
1575 UINT32 Argument;
1576 UINT16 BlkCount;
1577 UINT16 BlkSize;
1578 UINT16 TransMode;
1579 UINT8 HostCtrl1;
1580 UINT32 SdmaAddr;
1581 UINT64 AdmaAddr;
1582
1583 Packet = Trb->Packet;
1584 PciIo = Trb->Private->PciIo;
1585 //
1586 // Clear all bits in Error Interrupt Status Register
1587 //
1588 IntStatus = 0xFFFF;
1589 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1590 if (EFI_ERROR (Status)) {
1591 return Status;
1592 }
1593 //
1594 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1595 //
1596 IntStatus = 0xFF3F;
1597 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1598 if (EFI_ERROR (Status)) {
1599 return Status;
1600 }
1601 //
1602 // Set Host Control 1 register DMA Select field
1603 //
1604 if (Trb->Mode == SdMmcAdmaMode) {
1605 HostCtrl1 = BIT4;
1606 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1607 if (EFI_ERROR (Status)) {
1608 return Status;
1609 }
1610 }
1611
1612 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1613
1614 if (Trb->Mode == SdMmcSdmaMode) {
1615 if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
1616 return EFI_INVALID_PARAMETER;
1617 }
1618
1619 SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
1620 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
1621 if (EFI_ERROR (Status)) {
1622 return Status;
1623 }
1624 } else if (Trb->Mode == SdMmcAdmaMode) {
1625 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1626 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1627 if (EFI_ERROR (Status)) {
1628 return Status;
1629 }
1630 }
1631
1632 BlkSize = Trb->BlockSize;
1633 if (Trb->Mode == SdMmcSdmaMode) {
1634 //
1635 // Set SDMA boundary to be 512K bytes.
1636 //
1637 BlkSize |= 0x7000;
1638 }
1639
1640 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1641 if (EFI_ERROR (Status)) {
1642 return Status;
1643 }
1644
1645 BlkCount = 0;
1646 if (Trb->Mode != SdMmcNoData) {
1647 //
1648 // Calcuate Block Count.
1649 //
1650 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
1651 }
1652 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
1653 if (EFI_ERROR (Status)) {
1654 return Status;
1655 }
1656
1657 Argument = Packet->SdMmcCmdBlk->CommandArgument;
1658 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1659 if (EFI_ERROR (Status)) {
1660 return Status;
1661 }
1662
1663 TransMode = 0;
1664 if (Trb->Mode != SdMmcNoData) {
1665 if (Trb->Mode != SdMmcPioMode) {
1666 TransMode |= BIT0;
1667 }
1668 if (Trb->Read) {
1669 TransMode |= BIT4;
1670 }
1671 if (BlkCount > 1) {
1672 TransMode |= BIT5 | BIT1;
1673 }
1674 //
1675 // Only SD memory card needs to use AUTO CMD12 feature.
1676 //
1677 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
1678 if (BlkCount > 1) {
1679 TransMode |= BIT2;
1680 }
1681 }
1682 }
1683
1684 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1685 if (EFI_ERROR (Status)) {
1686 return Status;
1687 }
1688
1689 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
1690 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
1691 Cmd |= BIT5;
1692 }
1693 //
1694 // Convert ResponseType to value
1695 //
1696 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1697 switch (Packet->SdMmcCmdBlk->ResponseType) {
1698 case SdMmcResponseTypeR1:
1699 case SdMmcResponseTypeR5:
1700 case SdMmcResponseTypeR6:
1701 case SdMmcResponseTypeR7:
1702 Cmd |= (BIT1 | BIT3 | BIT4);
1703 break;
1704 case SdMmcResponseTypeR2:
1705 Cmd |= (BIT0 | BIT3);
1706 break;
1707 case SdMmcResponseTypeR3:
1708 case SdMmcResponseTypeR4:
1709 Cmd |= BIT1;
1710 break;
1711 case SdMmcResponseTypeR1b:
1712 case SdMmcResponseTypeR5b:
1713 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
1714 break;
1715 default:
1716 ASSERT (FALSE);
1717 break;
1718 }
1719 }
1720 //
1721 // Execute cmd
1722 //
1723 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
1724 return Status;
1725 }
1726
1727 /**
1728 Check the TRB execution result.
1729
1730 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1731 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1732
1733 @retval EFI_SUCCESS The TRB is executed successfully.
1734 @retval EFI_NOT_READY The TRB is not completed for execution.
1735 @retval Others Some erros happen when executing this request.
1736
1737 **/
1738 EFI_STATUS
1739 SdMmcCheckTrbResult (
1740 IN SD_MMC_HC_PRIVATE_DATA *Private,
1741 IN SD_MMC_HC_TRB *Trb
1742 )
1743 {
1744 EFI_STATUS Status;
1745 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1746 UINT16 IntStatus;
1747 UINT32 Response[4];
1748 UINT32 SdmaAddr;
1749 UINT8 Index;
1750 UINT8 SwReset;
1751 UINT32 PioLength;
1752
1753 SwReset = 0;
1754 Packet = Trb->Packet;
1755 //
1756 // Check Trb execution result by reading Normal Interrupt Status register.
1757 //
1758 Status = SdMmcHcRwMmio (
1759 Private->PciIo,
1760 Trb->Slot,
1761 SD_MMC_HC_NOR_INT_STS,
1762 TRUE,
1763 sizeof (IntStatus),
1764 &IntStatus
1765 );
1766 if (EFI_ERROR (Status)) {
1767 goto Done;
1768 }
1769 //
1770 // Check Transfer Complete bit is set or not.
1771 //
1772 if ((IntStatus & BIT1) == BIT1) {
1773 if ((IntStatus & BIT15) == BIT15) {
1774 //
1775 // Read Error Interrupt Status register to check if the error is
1776 // Data Timeout Error.
1777 // If yes, treat it as success as Transfer Complete has higher
1778 // priority than Data Timeout Error.
1779 //
1780 Status = SdMmcHcRwMmio (
1781 Private->PciIo,
1782 Trb->Slot,
1783 SD_MMC_HC_ERR_INT_STS,
1784 TRUE,
1785 sizeof (IntStatus),
1786 &IntStatus
1787 );
1788 if (!EFI_ERROR (Status)) {
1789 if ((IntStatus & BIT4) == BIT4) {
1790 Status = EFI_SUCCESS;
1791 } else {
1792 Status = EFI_DEVICE_ERROR;
1793 }
1794 }
1795 }
1796
1797 goto Done;
1798 }
1799 //
1800 // Check if there is a error happened during cmd execution.
1801 // If yes, then do error recovery procedure to follow SD Host Controller
1802 // Simplified Spec 3.0 section 3.10.1.
1803 //
1804 if ((IntStatus & BIT15) == BIT15) {
1805 Status = SdMmcHcRwMmio (
1806 Private->PciIo,
1807 Trb->Slot,
1808 SD_MMC_HC_ERR_INT_STS,
1809 TRUE,
1810 sizeof (IntStatus),
1811 &IntStatus
1812 );
1813 if (EFI_ERROR (Status)) {
1814 goto Done;
1815 }
1816 if ((IntStatus & 0x0F) != 0) {
1817 SwReset |= BIT1;
1818 }
1819 if ((IntStatus & 0xF0) != 0) {
1820 SwReset |= BIT2;
1821 }
1822
1823 Status = SdMmcHcRwMmio (
1824 Private->PciIo,
1825 Trb->Slot,
1826 SD_MMC_HC_SW_RST,
1827 FALSE,
1828 sizeof (SwReset),
1829 &SwReset
1830 );
1831 if (EFI_ERROR (Status)) {
1832 goto Done;
1833 }
1834 Status = SdMmcHcWaitMmioSet (
1835 Private->PciIo,
1836 Trb->Slot,
1837 SD_MMC_HC_SW_RST,
1838 sizeof (SwReset),
1839 0xFF,
1840 0,
1841 SD_MMC_HC_GENERIC_TIMEOUT
1842 );
1843 if (EFI_ERROR (Status)) {
1844 goto Done;
1845 }
1846
1847 Status = EFI_DEVICE_ERROR;
1848 goto Done;
1849 }
1850 //
1851 // Check if DMA interrupt is signalled for the SDMA transfer.
1852 //
1853 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
1854 //
1855 // Clear DMA interrupt bit.
1856 //
1857 IntStatus = BIT3;
1858 Status = SdMmcHcRwMmio (
1859 Private->PciIo,
1860 Trb->Slot,
1861 SD_MMC_HC_NOR_INT_STS,
1862 FALSE,
1863 sizeof (IntStatus),
1864 &IntStatus
1865 );
1866 if (EFI_ERROR (Status)) {
1867 goto Done;
1868 }
1869 //
1870 // Update SDMA Address register.
1871 //
1872 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
1873 Status = SdMmcHcRwMmio (
1874 Private->PciIo,
1875 Trb->Slot,
1876 SD_MMC_HC_SDMA_ADDR,
1877 FALSE,
1878 sizeof (UINT32),
1879 &SdmaAddr
1880 );
1881 if (EFI_ERROR (Status)) {
1882 goto Done;
1883 }
1884 Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
1885 }
1886
1887 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
1888 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
1889 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
1890 if ((IntStatus & BIT0) == BIT0) {
1891 Status = EFI_SUCCESS;
1892 goto Done;
1893 }
1894 }
1895
1896 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1897 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1898 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1899 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1900 //
1901 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
1902 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
1903 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
1904 //
1905 if ((IntStatus & BIT5) == BIT5) {
1906 //
1907 // Clear Buffer Read Ready interrupt at first.
1908 //
1909 IntStatus = BIT5;
1910 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1911 //
1912 // Read data out from Buffer Port register
1913 //
1914 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
1915 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
1916 }
1917 Status = EFI_SUCCESS;
1918 goto Done;
1919 }
1920 }
1921
1922 Status = EFI_NOT_READY;
1923 Done:
1924 //
1925 // Get response data when the cmd is executed successfully.
1926 //
1927 if (!EFI_ERROR (Status)) {
1928 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1929 for (Index = 0; Index < 4; Index++) {
1930 Status = SdMmcHcRwMmio (
1931 Private->PciIo,
1932 Trb->Slot,
1933 SD_MMC_HC_RESPONSE + Index * 4,
1934 TRUE,
1935 sizeof (UINT32),
1936 &Response[Index]
1937 );
1938 if (EFI_ERROR (Status)) {
1939 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
1940 return Status;
1941 }
1942 }
1943 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
1944 }
1945 }
1946
1947 if (Status != EFI_NOT_READY) {
1948 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
1949 }
1950
1951 return Status;
1952 }
1953
1954 /**
1955 Wait for the TRB execution result.
1956
1957 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1958 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1959
1960 @retval EFI_SUCCESS The TRB is executed successfully.
1961 @retval Others Some erros happen when executing this request.
1962
1963 **/
1964 EFI_STATUS
1965 SdMmcWaitTrbResult (
1966 IN SD_MMC_HC_PRIVATE_DATA *Private,
1967 IN SD_MMC_HC_TRB *Trb
1968 )
1969 {
1970 EFI_STATUS Status;
1971 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1972 UINT64 Timeout;
1973 BOOLEAN InfiniteWait;
1974
1975 Packet = Trb->Packet;
1976 //
1977 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1978 //
1979 Timeout = Packet->Timeout;
1980 if (Timeout == 0) {
1981 InfiniteWait = TRUE;
1982 } else {
1983 InfiniteWait = FALSE;
1984 }
1985
1986 while (InfiniteWait || (Timeout > 0)) {
1987 //
1988 // Check Trb execution result by reading Normal Interrupt Status register.
1989 //
1990 Status = SdMmcCheckTrbResult (Private, Trb);
1991 if (Status != EFI_NOT_READY) {
1992 return Status;
1993 }
1994 //
1995 // Stall for 1 microsecond.
1996 //
1997 gBS->Stall (1);
1998
1999 Timeout--;
2000 }
2001
2002 return EFI_TIMEOUT;
2003 }
2004
EFI Development Kit II mirror for PVE