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MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
5 4.20.
6
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
8
9 Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
11 This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18
19 **/
20
21 #include "SdMmcPciHcDxe.h"
22
23 /**
24 Dump the content of SD/MMC host controller's Capability Register.
25
26 @param[in] Slot The slot number of the SD card to send the command to.
27 @param[in] Capability The buffer to store the capability data.
28
29 **/
30 VOID
31 DumpCapabilityReg (
32 IN UINT8 Slot,
33 IN SD_MMC_HC_SLOT_CAP *Capability
34 )
35 {
36 //
37 // Dump Capability Data
38 //
39 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
40 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
41 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
42 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
43 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
49 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
50 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
51 DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));
52 DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));
53 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
54 DEBUG ((DEBUG_INFO, " SlotType "));
55 if (Capability->SlotType == 0x00) {
56 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
57 } else if (Capability->SlotType == 0x01) {
58 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
59 } else if (Capability->SlotType == 0x02) {
60 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
61 } else {
62 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
63 }
64 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
66 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
67 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
68 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
69 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
70 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
71 if (Capability->TimerCount == 0) {
72 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
73 } else {
74 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
75 }
76 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
77 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
78 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
79 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
80 return;
81 }
82
83 /**
84 Read SlotInfo register from SD/MMC host controller pci config space.
85
86 @param[in] PciIo The PCI IO protocol instance.
87 @param[out] FirstBar The buffer to store the first BAR value.
88 @param[out] SlotNum The buffer to store the supported slot number.
89
90 @retval EFI_SUCCESS The operation succeeds.
91 @retval Others The operation fails.
92
93 **/
94 EFI_STATUS
95 EFIAPI
96 SdMmcHcGetSlotInfo (
97 IN EFI_PCI_IO_PROTOCOL *PciIo,
98 OUT UINT8 *FirstBar,
99 OUT UINT8 *SlotNum
100 )
101 {
102 EFI_STATUS Status;
103 SD_MMC_HC_SLOT_INFO SlotInfo;
104
105 Status = PciIo->Pci.Read (
106 PciIo,
107 EfiPciIoWidthUint8,
108 SD_MMC_HC_SLOT_OFFSET,
109 sizeof (SlotInfo),
110 &SlotInfo
111 );
112 if (EFI_ERROR (Status)) {
113 return Status;
114 }
115
116 *FirstBar = SlotInfo.FirstBar;
117 *SlotNum = SlotInfo.SlotNum + 1;
118 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
119 return EFI_SUCCESS;
120 }
121
122 /**
123 Read/Write specified SD/MMC host controller mmio register.
124
125 @param[in] PciIo The PCI IO protocol instance.
126 @param[in] BarIndex The BAR index of the standard PCI Configuration
127 header to use as the base address for the memory
128 operation to perform.
129 @param[in] Offset The offset within the selected BAR to start the
130 memory operation.
131 @param[in] Read A boolean to indicate it's read or write operation.
132 @param[in] Count The width of the mmio register in bytes.
133 Must be 1, 2 , 4 or 8 bytes.
134 @param[in, out] Data For read operations, the destination buffer to store
135 the results. For write operations, the source buffer
136 to write data from. The caller is responsible for
137 having ownership of the data buffer and ensuring its
138 size not less than Count bytes.
139
140 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
141 @retval EFI_SUCCESS The read/write operation succeeds.
142 @retval Others The read/write operation fails.
143
144 **/
145 EFI_STATUS
146 EFIAPI
147 SdMmcHcRwMmio (
148 IN EFI_PCI_IO_PROTOCOL *PciIo,
149 IN UINT8 BarIndex,
150 IN UINT32 Offset,
151 IN BOOLEAN Read,
152 IN UINT8 Count,
153 IN OUT VOID *Data
154 )
155 {
156 EFI_STATUS Status;
157 EFI_PCI_IO_PROTOCOL_WIDTH Width;
158
159 if ((PciIo == NULL) || (Data == NULL)) {
160 return EFI_INVALID_PARAMETER;
161 }
162
163 switch (Count) {
164 case 1:
165 Width = EfiPciIoWidthUint8;
166 break;
167 case 2:
168 Width = EfiPciIoWidthUint16;
169 Count = 1;
170 break;
171 case 4:
172 Width = EfiPciIoWidthUint32;
173 Count = 1;
174 break;
175 case 8:
176 Width = EfiPciIoWidthUint32;
177 Count = 2;
178 break;
179 default:
180 return EFI_INVALID_PARAMETER;
181 }
182
183 if (Read) {
184 Status = PciIo->Mem.Read (
185 PciIo,
186 Width,
187 BarIndex,
188 (UINT64) Offset,
189 Count,
190 Data
191 );
192 } else {
193 Status = PciIo->Mem.Write (
194 PciIo,
195 Width,
196 BarIndex,
197 (UINT64) Offset,
198 Count,
199 Data
200 );
201 }
202
203 return Status;
204 }
205
206 /**
207 Do OR operation with the value of the specified SD/MMC host controller mmio register.
208
209 @param[in] PciIo The PCI IO protocol instance.
210 @param[in] BarIndex The BAR index of the standard PCI Configuration
211 header to use as the base address for the memory
212 operation to perform.
213 @param[in] Offset The offset within the selected BAR to start the
214 memory operation.
215 @param[in] Count The width of the mmio register in bytes.
216 Must be 1, 2 , 4 or 8 bytes.
217 @param[in] OrData The pointer to the data used to do OR operation.
218 The caller is responsible for having ownership of
219 the data buffer and ensuring its size not less than
220 Count bytes.
221
222 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
223 @retval EFI_SUCCESS The OR operation succeeds.
224 @retval Others The OR operation fails.
225
226 **/
227 EFI_STATUS
228 EFIAPI
229 SdMmcHcOrMmio (
230 IN EFI_PCI_IO_PROTOCOL *PciIo,
231 IN UINT8 BarIndex,
232 IN UINT32 Offset,
233 IN UINT8 Count,
234 IN VOID *OrData
235 )
236 {
237 EFI_STATUS Status;
238 UINT64 Data;
239 UINT64 Or;
240
241 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
242 if (EFI_ERROR (Status)) {
243 return Status;
244 }
245
246 if (Count == 1) {
247 Or = *(UINT8*) OrData;
248 } else if (Count == 2) {
249 Or = *(UINT16*) OrData;
250 } else if (Count == 4) {
251 Or = *(UINT32*) OrData;
252 } else if (Count == 8) {
253 Or = *(UINT64*) OrData;
254 } else {
255 return EFI_INVALID_PARAMETER;
256 }
257
258 Data |= Or;
259 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
260
261 return Status;
262 }
263
264 /**
265 Do AND operation with the value of the specified SD/MMC host controller mmio register.
266
267 @param[in] PciIo The PCI IO protocol instance.
268 @param[in] BarIndex The BAR index of the standard PCI Configuration
269 header to use as the base address for the memory
270 operation to perform.
271 @param[in] Offset The offset within the selected BAR to start the
272 memory operation.
273 @param[in] Count The width of the mmio register in bytes.
274 Must be 1, 2 , 4 or 8 bytes.
275 @param[in] AndData The pointer to the data used to do AND operation.
276 The caller is responsible for having ownership of
277 the data buffer and ensuring its size not less than
278 Count bytes.
279
280 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
281 @retval EFI_SUCCESS The AND operation succeeds.
282 @retval Others The AND operation fails.
283
284 **/
285 EFI_STATUS
286 EFIAPI
287 SdMmcHcAndMmio (
288 IN EFI_PCI_IO_PROTOCOL *PciIo,
289 IN UINT8 BarIndex,
290 IN UINT32 Offset,
291 IN UINT8 Count,
292 IN VOID *AndData
293 )
294 {
295 EFI_STATUS Status;
296 UINT64 Data;
297 UINT64 And;
298
299 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
300 if (EFI_ERROR (Status)) {
301 return Status;
302 }
303
304 if (Count == 1) {
305 And = *(UINT8*) AndData;
306 } else if (Count == 2) {
307 And = *(UINT16*) AndData;
308 } else if (Count == 4) {
309 And = *(UINT32*) AndData;
310 } else if (Count == 8) {
311 And = *(UINT64*) AndData;
312 } else {
313 return EFI_INVALID_PARAMETER;
314 }
315
316 Data &= And;
317 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
318
319 return Status;
320 }
321
322 /**
323 Wait for the value of the specified MMIO register set to the test value.
324
325 @param[in] PciIo The PCI IO protocol instance.
326 @param[in] BarIndex The BAR index of the standard PCI Configuration
327 header to use as the base address for the memory
328 operation to perform.
329 @param[in] Offset The offset within the selected BAR to start the
330 memory operation.
331 @param[in] Count The width of the mmio register in bytes.
332 Must be 1, 2, 4 or 8 bytes.
333 @param[in] MaskValue The mask value of memory.
334 @param[in] TestValue The test value of memory.
335
336 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
337 @retval EFI_SUCCESS The MMIO register has expected value.
338 @retval Others The MMIO operation fails.
339
340 **/
341 EFI_STATUS
342 EFIAPI
343 SdMmcHcCheckMmioSet (
344 IN EFI_PCI_IO_PROTOCOL *PciIo,
345 IN UINT8 BarIndex,
346 IN UINT32 Offset,
347 IN UINT8 Count,
348 IN UINT64 MaskValue,
349 IN UINT64 TestValue
350 )
351 {
352 EFI_STATUS Status;
353 UINT64 Value;
354
355 //
356 // Access PCI MMIO space to see if the value is the tested one.
357 //
358 Value = 0;
359 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
360 if (EFI_ERROR (Status)) {
361 return Status;
362 }
363
364 Value &= MaskValue;
365
366 if (Value == TestValue) {
367 return EFI_SUCCESS;
368 }
369
370 return EFI_NOT_READY;
371 }
372
373 /**
374 Wait for the value of the specified MMIO register set to the test value.
375
376 @param[in] PciIo The PCI IO protocol instance.
377 @param[in] BarIndex The BAR index of the standard PCI Configuration
378 header to use as the base address for the memory
379 operation to perform.
380 @param[in] Offset The offset within the selected BAR to start the
381 memory operation.
382 @param[in] Count The width of the mmio register in bytes.
383 Must be 1, 2, 4 or 8 bytes.
384 @param[in] MaskValue The mask value of memory.
385 @param[in] TestValue The test value of memory.
386 @param[in] Timeout The time out value for wait memory set, uses 1
387 microsecond as a unit.
388
389 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
390 range.
391 @retval EFI_SUCCESS The MMIO register has expected value.
392 @retval Others The MMIO operation fails.
393
394 **/
395 EFI_STATUS
396 EFIAPI
397 SdMmcHcWaitMmioSet (
398 IN EFI_PCI_IO_PROTOCOL *PciIo,
399 IN UINT8 BarIndex,
400 IN UINT32 Offset,
401 IN UINT8 Count,
402 IN UINT64 MaskValue,
403 IN UINT64 TestValue,
404 IN UINT64 Timeout
405 )
406 {
407 EFI_STATUS Status;
408 BOOLEAN InfiniteWait;
409
410 if (Timeout == 0) {
411 InfiniteWait = TRUE;
412 } else {
413 InfiniteWait = FALSE;
414 }
415
416 while (InfiniteWait || (Timeout > 0)) {
417 Status = SdMmcHcCheckMmioSet (
418 PciIo,
419 BarIndex,
420 Offset,
421 Count,
422 MaskValue,
423 TestValue
424 );
425 if (Status != EFI_NOT_READY) {
426 return Status;
427 }
428
429 //
430 // Stall for 1 microsecond.
431 //
432 gBS->Stall (1);
433
434 Timeout--;
435 }
436
437 return EFI_TIMEOUT;
438 }
439
440 /**
441 Get the controller version information from the specified slot.
442
443 @param[in] PciIo The PCI IO protocol instance.
444 @param[in] Slot The slot number of the SD card to send the command to.
445 @param[out] Version The buffer to store the version information.
446
447 @retval EFI_SUCCESS The operation executes successfully.
448 @retval Others The operation fails.
449
450 **/
451 EFI_STATUS
452 SdMmcHcGetControllerVersion (
453 IN EFI_PCI_IO_PROTOCOL *PciIo,
454 IN UINT8 Slot,
455 OUT UINT16 *Version
456 )
457 {
458 EFI_STATUS Status;
459
460 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);
461 if (EFI_ERROR (Status)) {
462 return Status;
463 }
464
465 *Version &= 0xFF;
466
467 return EFI_SUCCESS;
468 }
469
470 /**
471 Software reset the specified SD/MMC host controller and enable all interrupts.
472
473 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
474 @param[in] Slot The slot number of the SD card to send the command to.
475
476 @retval EFI_SUCCESS The software reset executes successfully.
477 @retval Others The software reset fails.
478
479 **/
480 EFI_STATUS
481 SdMmcHcReset (
482 IN SD_MMC_HC_PRIVATE_DATA *Private,
483 IN UINT8 Slot
484 )
485 {
486 EFI_STATUS Status;
487 UINT8 SwReset;
488 EFI_PCI_IO_PROTOCOL *PciIo;
489
490 //
491 // Notify the SD/MMC override protocol that we are about to reset
492 // the SD/MMC host controller.
493 //
494 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
495 Status = mOverride->NotifyPhase (
496 Private->ControllerHandle,
497 Slot,
498 EdkiiSdMmcResetPre,
499 NULL);
500 if (EFI_ERROR (Status)) {
501 DEBUG ((DEBUG_WARN,
502 "%a: SD/MMC pre reset notifier callback failed - %r\n",
503 __FUNCTION__, Status));
504 return Status;
505 }
506 }
507
508 PciIo = Private->PciIo;
509 SwReset = BIT0;
510 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
511
512 if (EFI_ERROR (Status)) {
513 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
514 return Status;
515 }
516
517 Status = SdMmcHcWaitMmioSet (
518 PciIo,
519 Slot,
520 SD_MMC_HC_SW_RST,
521 sizeof (SwReset),
522 BIT0,
523 0x00,
524 SD_MMC_HC_GENERIC_TIMEOUT
525 );
526 if (EFI_ERROR (Status)) {
527 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
528 return Status;
529 }
530
531 //
532 // Enable all interrupt after reset all.
533 //
534 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
535 if (EFI_ERROR (Status)) {
536 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
537 Status));
538 return Status;
539 }
540
541 //
542 // Notify the SD/MMC override protocol that we have just reset
543 // the SD/MMC host controller.
544 //
545 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
546 Status = mOverride->NotifyPhase (
547 Private->ControllerHandle,
548 Slot,
549 EdkiiSdMmcResetPost,
550 NULL);
551 if (EFI_ERROR (Status)) {
552 DEBUG ((DEBUG_WARN,
553 "%a: SD/MMC post reset notifier callback failed - %r\n",
554 __FUNCTION__, Status));
555 }
556 }
557
558 return Status;
559 }
560
561 /**
562 Set all interrupt status bits in Normal and Error Interrupt Status Enable
563 register.
564
565 @param[in] PciIo The PCI IO protocol instance.
566 @param[in] Slot The slot number of the SD card to send the command to.
567
568 @retval EFI_SUCCESS The operation executes successfully.
569 @retval Others The operation fails.
570
571 **/
572 EFI_STATUS
573 SdMmcHcEnableInterrupt (
574 IN EFI_PCI_IO_PROTOCOL *PciIo,
575 IN UINT8 Slot
576 )
577 {
578 EFI_STATUS Status;
579 UINT16 IntStatus;
580
581 //
582 // Enable all bits in Error Interrupt Status Enable Register
583 //
584 IntStatus = 0xFFFF;
585 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
586 if (EFI_ERROR (Status)) {
587 return Status;
588 }
589 //
590 // Enable all bits in Normal Interrupt Status Enable Register
591 //
592 IntStatus = 0xFFFF;
593 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
594
595 return Status;
596 }
597
598 /**
599 Get the capability data from the specified slot.
600
601 @param[in] PciIo The PCI IO protocol instance.
602 @param[in] Slot The slot number of the SD card to send the command to.
603 @param[out] Capability The buffer to store the capability data.
604
605 @retval EFI_SUCCESS The operation executes successfully.
606 @retval Others The operation fails.
607
608 **/
609 EFI_STATUS
610 SdMmcHcGetCapability (
611 IN EFI_PCI_IO_PROTOCOL *PciIo,
612 IN UINT8 Slot,
613 OUT SD_MMC_HC_SLOT_CAP *Capability
614 )
615 {
616 EFI_STATUS Status;
617 UINT64 Cap;
618
619 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
620 if (EFI_ERROR (Status)) {
621 return Status;
622 }
623
624 CopyMem (Capability, &Cap, sizeof (Cap));
625
626 return EFI_SUCCESS;
627 }
628
629 /**
630 Get the maximum current capability data from the specified slot.
631
632 @param[in] PciIo The PCI IO protocol instance.
633 @param[in] Slot The slot number of the SD card to send the command to.
634 @param[out] MaxCurrent The buffer to store the maximum current capability data.
635
636 @retval EFI_SUCCESS The operation executes successfully.
637 @retval Others The operation fails.
638
639 **/
640 EFI_STATUS
641 SdMmcHcGetMaxCurrent (
642 IN EFI_PCI_IO_PROTOCOL *PciIo,
643 IN UINT8 Slot,
644 OUT UINT64 *MaxCurrent
645 )
646 {
647 EFI_STATUS Status;
648
649 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
650
651 return Status;
652 }
653
654 /**
655 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
656 slot.
657
658 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
659
660 @param[in] PciIo The PCI IO protocol instance.
661 @param[in] Slot The slot number of the SD card to send the command to.
662 @param[out] MediaPresent The pointer to the media present boolean value.
663
664 @retval EFI_SUCCESS There is no media change happened.
665 @retval EFI_MEDIA_CHANGED There is media change happened.
666 @retval Others The detection fails.
667
668 **/
669 EFI_STATUS
670 SdMmcHcCardDetect (
671 IN EFI_PCI_IO_PROTOCOL *PciIo,
672 IN UINT8 Slot,
673 OUT BOOLEAN *MediaPresent
674 )
675 {
676 EFI_STATUS Status;
677 UINT16 Data;
678 UINT32 PresentState;
679
680 //
681 // Check Present State Register to see if there is a card presented.
682 //
683 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
684 if (EFI_ERROR (Status)) {
685 return Status;
686 }
687
688 if ((PresentState & BIT16) != 0) {
689 *MediaPresent = TRUE;
690 } else {
691 *MediaPresent = FALSE;
692 }
693
694 //
695 // Check Normal Interrupt Status Register
696 //
697 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
698 if (EFI_ERROR (Status)) {
699 return Status;
700 }
701
702 if ((Data & (BIT6 | BIT7)) != 0) {
703 //
704 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
705 //
706 Data &= BIT6 | BIT7;
707 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
708 if (EFI_ERROR (Status)) {
709 return Status;
710 }
711
712 return EFI_MEDIA_CHANGED;
713 }
714
715 return EFI_SUCCESS;
716 }
717
718 /**
719 Stop SD/MMC card clock.
720
721 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
722
723 @param[in] PciIo The PCI IO protocol instance.
724 @param[in] Slot The slot number of the SD card to send the command to.
725
726 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
727 @retval Others Fail to stop SD/MMC clock.
728
729 **/
730 EFI_STATUS
731 SdMmcHcStopClock (
732 IN EFI_PCI_IO_PROTOCOL *PciIo,
733 IN UINT8 Slot
734 )
735 {
736 EFI_STATUS Status;
737 UINT32 PresentState;
738 UINT16 ClockCtrl;
739
740 //
741 // Ensure no SD transactions are occurring on the SD Bus by
742 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
743 // in the Present State register to be 0.
744 //
745 Status = SdMmcHcWaitMmioSet (
746 PciIo,
747 Slot,
748 SD_MMC_HC_PRESENT_STATE,
749 sizeof (PresentState),
750 BIT0 | BIT1,
751 0,
752 SD_MMC_HC_GENERIC_TIMEOUT
753 );
754 if (EFI_ERROR (Status)) {
755 return Status;
756 }
757
758 //
759 // Set SD Clock Enable in the Clock Control register to 0
760 //
761 ClockCtrl = (UINT16)~BIT2;
762 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
763
764 return Status;
765 }
766
767 /**
768 SD/MMC card clock supply.
769
770 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
771
772 @param[in] PciIo The PCI IO protocol instance.
773 @param[in] Slot The slot number of the SD card to send the command to.
774 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
775 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
776 @param[in] ControllerVer The version of host controller.
777
778 @retval EFI_SUCCESS The clock is supplied successfully.
779 @retval Others The clock isn't supplied successfully.
780
781 **/
782 EFI_STATUS
783 SdMmcHcClockSupply (
784 IN EFI_PCI_IO_PROTOCOL *PciIo,
785 IN UINT8 Slot,
786 IN UINT64 ClockFreq,
787 IN UINT32 BaseClkFreq,
788 IN UINT16 ControllerVer
789 )
790 {
791 EFI_STATUS Status;
792 UINT32 SettingFreq;
793 UINT32 Divisor;
794 UINT32 Remainder;
795 UINT16 ClockCtrl;
796
797 //
798 // Calculate a divisor for SD clock frequency
799 //
800 ASSERT (BaseClkFreq != 0);
801
802 if (ClockFreq == 0) {
803 return EFI_INVALID_PARAMETER;
804 }
805
806 if (ClockFreq > (BaseClkFreq * 1000)) {
807 ClockFreq = BaseClkFreq * 1000;
808 }
809
810 //
811 // Calculate the divisor of base frequency.
812 //
813 Divisor = 0;
814 SettingFreq = BaseClkFreq * 1000;
815 while (ClockFreq < SettingFreq) {
816 Divisor++;
817
818 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
819 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
820 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
821 break;
822 }
823 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
824 SettingFreq ++;
825 }
826 }
827
828 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
829
830 //
831 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
832 //
833 if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&
834 (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {
835 ASSERT (Divisor <= 0x3FF);
836 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
837 } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||
838 (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {
839 //
840 // Only the most significant bit can be used as divisor.
841 //
842 if (((Divisor - 1) & Divisor) != 0) {
843 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
844 }
845 ASSERT (Divisor <= 0x80);
846 ClockCtrl = (Divisor & 0xFF) << 8;
847 } else {
848 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
849 return EFI_UNSUPPORTED;
850 }
851
852 //
853 // Stop bus clock at first
854 //
855 Status = SdMmcHcStopClock (PciIo, Slot);
856 if (EFI_ERROR (Status)) {
857 return Status;
858 }
859
860 //
861 // Supply clock frequency with specified divisor
862 //
863 ClockCtrl |= BIT0;
864 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
865 if (EFI_ERROR (Status)) {
866 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
867 return Status;
868 }
869
870 //
871 // Wait Internal Clock Stable in the Clock Control register to be 1
872 //
873 Status = SdMmcHcWaitMmioSet (
874 PciIo,
875 Slot,
876 SD_MMC_HC_CLOCK_CTRL,
877 sizeof (ClockCtrl),
878 BIT1,
879 BIT1,
880 SD_MMC_HC_GENERIC_TIMEOUT
881 );
882 if (EFI_ERROR (Status)) {
883 return Status;
884 }
885
886 //
887 // Set SD Clock Enable in the Clock Control register to 1
888 //
889 ClockCtrl = BIT2;
890 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
891
892 return Status;
893 }
894
895 /**
896 SD/MMC bus power control.
897
898 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
899
900 @param[in] PciIo The PCI IO protocol instance.
901 @param[in] Slot The slot number of the SD card to send the command to.
902 @param[in] PowerCtrl The value setting to the power control register.
903
904 @retval TRUE There is a SD/MMC card attached.
905 @retval FALSE There is no a SD/MMC card attached.
906
907 **/
908 EFI_STATUS
909 SdMmcHcPowerControl (
910 IN EFI_PCI_IO_PROTOCOL *PciIo,
911 IN UINT8 Slot,
912 IN UINT8 PowerCtrl
913 )
914 {
915 EFI_STATUS Status;
916
917 //
918 // Clr SD Bus Power
919 //
920 PowerCtrl &= (UINT8)~BIT0;
921 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
922 if (EFI_ERROR (Status)) {
923 return Status;
924 }
925
926 //
927 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
928 //
929 PowerCtrl |= BIT0;
930 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
931
932 return Status;
933 }
934
935 /**
936 Set the SD/MMC bus width.
937
938 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
939
940 @param[in] PciIo The PCI IO protocol instance.
941 @param[in] Slot The slot number of the SD card to send the command to.
942 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
943
944 @retval EFI_SUCCESS The bus width is set successfully.
945 @retval Others The bus width isn't set successfully.
946
947 **/
948 EFI_STATUS
949 SdMmcHcSetBusWidth (
950 IN EFI_PCI_IO_PROTOCOL *PciIo,
951 IN UINT8 Slot,
952 IN UINT16 BusWidth
953 )
954 {
955 EFI_STATUS Status;
956 UINT8 HostCtrl1;
957
958 if (BusWidth == 1) {
959 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
960 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
961 } else if (BusWidth == 4) {
962 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
963 if (EFI_ERROR (Status)) {
964 return Status;
965 }
966 HostCtrl1 |= BIT1;
967 HostCtrl1 &= (UINT8)~BIT5;
968 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
969 } else if (BusWidth == 8) {
970 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
971 if (EFI_ERROR (Status)) {
972 return Status;
973 }
974 HostCtrl1 &= (UINT8)~BIT1;
975 HostCtrl1 |= BIT5;
976 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
977 } else {
978 ASSERT (FALSE);
979 return EFI_INVALID_PARAMETER;
980 }
981
982 return Status;
983 }
984
985 /**
986 Configure V4 controller enhancements at initialization.
987
988 @param[in] PciIo The PCI IO protocol instance.
989 @param[in] Slot The slot number of the SD card to send the command to.
990 @param[in] Capability The capability of the slot.
991 @param[in] ControllerVer The version of host controller.
992
993 @retval EFI_SUCCESS The clock is supplied successfully.
994
995 **/
996 EFI_STATUS
997 SdMmcHcInitV4Enhancements (
998 IN EFI_PCI_IO_PROTOCOL *PciIo,
999 IN UINT8 Slot,
1000 IN SD_MMC_HC_SLOT_CAP Capability,
1001 IN UINT16 ControllerVer
1002 )
1003 {
1004 EFI_STATUS Status;
1005 UINT16 HostCtrl2;
1006
1007 //
1008 // Check if controller version V4 or higher
1009 //
1010 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
1011 HostCtrl2 = SD_MMC_HC_V4_EN;
1012 //
1013 // Check if V4 64bit support is available
1014 //
1015 if (Capability.SysBus64V4 != 0) {
1016 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1017 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1018 }
1019 //
1020 // Check if controller version V4.10 or higher
1021 //
1022 if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {
1023 HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;
1024 DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));
1025 }
1026 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1027 if (EFI_ERROR (Status)) {
1028 return Status;
1029 }
1030 }
1031
1032 return EFI_SUCCESS;
1033 }
1034
1035 /**
1036 Supply SD/MMC card with lowest clock frequency at initialization.
1037
1038 @param[in] PciIo The PCI IO protocol instance.
1039 @param[in] Slot The slot number of the SD card to send the command to.
1040 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
1041 @param[in] ControllerVer The version of host controller.
1042
1043 @retval EFI_SUCCESS The clock is supplied successfully.
1044 @retval Others The clock isn't supplied successfully.
1045
1046 **/
1047 EFI_STATUS
1048 SdMmcHcInitClockFreq (
1049 IN EFI_PCI_IO_PROTOCOL *PciIo,
1050 IN UINT8 Slot,
1051 IN UINT32 BaseClkFreq,
1052 IN UINT16 ControllerVer
1053 )
1054 {
1055 EFI_STATUS Status;
1056 UINT32 InitFreq;
1057
1058 //
1059 // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
1060 // the Capability Register 1 can be zero, which means a need for obtaining
1061 // the clock frequency via another method. Fail in case it is not updated
1062 // by SW at this point.
1063 //
1064 if (BaseClkFreq == 0) {
1065 //
1066 // Don't support get Base Clock Frequency information via another method
1067 //
1068 return EFI_UNSUPPORTED;
1069 }
1070 //
1071 // Supply 400KHz clock frequency at initialization phase.
1072 //
1073 InitFreq = 400;
1074 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq, ControllerVer);
1075 return Status;
1076 }
1077
1078 /**
1079 Supply SD/MMC card with maximum voltage at initialization.
1080
1081 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1082
1083 @param[in] PciIo The PCI IO protocol instance.
1084 @param[in] Slot The slot number of the SD card to send the command to.
1085 @param[in] Capability The capability of the slot.
1086
1087 @retval EFI_SUCCESS The voltage is supplied successfully.
1088 @retval Others The voltage isn't supplied successfully.
1089
1090 **/
1091 EFI_STATUS
1092 SdMmcHcInitPowerVoltage (
1093 IN EFI_PCI_IO_PROTOCOL *PciIo,
1094 IN UINT8 Slot,
1095 IN SD_MMC_HC_SLOT_CAP Capability
1096 )
1097 {
1098 EFI_STATUS Status;
1099 UINT8 MaxVoltage;
1100 UINT8 HostCtrl2;
1101
1102 //
1103 // Calculate supported maximum voltage according to SD Bus Voltage Select
1104 //
1105 if (Capability.Voltage33 != 0) {
1106 //
1107 // Support 3.3V
1108 //
1109 MaxVoltage = 0x0E;
1110 } else if (Capability.Voltage30 != 0) {
1111 //
1112 // Support 3.0V
1113 //
1114 MaxVoltage = 0x0C;
1115 } else if (Capability.Voltage18 != 0) {
1116 //
1117 // Support 1.8V
1118 //
1119 MaxVoltage = 0x0A;
1120 HostCtrl2 = BIT3;
1121 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1122 gBS->Stall (5000);
1123 if (EFI_ERROR (Status)) {
1124 return Status;
1125 }
1126 } else {
1127 ASSERT (FALSE);
1128 return EFI_DEVICE_ERROR;
1129 }
1130
1131 //
1132 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1133 //
1134 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1135
1136 return Status;
1137 }
1138
1139 /**
1140 Initialize the Timeout Control register with most conservative value at initialization.
1141
1142 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1143
1144 @param[in] PciIo The PCI IO protocol instance.
1145 @param[in] Slot The slot number of the SD card to send the command to.
1146
1147 @retval EFI_SUCCESS The timeout control register is configured successfully.
1148 @retval Others The timeout control register isn't configured successfully.
1149
1150 **/
1151 EFI_STATUS
1152 SdMmcHcInitTimeoutCtrl (
1153 IN EFI_PCI_IO_PROTOCOL *PciIo,
1154 IN UINT8 Slot
1155 )
1156 {
1157 EFI_STATUS Status;
1158 UINT8 Timeout;
1159
1160 Timeout = 0x0E;
1161 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1162
1163 return Status;
1164 }
1165
1166 /**
1167 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1168 at initialization.
1169
1170 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1171 @param[in] Slot The slot number of the SD card to send the command to.
1172
1173 @retval EFI_SUCCESS The host controller is initialized successfully.
1174 @retval Others The host controller isn't initialized successfully.
1175
1176 **/
1177 EFI_STATUS
1178 SdMmcHcInitHost (
1179 IN SD_MMC_HC_PRIVATE_DATA *Private,
1180 IN UINT8 Slot
1181 )
1182 {
1183 EFI_STATUS Status;
1184 EFI_PCI_IO_PROTOCOL *PciIo;
1185 SD_MMC_HC_SLOT_CAP Capability;
1186
1187 //
1188 // Notify the SD/MMC override protocol that we are about to initialize
1189 // the SD/MMC host controller.
1190 //
1191 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1192 Status = mOverride->NotifyPhase (
1193 Private->ControllerHandle,
1194 Slot,
1195 EdkiiSdMmcInitHostPre,
1196 NULL);
1197 if (EFI_ERROR (Status)) {
1198 DEBUG ((DEBUG_WARN,
1199 "%a: SD/MMC pre init notifier callback failed - %r\n",
1200 __FUNCTION__, Status));
1201 return Status;
1202 }
1203 }
1204
1205 PciIo = Private->PciIo;
1206 Capability = Private->Capability[Slot];
1207
1208 Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);
1209 if (EFI_ERROR (Status)) {
1210 return Status;
1211 }
1212
1213 Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
1214 if (EFI_ERROR (Status)) {
1215 return Status;
1216 }
1217
1218 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1219 if (EFI_ERROR (Status)) {
1220 return Status;
1221 }
1222
1223 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1224 if (EFI_ERROR (Status)) {
1225 return Status;
1226 }
1227
1228 //
1229 // Notify the SD/MMC override protocol that we are have just initialized
1230 // the SD/MMC host controller.
1231 //
1232 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1233 Status = mOverride->NotifyPhase (
1234 Private->ControllerHandle,
1235 Slot,
1236 EdkiiSdMmcInitHostPost,
1237 NULL);
1238 if (EFI_ERROR (Status)) {
1239 DEBUG ((DEBUG_WARN,
1240 "%a: SD/MMC post init notifier callback failed - %r\n",
1241 __FUNCTION__, Status));
1242 }
1243 }
1244 return Status;
1245 }
1246
1247 /**
1248 Set SD Host Controler control 2 registry according to selected speed.
1249
1250 @param[in] ControllerHandle The handle of the controller.
1251 @param[in] PciIo The PCI IO protocol instance.
1252 @param[in] Slot The slot number of the SD card to send the command to.
1253 @param[in] Timing The timing to select.
1254
1255 @retval EFI_SUCCESS The timing is set successfully.
1256 @retval Others The timing isn't set successfully.
1257 **/
1258 EFI_STATUS
1259 SdMmcHcUhsSignaling (
1260 IN EFI_HANDLE ControllerHandle,
1261 IN EFI_PCI_IO_PROTOCOL *PciIo,
1262 IN UINT8 Slot,
1263 IN SD_MMC_BUS_MODE Timing
1264 )
1265 {
1266 EFI_STATUS Status;
1267 UINT8 HostCtrl2;
1268
1269 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
1270 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1271 if (EFI_ERROR (Status)) {
1272 return Status;
1273 }
1274
1275 switch (Timing) {
1276 case SdMmcUhsSdr12:
1277 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1278 break;
1279 case SdMmcUhsSdr25:
1280 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1281 break;
1282 case SdMmcUhsSdr50:
1283 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1284 break;
1285 case SdMmcUhsSdr104:
1286 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1287 break;
1288 case SdMmcUhsDdr50:
1289 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1290 break;
1291 case SdMmcMmcLegacy:
1292 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1293 break;
1294 case SdMmcMmcHsSdr:
1295 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1296 break;
1297 case SdMmcMmcHsDdr:
1298 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1299 break;
1300 case SdMmcMmcHs200:
1301 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1302 break;
1303 case SdMmcMmcHs400:
1304 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1305 break;
1306 default:
1307 HostCtrl2 = 0;
1308 break;
1309 }
1310 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1311 if (EFI_ERROR (Status)) {
1312 return Status;
1313 }
1314
1315 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1316 Status = mOverride->NotifyPhase (
1317 ControllerHandle,
1318 Slot,
1319 EdkiiSdMmcUhsSignaling,
1320 &Timing
1321 );
1322 if (EFI_ERROR (Status)) {
1323 DEBUG ((
1324 DEBUG_ERROR,
1325 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1326 __FUNCTION__,
1327 Status
1328 ));
1329 return Status;
1330 }
1331 }
1332
1333 return EFI_SUCCESS;
1334 }
1335
1336 /**
1337 Turn on/off LED.
1338
1339 @param[in] PciIo The PCI IO protocol instance.
1340 @param[in] Slot The slot number of the SD card to send the command to.
1341 @param[in] On The boolean to turn on/off LED.
1342
1343 @retval EFI_SUCCESS The LED is turned on/off successfully.
1344 @retval Others The LED isn't turned on/off successfully.
1345
1346 **/
1347 EFI_STATUS
1348 SdMmcHcLedOnOff (
1349 IN EFI_PCI_IO_PROTOCOL *PciIo,
1350 IN UINT8 Slot,
1351 IN BOOLEAN On
1352 )
1353 {
1354 EFI_STATUS Status;
1355 UINT8 HostCtrl1;
1356
1357 if (On) {
1358 HostCtrl1 = BIT0;
1359 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1360 } else {
1361 HostCtrl1 = (UINT8)~BIT0;
1362 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1363 }
1364
1365 return Status;
1366 }
1367
1368 /**
1369 Build ADMA descriptor table for transfer.
1370
1371 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1372
1373 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1374 @param[in] ControllerVer The version of host controller.
1375
1376 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1377 @retval Others The ADMA descriptor table isn't created successfully.
1378
1379 **/
1380 EFI_STATUS
1381 BuildAdmaDescTable (
1382 IN SD_MMC_HC_TRB *Trb,
1383 IN UINT16 ControllerVer
1384 )
1385 {
1386 EFI_PHYSICAL_ADDRESS Data;
1387 UINT64 DataLen;
1388 UINT64 Entries;
1389 UINT32 Index;
1390 UINT64 Remaining;
1391 UINT64 Address;
1392 UINTN TableSize;
1393 EFI_PCI_IO_PROTOCOL *PciIo;
1394 EFI_STATUS Status;
1395 UINTN Bytes;
1396 BOOLEAN AddressingMode64;
1397 BOOLEAN DataLength26;
1398 UINT32 AdmaMaxDataPerLine;
1399 UINT32 DescSize;
1400 VOID *AdmaDesc;
1401
1402 AddressingMode64 = FALSE;
1403 DataLength26 = FALSE;
1404 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;
1405 DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);
1406 AdmaDesc = NULL;
1407
1408 Data = Trb->DataPhy;
1409 DataLen = Trb->DataLen;
1410 PciIo = Trb->Private->PciIo;
1411
1412 //
1413 // Detect whether 64bit addressing is supported.
1414 //
1415 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
1416 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1417 SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);
1418 if (!EFI_ERROR (Status)) {
1419 AddressingMode64 = TRUE;
1420 DescSize = sizeof (SD_MMC_HC_ADMA_64_DESC_LINE);
1421 }
1422 }
1423 //
1424 // Check for valid ranges in 32bit ADMA Descriptor Table
1425 //
1426 if (!AddressingMode64 &&
1427 ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {
1428 return EFI_INVALID_PARAMETER;
1429 }
1430 //
1431 // Check address field alignment
1432 //
1433 if (AddressingMode64) {
1434 //
1435 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1436 //
1437 if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {
1438 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));
1439 }
1440 } else {
1441 //
1442 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1443 //
1444 if ((Data & (BIT0 | BIT1)) != 0) {
1445 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1446 }
1447 }
1448 //
1449 // Detect whether 26bit data length is supported.
1450 //
1451 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1452 SD_MMC_HC_26_DATA_LEN_ADMA_EN, SD_MMC_HC_26_DATA_LEN_ADMA_EN);
1453 if (!EFI_ERROR (Status)) {
1454 DataLength26 = TRUE;
1455 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;
1456 }
1457
1458 Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
1459 TableSize = (UINTN)MultU64x32 (Entries, DescSize);
1460 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1461 Status = PciIo->AllocateBuffer (
1462 PciIo,
1463 AllocateAnyPages,
1464 EfiBootServicesData,
1465 EFI_SIZE_TO_PAGES (TableSize),
1466 (VOID **)&AdmaDesc,
1467 0
1468 );
1469 if (EFI_ERROR (Status)) {
1470 return EFI_OUT_OF_RESOURCES;
1471 }
1472 ZeroMem (AdmaDesc, TableSize);
1473 Bytes = TableSize;
1474 Status = PciIo->Map (
1475 PciIo,
1476 EfiPciIoOperationBusMasterCommonBuffer,
1477 AdmaDesc,
1478 &Bytes,
1479 &Trb->AdmaDescPhy,
1480 &Trb->AdmaMap
1481 );
1482
1483 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1484 //
1485 // Map error or unable to map the whole RFis buffer into a contiguous region.
1486 //
1487 PciIo->FreeBuffer (
1488 PciIo,
1489 EFI_SIZE_TO_PAGES (TableSize),
1490 AdmaDesc
1491 );
1492 return EFI_OUT_OF_RESOURCES;
1493 }
1494
1495 if ((!AddressingMode64) &&
1496 (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1497 //
1498 // The ADMA doesn't support 64bit addressing.
1499 //
1500 PciIo->Unmap (
1501 PciIo,
1502 Trb->AdmaMap
1503 );
1504 PciIo->FreeBuffer (
1505 PciIo,
1506 EFI_SIZE_TO_PAGES (TableSize),
1507 AdmaDesc
1508 );
1509 return EFI_DEVICE_ERROR;
1510 }
1511
1512 Remaining = DataLen;
1513 Address = Data;
1514 if (!AddressingMode64) {
1515 Trb->Adma32Desc = AdmaDesc;
1516 Trb->Adma64Desc = NULL;
1517 } else {
1518 Trb->Adma64Desc = AdmaDesc;
1519 Trb->Adma32Desc = NULL;
1520 }
1521 for (Index = 0; Index < Entries; Index++) {
1522 if (!AddressingMode64) {
1523 if (Remaining <= AdmaMaxDataPerLine) {
1524 Trb->Adma32Desc[Index].Valid = 1;
1525 Trb->Adma32Desc[Index].Act = 2;
1526 if (DataLength26) {
1527 Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1528 }
1529 Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1530 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1531 break;
1532 } else {
1533 Trb->Adma32Desc[Index].Valid = 1;
1534 Trb->Adma32Desc[Index].Act = 2;
1535 if (DataLength26) {
1536 Trb->Adma32Desc[Index].UpperLength = 0;
1537 }
1538 Trb->Adma32Desc[Index].LowerLength = 0;
1539 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1540 }
1541 } else {
1542 if (Remaining <= AdmaMaxDataPerLine) {
1543 Trb->Adma64Desc[Index].Valid = 1;
1544 Trb->Adma64Desc[Index].Act = 2;
1545 if (DataLength26) {
1546 Trb->Adma64Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1547 }
1548 Trb->Adma64Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1549 Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;
1550 Trb->Adma64Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1551 break;
1552 } else {
1553 Trb->Adma64Desc[Index].Valid = 1;
1554 Trb->Adma64Desc[Index].Act = 2;
1555 if (DataLength26) {
1556 Trb->Adma64Desc[Index].UpperLength = 0;
1557 }
1558 Trb->Adma64Desc[Index].LowerLength = 0;
1559 Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;
1560 Trb->Adma64Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1561 }
1562 }
1563
1564 Remaining -= AdmaMaxDataPerLine;
1565 Address += AdmaMaxDataPerLine;
1566 }
1567
1568 //
1569 // Set the last descriptor line as end of descriptor table
1570 //
1571 AddressingMode64 ? (Trb->Adma64Desc[Index].End = 1) : (Trb->Adma32Desc[Index].End = 1);
1572 return EFI_SUCCESS;
1573 }
1574
1575 /**
1576 Create a new TRB for the SD/MMC cmd request.
1577
1578 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1579 @param[in] Slot The slot number of the SD card to send the command to.
1580 @param[in] Packet A pointer to the SD command data structure.
1581 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1582 not NULL, then nonblocking I/O is performed, and Event
1583 will be signaled when the Packet completes.
1584
1585 @return Created Trb or NULL.
1586
1587 **/
1588 SD_MMC_HC_TRB *
1589 SdMmcCreateTrb (
1590 IN SD_MMC_HC_PRIVATE_DATA *Private,
1591 IN UINT8 Slot,
1592 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1593 IN EFI_EVENT Event
1594 )
1595 {
1596 SD_MMC_HC_TRB *Trb;
1597 EFI_STATUS Status;
1598 EFI_TPL OldTpl;
1599 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1600 EFI_PCI_IO_PROTOCOL *PciIo;
1601 UINTN MapLength;
1602
1603 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1604 if (Trb == NULL) {
1605 return NULL;
1606 }
1607
1608 Trb->Signature = SD_MMC_HC_TRB_SIG;
1609 Trb->Slot = Slot;
1610 Trb->BlockSize = 0x200;
1611 Trb->Packet = Packet;
1612 Trb->Event = Event;
1613 Trb->Started = FALSE;
1614 Trb->Timeout = Packet->Timeout;
1615 Trb->Private = Private;
1616
1617 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1618 Trb->Data = Packet->InDataBuffer;
1619 Trb->DataLen = Packet->InTransferLength;
1620 Trb->Read = TRUE;
1621 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1622 Trb->Data = Packet->OutDataBuffer;
1623 Trb->DataLen = Packet->OutTransferLength;
1624 Trb->Read = FALSE;
1625 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1626 Trb->Data = NULL;
1627 Trb->DataLen = 0;
1628 } else {
1629 goto Error;
1630 }
1631
1632 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1633 Trb->BlockSize = (UINT16)Trb->DataLen;
1634 }
1635
1636 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1637 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1638 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1639 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1640 Trb->Mode = SdMmcPioMode;
1641 } else {
1642 if (Trb->Read) {
1643 Flag = EfiPciIoOperationBusMasterWrite;
1644 } else {
1645 Flag = EfiPciIoOperationBusMasterRead;
1646 }
1647
1648 PciIo = Private->PciIo;
1649 if (Trb->DataLen != 0) {
1650 MapLength = Trb->DataLen;
1651 Status = PciIo->Map (
1652 PciIo,
1653 Flag,
1654 Trb->Data,
1655 &MapLength,
1656 &Trb->DataPhy,
1657 &Trb->DataMap
1658 );
1659 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1660 Status = EFI_BAD_BUFFER_SIZE;
1661 goto Error;
1662 }
1663 }
1664
1665 if (Trb->DataLen == 0) {
1666 Trb->Mode = SdMmcNoData;
1667 } else if (Private->Capability[Slot].Adma2 != 0) {
1668 Trb->Mode = SdMmcAdmaMode;
1669 Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
1670 if (EFI_ERROR (Status)) {
1671 PciIo->Unmap (PciIo, Trb->DataMap);
1672 goto Error;
1673 }
1674 } else if (Private->Capability[Slot].Sdma != 0) {
1675 Trb->Mode = SdMmcSdmaMode;
1676 } else {
1677 Trb->Mode = SdMmcPioMode;
1678 }
1679 }
1680
1681 if (Event != NULL) {
1682 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1683 InsertTailList (&Private->Queue, &Trb->TrbList);
1684 gBS->RestoreTPL (OldTpl);
1685 }
1686
1687 return Trb;
1688
1689 Error:
1690 SdMmcFreeTrb (Trb);
1691 return NULL;
1692 }
1693
1694 /**
1695 Free the resource used by the TRB.
1696
1697 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1698
1699 **/
1700 VOID
1701 SdMmcFreeTrb (
1702 IN SD_MMC_HC_TRB *Trb
1703 )
1704 {
1705 EFI_PCI_IO_PROTOCOL *PciIo;
1706
1707 PciIo = Trb->Private->PciIo;
1708
1709 if (Trb->AdmaMap != NULL) {
1710 PciIo->Unmap (
1711 PciIo,
1712 Trb->AdmaMap
1713 );
1714 }
1715 if (Trb->Adma32Desc != NULL) {
1716 PciIo->FreeBuffer (
1717 PciIo,
1718 Trb->AdmaPages,
1719 Trb->Adma32Desc
1720 );
1721 }
1722 if (Trb->Adma64Desc != NULL) {
1723 PciIo->FreeBuffer (
1724 PciIo,
1725 Trb->AdmaPages,
1726 Trb->Adma64Desc
1727 );
1728 }
1729 if (Trb->DataMap != NULL) {
1730 PciIo->Unmap (
1731 PciIo,
1732 Trb->DataMap
1733 );
1734 }
1735 FreePool (Trb);
1736 return;
1737 }
1738
1739 /**
1740 Check if the env is ready for execute specified TRB.
1741
1742 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1743 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1744
1745 @retval EFI_SUCCESS The env is ready for TRB execution.
1746 @retval EFI_NOT_READY The env is not ready for TRB execution.
1747 @retval Others Some erros happen.
1748
1749 **/
1750 EFI_STATUS
1751 SdMmcCheckTrbEnv (
1752 IN SD_MMC_HC_PRIVATE_DATA *Private,
1753 IN SD_MMC_HC_TRB *Trb
1754 )
1755 {
1756 EFI_STATUS Status;
1757 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1758 EFI_PCI_IO_PROTOCOL *PciIo;
1759 UINT32 PresentState;
1760
1761 Packet = Trb->Packet;
1762
1763 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1764 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1765 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1766 //
1767 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1768 // the Present State register to be 0
1769 //
1770 PresentState = BIT0 | BIT1;
1771 } else {
1772 //
1773 // Wait Command Inhibit (CMD) in the Present State register
1774 // to be 0
1775 //
1776 PresentState = BIT0;
1777 }
1778
1779 PciIo = Private->PciIo;
1780 Status = SdMmcHcCheckMmioSet (
1781 PciIo,
1782 Trb->Slot,
1783 SD_MMC_HC_PRESENT_STATE,
1784 sizeof (PresentState),
1785 PresentState,
1786 0
1787 );
1788
1789 return Status;
1790 }
1791
1792 /**
1793 Wait for the env to be ready for execute specified TRB.
1794
1795 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1796 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1797
1798 @retval EFI_SUCCESS The env is ready for TRB execution.
1799 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1800 @retval Others Some erros happen.
1801
1802 **/
1803 EFI_STATUS
1804 SdMmcWaitTrbEnv (
1805 IN SD_MMC_HC_PRIVATE_DATA *Private,
1806 IN SD_MMC_HC_TRB *Trb
1807 )
1808 {
1809 EFI_STATUS Status;
1810 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1811 UINT64 Timeout;
1812 BOOLEAN InfiniteWait;
1813
1814 //
1815 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1816 //
1817 Packet = Trb->Packet;
1818 Timeout = Packet->Timeout;
1819 if (Timeout == 0) {
1820 InfiniteWait = TRUE;
1821 } else {
1822 InfiniteWait = FALSE;
1823 }
1824
1825 while (InfiniteWait || (Timeout > 0)) {
1826 //
1827 // Check Trb execution result by reading Normal Interrupt Status register.
1828 //
1829 Status = SdMmcCheckTrbEnv (Private, Trb);
1830 if (Status != EFI_NOT_READY) {
1831 return Status;
1832 }
1833 //
1834 // Stall for 1 microsecond.
1835 //
1836 gBS->Stall (1);
1837
1838 Timeout--;
1839 }
1840
1841 return EFI_TIMEOUT;
1842 }
1843
1844 /**
1845 Execute the specified TRB.
1846
1847 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1848 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1849
1850 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1851 @retval Others Some erros happen when sending this request to the host controller.
1852
1853 **/
1854 EFI_STATUS
1855 SdMmcExecTrb (
1856 IN SD_MMC_HC_PRIVATE_DATA *Private,
1857 IN SD_MMC_HC_TRB *Trb
1858 )
1859 {
1860 EFI_STATUS Status;
1861 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1862 EFI_PCI_IO_PROTOCOL *PciIo;
1863 UINT16 Cmd;
1864 UINT16 IntStatus;
1865 UINT32 Argument;
1866 UINT32 BlkCount;
1867 UINT16 BlkSize;
1868 UINT16 TransMode;
1869 UINT8 HostCtrl1;
1870 UINT64 SdmaAddr;
1871 UINT64 AdmaAddr;
1872 BOOLEAN AddressingMode64;
1873
1874 AddressingMode64 = FALSE;
1875
1876 Packet = Trb->Packet;
1877 PciIo = Trb->Private->PciIo;
1878 //
1879 // Clear all bits in Error Interrupt Status Register
1880 //
1881 IntStatus = 0xFFFF;
1882 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1883 if (EFI_ERROR (Status)) {
1884 return Status;
1885 }
1886 //
1887 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1888 //
1889 IntStatus = 0xFF3F;
1890 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1891 if (EFI_ERROR (Status)) {
1892 return Status;
1893 }
1894 //
1895 // Set Host Control 1 register DMA Select field
1896 //
1897 if (Trb->Mode == SdMmcAdmaMode) {
1898 HostCtrl1 = BIT4;
1899 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1900 if (EFI_ERROR (Status)) {
1901 return Status;
1902 }
1903 }
1904
1905 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1906
1907 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1908 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1909 SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);
1910 if (!EFI_ERROR (Status)) {
1911 AddressingMode64 = TRUE;
1912 }
1913 }
1914
1915 if (Trb->Mode == SdMmcSdmaMode) {
1916 if ((!AddressingMode64) &&
1917 ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {
1918 return EFI_INVALID_PARAMETER;
1919 }
1920
1921 SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;
1922
1923 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1924 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);
1925 } else {
1926 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);
1927 }
1928
1929 if (EFI_ERROR (Status)) {
1930 return Status;
1931 }
1932 } else if (Trb->Mode == SdMmcAdmaMode) {
1933 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1934 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1935 if (EFI_ERROR (Status)) {
1936 return Status;
1937 }
1938 }
1939
1940 BlkSize = Trb->BlockSize;
1941 if (Trb->Mode == SdMmcSdmaMode) {
1942 //
1943 // Set SDMA boundary to be 512K bytes.
1944 //
1945 BlkSize |= 0x7000;
1946 }
1947
1948 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1949 if (EFI_ERROR (Status)) {
1950 return Status;
1951 }
1952
1953 BlkCount = 0;
1954 if (Trb->Mode != SdMmcNoData) {
1955 //
1956 // Calcuate Block Count.
1957 //
1958 BlkCount = (Trb->DataLen / Trb->BlockSize);
1959 }
1960 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {
1961 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);
1962 } else {
1963 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);
1964 }
1965 if (EFI_ERROR (Status)) {
1966 return Status;
1967 }
1968
1969 Argument = Packet->SdMmcCmdBlk->CommandArgument;
1970 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1971 if (EFI_ERROR (Status)) {
1972 return Status;
1973 }
1974
1975 TransMode = 0;
1976 if (Trb->Mode != SdMmcNoData) {
1977 if (Trb->Mode != SdMmcPioMode) {
1978 TransMode |= BIT0;
1979 }
1980 if (Trb->Read) {
1981 TransMode |= BIT4;
1982 }
1983 if (BlkCount > 1) {
1984 TransMode |= BIT5 | BIT1;
1985 }
1986 //
1987 // Only SD memory card needs to use AUTO CMD12 feature.
1988 //
1989 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
1990 if (BlkCount > 1) {
1991 TransMode |= BIT2;
1992 }
1993 }
1994 }
1995
1996 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1997 if (EFI_ERROR (Status)) {
1998 return Status;
1999 }
2000
2001 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
2002 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
2003 Cmd |= BIT5;
2004 }
2005 //
2006 // Convert ResponseType to value
2007 //
2008 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2009 switch (Packet->SdMmcCmdBlk->ResponseType) {
2010 case SdMmcResponseTypeR1:
2011 case SdMmcResponseTypeR5:
2012 case SdMmcResponseTypeR6:
2013 case SdMmcResponseTypeR7:
2014 Cmd |= (BIT1 | BIT3 | BIT4);
2015 break;
2016 case SdMmcResponseTypeR2:
2017 Cmd |= (BIT0 | BIT3);
2018 break;
2019 case SdMmcResponseTypeR3:
2020 case SdMmcResponseTypeR4:
2021 Cmd |= BIT1;
2022 break;
2023 case SdMmcResponseTypeR1b:
2024 case SdMmcResponseTypeR5b:
2025 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
2026 break;
2027 default:
2028 ASSERT (FALSE);
2029 break;
2030 }
2031 }
2032 //
2033 // Execute cmd
2034 //
2035 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
2036 return Status;
2037 }
2038
2039 /**
2040 Check the TRB execution result.
2041
2042 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2043 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2044
2045 @retval EFI_SUCCESS The TRB is executed successfully.
2046 @retval EFI_NOT_READY The TRB is not completed for execution.
2047 @retval Others Some erros happen when executing this request.
2048
2049 **/
2050 EFI_STATUS
2051 SdMmcCheckTrbResult (
2052 IN SD_MMC_HC_PRIVATE_DATA *Private,
2053 IN SD_MMC_HC_TRB *Trb
2054 )
2055 {
2056 EFI_STATUS Status;
2057 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2058 UINT16 IntStatus;
2059 UINT32 Response[4];
2060 UINT64 SdmaAddr;
2061 UINT8 Index;
2062 UINT8 SwReset;
2063 UINT32 PioLength;
2064
2065 SwReset = 0;
2066 Packet = Trb->Packet;
2067 //
2068 // Check Trb execution result by reading Normal Interrupt Status register.
2069 //
2070 Status = SdMmcHcRwMmio (
2071 Private->PciIo,
2072 Trb->Slot,
2073 SD_MMC_HC_NOR_INT_STS,
2074 TRUE,
2075 sizeof (IntStatus),
2076 &IntStatus
2077 );
2078 if (EFI_ERROR (Status)) {
2079 goto Done;
2080 }
2081 //
2082 // Check Transfer Complete bit is set or not.
2083 //
2084 if ((IntStatus & BIT1) == BIT1) {
2085 if ((IntStatus & BIT15) == BIT15) {
2086 //
2087 // Read Error Interrupt Status register to check if the error is
2088 // Data Timeout Error.
2089 // If yes, treat it as success as Transfer Complete has higher
2090 // priority than Data Timeout Error.
2091 //
2092 Status = SdMmcHcRwMmio (
2093 Private->PciIo,
2094 Trb->Slot,
2095 SD_MMC_HC_ERR_INT_STS,
2096 TRUE,
2097 sizeof (IntStatus),
2098 &IntStatus
2099 );
2100 if (!EFI_ERROR (Status)) {
2101 if ((IntStatus & BIT4) == BIT4) {
2102 Status = EFI_SUCCESS;
2103 } else {
2104 Status = EFI_DEVICE_ERROR;
2105 }
2106 }
2107 }
2108
2109 goto Done;
2110 }
2111 //
2112 // Check if there is a error happened during cmd execution.
2113 // If yes, then do error recovery procedure to follow SD Host Controller
2114 // Simplified Spec 3.0 section 3.10.1.
2115 //
2116 if ((IntStatus & BIT15) == BIT15) {
2117 Status = SdMmcHcRwMmio (
2118 Private->PciIo,
2119 Trb->Slot,
2120 SD_MMC_HC_ERR_INT_STS,
2121 TRUE,
2122 sizeof (IntStatus),
2123 &IntStatus
2124 );
2125 if (EFI_ERROR (Status)) {
2126 goto Done;
2127 }
2128 if ((IntStatus & 0x0F) != 0) {
2129 SwReset |= BIT1;
2130 }
2131 if ((IntStatus & 0xF0) != 0) {
2132 SwReset |= BIT2;
2133 }
2134
2135 Status = SdMmcHcRwMmio (
2136 Private->PciIo,
2137 Trb->Slot,
2138 SD_MMC_HC_SW_RST,
2139 FALSE,
2140 sizeof (SwReset),
2141 &SwReset
2142 );
2143 if (EFI_ERROR (Status)) {
2144 goto Done;
2145 }
2146 Status = SdMmcHcWaitMmioSet (
2147 Private->PciIo,
2148 Trb->Slot,
2149 SD_MMC_HC_SW_RST,
2150 sizeof (SwReset),
2151 0xFF,
2152 0,
2153 SD_MMC_HC_GENERIC_TIMEOUT
2154 );
2155 if (EFI_ERROR (Status)) {
2156 goto Done;
2157 }
2158
2159 Status = EFI_DEVICE_ERROR;
2160 goto Done;
2161 }
2162 //
2163 // Check if DMA interrupt is signalled for the SDMA transfer.
2164 //
2165 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
2166 //
2167 // Clear DMA interrupt bit.
2168 //
2169 IntStatus = BIT3;
2170 Status = SdMmcHcRwMmio (
2171 Private->PciIo,
2172 Trb->Slot,
2173 SD_MMC_HC_NOR_INT_STS,
2174 FALSE,
2175 sizeof (IntStatus),
2176 &IntStatus
2177 );
2178 if (EFI_ERROR (Status)) {
2179 goto Done;
2180 }
2181 //
2182 // Update SDMA Address register.
2183 //
2184 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
2185
2186 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2187 Status = SdMmcHcRwMmio (
2188 Private->PciIo,
2189 Trb->Slot,
2190 SD_MMC_HC_ADMA_SYS_ADDR,
2191 FALSE,
2192 sizeof (UINT64),
2193 &SdmaAddr
2194 );
2195 } else {
2196 Status = SdMmcHcRwMmio (
2197 Private->PciIo,
2198 Trb->Slot,
2199 SD_MMC_HC_SDMA_ADDR,
2200 FALSE,
2201 sizeof (UINT32),
2202 &SdmaAddr
2203 );
2204 }
2205
2206 if (EFI_ERROR (Status)) {
2207 goto Done;
2208 }
2209 Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
2210 }
2211
2212 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
2213 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
2214 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
2215 if ((IntStatus & BIT0) == BIT0) {
2216 Status = EFI_SUCCESS;
2217 goto Done;
2218 }
2219 }
2220
2221 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
2222 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
2223 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
2224 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
2225 //
2226 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2227 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2228 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2229 //
2230 if ((IntStatus & BIT5) == BIT5) {
2231 //
2232 // Clear Buffer Read Ready interrupt at first.
2233 //
2234 IntStatus = BIT5;
2235 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2236 //
2237 // Read data out from Buffer Port register
2238 //
2239 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
2240 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
2241 }
2242 Status = EFI_SUCCESS;
2243 goto Done;
2244 }
2245 }
2246
2247 Status = EFI_NOT_READY;
2248 Done:
2249 //
2250 // Get response data when the cmd is executed successfully.
2251 //
2252 if (!EFI_ERROR (Status)) {
2253 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2254 for (Index = 0; Index < 4; Index++) {
2255 Status = SdMmcHcRwMmio (
2256 Private->PciIo,
2257 Trb->Slot,
2258 SD_MMC_HC_RESPONSE + Index * 4,
2259 TRUE,
2260 sizeof (UINT32),
2261 &Response[Index]
2262 );
2263 if (EFI_ERROR (Status)) {
2264 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2265 return Status;
2266 }
2267 }
2268 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2269 }
2270 }
2271
2272 if (Status != EFI_NOT_READY) {
2273 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2274 }
2275
2276 return Status;
2277 }
2278
2279 /**
2280 Wait for the TRB execution result.
2281
2282 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2283 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2284
2285 @retval EFI_SUCCESS The TRB is executed successfully.
2286 @retval Others Some erros happen when executing this request.
2287
2288 **/
2289 EFI_STATUS
2290 SdMmcWaitTrbResult (
2291 IN SD_MMC_HC_PRIVATE_DATA *Private,
2292 IN SD_MMC_HC_TRB *Trb
2293 )
2294 {
2295 EFI_STATUS Status;
2296 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2297 UINT64 Timeout;
2298 BOOLEAN InfiniteWait;
2299
2300 Packet = Trb->Packet;
2301 //
2302 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2303 //
2304 Timeout = Packet->Timeout;
2305 if (Timeout == 0) {
2306 InfiniteWait = TRUE;
2307 } else {
2308 InfiniteWait = FALSE;
2309 }
2310
2311 while (InfiniteWait || (Timeout > 0)) {
2312 //
2313 // Check Trb execution result by reading Normal Interrupt Status register.
2314 //
2315 Status = SdMmcCheckTrbResult (Private, Trb);
2316 if (Status != EFI_NOT_READY) {
2317 return Status;
2318 }
2319 //
2320 // Stall for 1 microsecond.
2321 //
2322 gBS->Stall (1);
2323
2324 Timeout--;
2325 }
2326
2327 return EFI_TIMEOUT;
2328 }
2329
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