MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h

   1 /** @file
   2
   3   Provides some data structure definitions used by the SD/MMC host controller driver.
   4
   5 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _SD_MMC_PCI_HCI_H_
  17 #define _SD_MMC_PCI_HCI_H_
  18
  19 //
  20 // SD Host Controller SlotInfo Register Offset
  21 //
  22 #define SD_MMC_HC_SLOT_OFFSET         0x40
  23
  24 #define SD_MMC_HC_MAX_SLOT            6
  25
  26 //
  27 // SD Host Controller MMIO Register Offset
  28 //
  29 #define SD_MMC_HC_SDMA_ADDR           0x00
  30 #define SD_MMC_HC_ARG2                0x00
  31 #define SD_MMC_HC_BLK_SIZE            0x04
  32 #define SD_MMC_HC_BLK_COUNT           0x06
  33 #define SD_MMC_HC_ARG1                0x08
  34 #define SD_MMC_HC_TRANS_MOD           0x0C
  35 #define SD_MMC_HC_COMMAND             0x0E
  36 #define SD_MMC_HC_RESPONSE            0x10
  37 #define SD_MMC_HC_BUF_DAT_PORT        0x20
  38 #define SD_MMC_HC_PRESENT_STATE       0x24
  39 #define SD_MMC_HC_HOST_CTRL1          0x28
  40 #define SD_MMC_HC_POWER_CTRL          0x29
  41 #define SD_MMC_HC_BLK_GAP_CTRL        0x2A
  42 #define SD_MMC_HC_WAKEUP_CTRL         0x2B
  43 #define SD_MMC_HC_CLOCK_CTRL          0x2C
  44 #define SD_MMC_HC_TIMEOUT_CTRL        0x2E
  45 #define SD_MMC_HC_SW_RST              0x2F
  46 #define SD_MMC_HC_NOR_INT_STS         0x30
  47 #define SD_MMC_HC_ERR_INT_STS         0x32
  48 #define SD_MMC_HC_NOR_INT_STS_EN      0x34
  49 #define SD_MMC_HC_ERR_INT_STS_EN      0x36
  50 #define SD_MMC_HC_NOR_INT_SIG_EN      0x38
  51 #define SD_MMC_HC_ERR_INT_SIG_EN      0x3A
  52 #define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C
  53 #define SD_MMC_HC_HOST_CTRL2          0x3E
  54 #define SD_MMC_HC_CAP                 0x40
  55 #define SD_MMC_HC_MAX_CURRENT_CAP     0x48
  56 #define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50
  57 #define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52
  58 #define SD_MMC_HC_ADMA_ERR_STS        0x54
  59 #define SD_MMC_HC_ADMA_SYS_ADDR       0x58
  60 #define SD_MMC_HC_PRESET_VAL          0x60
  61 #define SD_MMC_HC_SHARED_BUS_CTRL     0xE0
  62 #define SD_MMC_HC_SLOT_INT_STS        0xFC
  63 #define SD_MMC_HC_CTRL_VER            0xFE
  64
  65 //
  66 // The transfer modes supported by SD Host Controller
  67 // Simplified Spec 3.0 Table 1-2
  68 //
  69 typedef enum {
  70   SdMmcNoData,
  71   SdMmcPioMode,
  72   SdMmcSdmaMode,
  73   SdMmcAdmaMode
  74 } SD_MMC_HC_TRANSFER_MODE;
  75
  76 //
  77 // The maximum data length of each descriptor line
  78 //
  79 #define ADMA_MAX_DATA_PER_LINE     0x10000
  80
  81 typedef struct {
  82   UINT32 Valid:1;
  83   UINT32 End:1;
  84   UINT32 Int:1;
  85   UINT32 Reserved:1;
  86   UINT32 Act:2;
  87   UINT32 Reserved1:10;
  88   UINT32 Length:16;
  89   UINT32 Address;
  90 } SD_MMC_HC_ADMA_DESC_LINE;
  91
  92 #define SD_MMC_SDMA_BOUNDARY          512 * 1024
  93 #define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))
  94
  95 typedef struct {
  96   UINT8    FirstBar:3;        // bit 0:2
  97   UINT8    Reserved:1;        // bit 3
  98   UINT8    SlotNum:3;         // bit 4:6
  99   UINT8    Reserved1:1;       // bit 7
 100 } SD_MMC_HC_SLOT_INFO;
 101
 102 typedef struct {
 103   UINT32   TimeoutFreq:6;     // bit 0:5
 104   UINT32   Reserved:1;        // bit 6
 105   UINT32   TimeoutUnit:1;     // bit 7
 106   UINT32   BaseClkFreq:8;     // bit 8:15
 107   UINT32   MaxBlkLen:2;       // bit 16:17
 108   UINT32   BusWidth8:1;       // bit 18
 109   UINT32   Adma2:1;           // bit 19
 110   UINT32   Reserved2:1;       // bit 20
 111   UINT32   HighSpeed:1;       // bit 21
 112   UINT32   Sdma:1;            // bit 22
 113   UINT32   SuspRes:1;         // bit 23
 114   UINT32   Voltage33:1;       // bit 24
 115   UINT32   Voltage30:1;       // bit 25
 116   UINT32   Voltage18:1;       // bit 26
 117   UINT32   Reserved3:1;       // bit 27
 118   UINT32   SysBus64:1;        // bit 28
 119   UINT32   AsyncInt:1;        // bit 29
 120   UINT32   SlotType:2;        // bit 30:31
 121   UINT32   Sdr50:1;           // bit 32
 122   UINT32   Sdr104:1;          // bit 33
 123   UINT32   Ddr50:1;           // bit 34
 124   UINT32   Reserved4:1;       // bit 35
 125   UINT32   DriverTypeA:1;     // bit 36
 126   UINT32   DriverTypeC:1;     // bit 37
 127   UINT32   DriverTypeD:1;     // bit 38
 128   UINT32   DriverType4:1;     // bit 39
 129   UINT32   TimerCount:4;      // bit 40:43
 130   UINT32   Reserved5:1;       // bit 44
 131   UINT32   TuningSDR50:1;     // bit 45
 132   UINT32   RetuningMod:2;     // bit 46:47
 133   UINT32   ClkMultiplier:8;   // bit 48:55
 134   UINT32   Reserved6:7;       // bit 56:62
 135   UINT32   Hs400:1;           // bit 63
 136 } SD_MMC_HC_SLOT_CAP;
 137
 138 //
 139 // SD Host controller version
 140 //
 141 #define SD_MMC_HC_CTRL_VER_100      0x00
 142 #define SD_MMC_HC_CTRL_VER_200      0x01
 143 #define SD_MMC_HC_CTRL_VER_300      0x02
 144 #define SD_MMC_HC_CTRL_VER_400      0x03
 145 #define SD_MMC_HC_CTRL_VER_410      0x04
 146 #define SD_MMC_HC_CTRL_VER_420      0x05
 147
 148 /**
 149   Dump the content of SD/MMC host controller's Capability Register.
 150
 151   @param[in]  Slot            The slot number of the SD card to send the command to.
 152   @param[in]  Capability      The buffer to store the capability data.
 153
 154 **/
 155 VOID
 156 DumpCapabilityReg (
 157   IN UINT8                Slot,
 158   IN SD_MMC_HC_SLOT_CAP   *Capability
 159   );
 160
 161 /**
 162   Read SlotInfo register from SD/MMC host controller pci config space.
 163
 164   @param[in]  PciIo        The PCI IO protocol instance.
 165   @param[out] FirstBar     The buffer to store the first BAR value.
 166   @param[out] SlotNum      The buffer to store the supported slot number.
 167
 168   @retval EFI_SUCCESS      The operation succeeds.
 169   @retval Others           The operation fails.
 170
 171 **/
 172 EFI_STATUS
 173 EFIAPI
 174 SdMmcHcGetSlotInfo (
 175   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 176      OUT UINT8                 *FirstBar,
 177      OUT UINT8                 *SlotNum
 178   );
 179
 180 /**
 181   Read/Write specified SD/MMC host controller mmio register.
 182
 183   @param[in]      PciIo        The PCI IO protocol instance.
 184   @param[in]      BarIndex     The BAR index of the standard PCI Configuration
 185                                header to use as the base address for the memory
 186                                operation to perform.
 187   @param[in]      Offset       The offset within the selected BAR to start the
 188                                memory operation.
 189   @param[in]      Read         A boolean to indicate it's read or write operation.
 190   @param[in]      Count        The width of the mmio register in bytes.
 191                                Must be 1, 2 , 4 or 8 bytes.
 192   @param[in, out] Data         For read operations, the destination buffer to store
 193                                the results. For write operations, the source buffer
 194                                to write data from. The caller is responsible for
 195                                having ownership of the data buffer and ensuring its
 196                                size not less than Count bytes.
 197
 198   @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
 199   @retval EFI_SUCCESS           The read/write operation succeeds.
 200   @retval Others                The read/write operation fails.
 201
 202 **/
 203 EFI_STATUS
 204 EFIAPI
 205 SdMmcHcRwMmio (
 206   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 207   IN     UINT8                 BarIndex,
 208   IN     UINT32                Offset,
 209   IN     BOOLEAN               Read,
 210   IN     UINT8                 Count,
 211   IN OUT VOID                  *Data
 212   );
 213
 214 /**
 215   Do OR operation with the value of the specified SD/MMC host controller mmio register.
 216
 217   @param[in] PciIo             The PCI IO protocol instance.
 218   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 219                                header to use as the base address for the memory
 220                                operation to perform.
 221   @param[in] Offset            The offset within the selected BAR to start the
 222                                memory operation.
 223   @param[in] Count             The width of the mmio register in bytes.
 224                                Must be 1, 2 , 4 or 8 bytes.
 225   @param[in] OrData            The pointer to the data used to do OR operation.
 226                                The caller is responsible for having ownership of
 227                                the data buffer and ensuring its size not less than
 228                                Count bytes.
 229
 230   @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
 231   @retval EFI_SUCCESS           The OR operation succeeds.
 232   @retval Others                The OR operation fails.
 233
 234 **/
 235 EFI_STATUS
 236 EFIAPI
 237 SdMmcHcOrMmio (
 238   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 239   IN  UINT8                    BarIndex,
 240   IN  UINT32                   Offset,
 241   IN  UINT8                    Count,
 242   IN  VOID                     *OrData
 243   );
 244
 245 /**
 246   Do AND operation with the value of the specified SD/MMC host controller mmio register.
 247
 248   @param[in] PciIo             The PCI IO protocol instance.
 249   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 250                                header to use as the base address for the memory
 251                                operation to perform.
 252   @param[in] Offset            The offset within the selected BAR to start the
 253                                memory operation.
 254   @param[in] Count             The width of the mmio register in bytes.
 255                                Must be 1, 2 , 4 or 8 bytes.
 256   @param[in] AndData           The pointer to the data used to do AND operation.
 257                                The caller is responsible for having ownership of
 258                                the data buffer and ensuring its size not less than
 259                                Count bytes.
 260
 261   @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
 262   @retval EFI_SUCCESS           The AND operation succeeds.
 263   @retval Others                The AND operation fails.
 264
 265 **/
 266 EFI_STATUS
 267 EFIAPI
 268 SdMmcHcAndMmio (
 269   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 270   IN  UINT8                    BarIndex,
 271   IN  UINT32                   Offset,
 272   IN  UINT8                    Count,
 273   IN  VOID                     *AndData
 274   );
 275
 276 /**
 277   Wait for the value of the specified MMIO register set to the test value.
 278
 279   @param[in]  PciIo         The PCI IO protocol instance.
 280   @param[in]  BarIndex      The BAR index of the standard PCI Configuration
 281                             header to use as the base address for the memory
 282                             operation to perform.
 283   @param[in]  Offset        The offset within the selected BAR to start the
 284                             memory operation.
 285   @param[in]  Count         The width of the mmio register in bytes.
 286                             Must be 1, 2, 4 or 8 bytes.
 287   @param[in]  MaskValue     The mask value of memory.
 288   @param[in]  TestValue     The test value of memory.
 289   @param[in]  Timeout       The time out value for wait memory set, uses 1
 290                             microsecond as a unit.
 291
 292   @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
 293                             range.
 294   @retval EFI_SUCCESS       The MMIO register has expected value.
 295   @retval Others            The MMIO operation fails.
 296
 297 **/
 298 EFI_STATUS
 299 EFIAPI
 300 SdMmcHcWaitMmioSet (
 301   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 302   IN  UINT8                     BarIndex,
 303   IN  UINT32                    Offset,
 304   IN  UINT8                     Count,
 305   IN  UINT64                    MaskValue,
 306   IN  UINT64                    TestValue,
 307   IN  UINT64                    Timeout
 308   );
 309
 310 /**
 311   Set all interrupt status bits in Normal and Error Interrupt Status Enable
 312   register.
 313
 314   @param[in] PciIo          The PCI IO protocol instance.
 315   @param[in] Slot           The slot number of the SD card to send the command to.
 316
 317   @retval EFI_SUCCESS       The operation executes successfully.
 318   @retval Others            The operation fails.
 319
 320 **/
 321 EFI_STATUS
 322 SdMmcHcEnableInterrupt (
 323   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 324   IN UINT8                  Slot
 325   );
 326
 327 /**
 328   Get the capability data from the specified slot.
 329
 330   @param[in]  PciIo           The PCI IO protocol instance.
 331   @param[in]  Slot            The slot number of the SD card to send the command to.
 332   @param[out] Capability      The buffer to store the capability data.
 333
 334   @retval EFI_SUCCESS         The operation executes successfully.
 335   @retval Others              The operation fails.
 336
 337 **/
 338 EFI_STATUS
 339 SdMmcHcGetCapability (
 340   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 341   IN     UINT8                Slot,
 342      OUT SD_MMC_HC_SLOT_CAP   *Capability
 343   );
 344
 345 /**
 346   Get the maximum current capability data from the specified slot.
 347
 348   @param[in]  PciIo           The PCI IO protocol instance.
 349   @param[in]  Slot            The slot number of the SD card to send the command to.
 350   @param[out] MaxCurrent      The buffer to store the maximum current capability data.
 351
 352   @retval EFI_SUCCESS         The operation executes successfully.
 353   @retval Others              The operation fails.
 354
 355 **/
 356 EFI_STATUS
 357 SdMmcHcGetMaxCurrent (
 358   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 359   IN     UINT8                Slot,
 360      OUT UINT64               *MaxCurrent
 361   );
 362
 363 /**
 364   Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
 365   slot.
 366
 367   Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
 368
 369   @param[in]  PciIo         The PCI IO protocol instance.
 370   @param[in]  Slot          The slot number of the SD card to send the command to.
 371   @param[out] MediaPresent  The pointer to the media present boolean value.
 372
 373   @retval EFI_SUCCESS       There is no media change happened.
 374   @retval EFI_MEDIA_CHANGED There is media change happened.
 375   @retval Others            The detection fails.
 376
 377 **/
 378 EFI_STATUS
 379 SdMmcHcCardDetect (
 380   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 381   IN UINT8                  Slot,
 382      OUT BOOLEAN            *MediaPresent
 383   );
 384
 385 /**
 386   Stop SD/MMC card clock.
 387
 388   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
 389
 390   @param[in] PciIo          The PCI IO protocol instance.
 391   @param[in] Slot           The slot number of the SD card to send the command to.
 392
 393   @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
 394   @retval Others            Fail to stop SD/MMC clock.
 395
 396 **/
 397 EFI_STATUS
 398 SdMmcHcStopClock (
 399   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 400   IN UINT8                  Slot
 401   );
 402
 403 /**
 404   SD/MMC card clock supply.
 405
 406   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
 407
 408   @param[in] PciIo          The PCI IO protocol instance.
 409   @param[in] Slot           The slot number of the SD card to send the command to.
 410   @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
 411   @param[in] Capability     The capability of the slot.
 412
 413   @retval EFI_SUCCESS       The clock is supplied successfully.
 414   @retval Others            The clock isn't supplied successfully.
 415
 416 **/
 417 EFI_STATUS
 418 SdMmcHcClockSupply (
 419   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 420   IN UINT8                  Slot,
 421   IN UINT64                 ClockFreq,
 422   IN SD_MMC_HC_SLOT_CAP     Capability
 423   );
 424
 425 /**
 426   SD/MMC bus power control.
 427
 428   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 429
 430   @param[in] PciIo          The PCI IO protocol instance.
 431   @param[in] Slot           The slot number of the SD card to send the command to.
 432   @param[in] PowerCtrl      The value setting to the power control register.
 433
 434   @retval TRUE              There is a SD/MMC card attached.
 435   @retval FALSE             There is no a SD/MMC card attached.
 436
 437 **/
 438 EFI_STATUS
 439 SdMmcHcPowerControl (
 440   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 441   IN UINT8                  Slot,
 442   IN UINT8                  PowerCtrl
 443   );
 444
 445 /**
 446   Set the SD/MMC bus width.
 447
 448   Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
 449
 450   @param[in] PciIo          The PCI IO protocol instance.
 451   @param[in] Slot           The slot number of the SD card to send the command to.
 452   @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
 453
 454   @retval EFI_SUCCESS       The bus width is set successfully.
 455   @retval Others            The bus width isn't set successfully.
 456
 457 **/
 458 EFI_STATUS
 459 SdMmcHcSetBusWidth (
 460   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 461   IN UINT8                  Slot,
 462   IN UINT16                 BusWidth
 463   );
 464
 465 /**
 466   Supply SD/MMC card with lowest clock frequency at initialization.
 467
 468   @param[in] PciIo          The PCI IO protocol instance.
 469   @param[in] Slot           The slot number of the SD card to send the command to.
 470   @param[in] Capability     The capability of the slot.
 471
 472   @retval EFI_SUCCESS       The clock is supplied successfully.
 473   @retval Others            The clock isn't supplied successfully.
 474
 475 **/
 476 EFI_STATUS
 477 SdMmcHcInitClockFreq (
 478   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 479   IN UINT8                  Slot,
 480   IN SD_MMC_HC_SLOT_CAP     Capability
 481   );
 482
 483 /**
 484   Supply SD/MMC card with maximum voltage at initialization.
 485
 486   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 487
 488   @param[in] PciIo          The PCI IO protocol instance.
 489   @param[in] Slot           The slot number of the SD card to send the command to.
 490   @param[in] Capability     The capability of the slot.
 491
 492   @retval EFI_SUCCESS       The voltage is supplied successfully.
 493   @retval Others            The voltage isn't supplied successfully.
 494
 495 **/
 496 EFI_STATUS
 497 SdMmcHcInitPowerVoltage (
 498   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 499   IN UINT8                  Slot,
 500   IN SD_MMC_HC_SLOT_CAP     Capability
 501   );
 502
 503 /**
 504   Initialize the Timeout Control register with most conservative value at initialization.
 505
 506   Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
 507
 508   @param[in] PciIo          The PCI IO protocol instance.
 509   @param[in] Slot           The slot number of the SD card to send the command to.
 510
 511   @retval EFI_SUCCESS       The timeout control register is configured successfully.
 512   @retval Others            The timeout control register isn't configured successfully.
 513
 514 **/
 515 EFI_STATUS
 516 SdMmcHcInitTimeoutCtrl (
 517   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 518   IN UINT8                  Slot
 519   );
 520
 521 #endif