MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h

   1 /** @file
   2
   3   Provides some data structure definitions used by the SD/MMC host controller driver.
   4
   5 Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
   6 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   7 This program and the accompanying materials
   8 are licensed and made available under the terms and conditions of the BSD License
   9 which accompanies this distribution.  The full text of the license may be found at
  10 http://opensource.org/licenses/bsd-license.php
  11
  12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #ifndef _SD_MMC_PCI_HCI_H_
  18 #define _SD_MMC_PCI_HCI_H_
  19
  20 //
  21 // SD Host Controller SlotInfo Register Offset
  22 //
  23 #define SD_MMC_HC_SLOT_OFFSET         0x40
  24
  25 #define SD_MMC_HC_MAX_SLOT            6
  26
  27 //
  28 // SD Host Controller MMIO Register Offset
  29 //
  30 #define SD_MMC_HC_SDMA_ADDR           0x00
  31 #define SD_MMC_HC_ARG2                0x00
  32 #define SD_MMC_HC_BLK_SIZE            0x04
  33 #define SD_MMC_HC_BLK_COUNT           0x06
  34 #define SD_MMC_HC_ARG1                0x08
  35 #define SD_MMC_HC_TRANS_MOD           0x0C
  36 #define SD_MMC_HC_COMMAND             0x0E
  37 #define SD_MMC_HC_RESPONSE            0x10
  38 #define SD_MMC_HC_BUF_DAT_PORT        0x20
  39 #define SD_MMC_HC_PRESENT_STATE       0x24
  40 #define SD_MMC_HC_HOST_CTRL1          0x28
  41 #define SD_MMC_HC_POWER_CTRL          0x29
  42 #define SD_MMC_HC_BLK_GAP_CTRL        0x2A
  43 #define SD_MMC_HC_WAKEUP_CTRL         0x2B
  44 #define SD_MMC_HC_CLOCK_CTRL          0x2C
  45 #define SD_MMC_HC_TIMEOUT_CTRL        0x2E
  46 #define SD_MMC_HC_SW_RST              0x2F
  47 #define SD_MMC_HC_NOR_INT_STS         0x30
  48 #define SD_MMC_HC_ERR_INT_STS         0x32
  49 #define SD_MMC_HC_NOR_INT_STS_EN      0x34
  50 #define SD_MMC_HC_ERR_INT_STS_EN      0x36
  51 #define SD_MMC_HC_NOR_INT_SIG_EN      0x38
  52 #define SD_MMC_HC_ERR_INT_SIG_EN      0x3A
  53 #define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C
  54 #define SD_MMC_HC_HOST_CTRL2          0x3E
  55 #define SD_MMC_HC_CAP                 0x40
  56 #define SD_MMC_HC_MAX_CURRENT_CAP     0x48
  57 #define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50
  58 #define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52
  59 #define SD_MMC_HC_ADMA_ERR_STS        0x54
  60 #define SD_MMC_HC_ADMA_SYS_ADDR       0x58
  61 #define SD_MMC_HC_PRESET_VAL          0x60
  62 #define SD_MMC_HC_SHARED_BUS_CTRL     0xE0
  63 #define SD_MMC_HC_SLOT_INT_STS        0xFC
  64 #define SD_MMC_HC_CTRL_VER            0xFE
  65
  66 //
  67 // SD Host Controller bits to HOST_CTRL2 register
  68 //
  69 #define SD_MMC_HC_CTRL_UHS_MASK       0x0007
  70 #define SD_MMC_HC_CTRL_UHS_SDR12      0x0000
  71 #define SD_MMC_HC_CTRL_UHS_SDR25      0x0001
  72 #define SD_MMC_HC_CTRL_UHS_SDR50      0x0002
  73 #define SD_MMC_HC_CTRL_UHS_SDR104     0x0003
  74 #define SD_MMC_HC_CTRL_UHS_DDR50      0x0004
  75 #define SD_MMC_HC_CTRL_MMC_LEGACY     0x0000
  76 #define SD_MMC_HC_CTRL_MMC_HS_SDR     0x0001
  77 #define SD_MMC_HC_CTRL_MMC_HS_DDR     0x0004
  78 #define SD_MMC_HC_CTRL_MMC_HS200      0x0003
  79 #define SD_MMC_HC_CTRL_MMC_HS400      0x0005
  80
  81 //
  82 // The transfer modes supported by SD Host Controller
  83 // Simplified Spec 3.0 Table 1-2
  84 //
  85 typedef enum {
  86   SdMmcNoData,
  87   SdMmcPioMode,
  88   SdMmcSdmaMode,
  89   SdMmcAdmaMode
  90 } SD_MMC_HC_TRANSFER_MODE;
  91
  92 //
  93 // The maximum data length of each descriptor line
  94 //
  95 #define ADMA_MAX_DATA_PER_LINE_16B     SIZE_64KB
  96 #define ADMA_MAX_DATA_PER_LINE_26B     SIZE_64MB
  97
  98 //
  99 // ADMA descriptor for 32b addressing.
 100 //
 101 typedef struct {
 102   UINT32 Valid:1;
 103   UINT32 End:1;
 104   UINT32 Int:1;
 105   UINT32 Reserved:1;
 106   UINT32 Act:2;
 107   UINT32 UpperLength:10;
 108   UINT32 LowerLength:16;
 109   UINT32 Address;
 110 } SD_MMC_HC_ADMA_32_DESC_LINE;
 111
 112 //
 113 // ADMA descriptor for 64b addressing.
 114 //
 115 typedef struct {
 116   UINT32 Valid:1;
 117   UINT32 End:1;
 118   UINT32 Int:1;
 119   UINT32 Reserved:1;
 120   UINT32 Act:2;
 121   UINT32 UpperLength:10;
 122   UINT32 LowerLength:16;
 123   UINT32 LowerAddress;
 124   UINT32 UpperAddress;
 125   UINT32 Reserved1;
 126 } SD_MMC_HC_ADMA_64_DESC_LINE;
 127
 128 #define SD_MMC_SDMA_BOUNDARY          512 * 1024
 129 #define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))
 130
 131 typedef struct {
 132   UINT8    FirstBar:3;        // bit 0:2
 133   UINT8    Reserved:1;        // bit 3
 134   UINT8    SlotNum:3;         // bit 4:6
 135   UINT8    Reserved1:1;       // bit 7
 136 } SD_MMC_HC_SLOT_INFO;
 137
 138 typedef struct {
 139   UINT32   TimeoutFreq:6;     // bit 0:5
 140   UINT32   Reserved:1;        // bit 6
 141   UINT32   TimeoutUnit:1;     // bit 7
 142   UINT32   BaseClkFreq:8;     // bit 8:15
 143   UINT32   MaxBlkLen:2;       // bit 16:17
 144   UINT32   BusWidth8:1;       // bit 18
 145   UINT32   Adma2:1;           // bit 19
 146   UINT32   Reserved2:1;       // bit 20
 147   UINT32   HighSpeed:1;       // bit 21
 148   UINT32   Sdma:1;            // bit 22
 149   UINT32   SuspRes:1;         // bit 23
 150   UINT32   Voltage33:1;       // bit 24
 151   UINT32   Voltage30:1;       // bit 25
 152   UINT32   Voltage18:1;       // bit 26
 153   UINT32   SysBus64V4:1;      // bit 27
 154   UINT32   SysBus64V3:1;      // bit 28
 155   UINT32   AsyncInt:1;        // bit 29
 156   UINT32   SlotType:2;        // bit 30:31
 157   UINT32   Sdr50:1;           // bit 32
 158   UINT32   Sdr104:1;          // bit 33
 159   UINT32   Ddr50:1;           // bit 34
 160   UINT32   Reserved3:1;       // bit 35
 161   UINT32   DriverTypeA:1;     // bit 36
 162   UINT32   DriverTypeC:1;     // bit 37
 163   UINT32   DriverTypeD:1;     // bit 38
 164   UINT32   DriverType4:1;     // bit 39
 165   UINT32   TimerCount:4;      // bit 40:43
 166   UINT32   Reserved4:1;       // bit 44
 167   UINT32   TuningSDR50:1;     // bit 45
 168   UINT32   RetuningMod:2;     // bit 46:47
 169   UINT32   ClkMultiplier:8;   // bit 48:55
 170   UINT32   Reserved5:7;       // bit 56:62
 171   UINT32   Hs400:1;           // bit 63
 172 } SD_MMC_HC_SLOT_CAP;
 173
 174 //
 175 // SD Host controller version
 176 //
 177 #define SD_MMC_HC_CTRL_VER_100        0x00
 178 #define SD_MMC_HC_CTRL_VER_200        0x01
 179 #define SD_MMC_HC_CTRL_VER_300        0x02
 180 #define SD_MMC_HC_CTRL_VER_400        0x03
 181 #define SD_MMC_HC_CTRL_VER_410        0x04
 182 #define SD_MMC_HC_CTRL_VER_420        0x05
 183
 184 //
 185 // SD Host controller V4 enhancements
 186 //
 187 #define SD_MMC_HC_V4_EN               BIT12
 188 #define SD_MMC_HC_64_ADDR_EN          BIT13
 189 #define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
 190
 191 /**
 192   Dump the content of SD/MMC host controller's Capability Register.
 193
 194   @param[in]  Slot            The slot number of the SD card to send the command to.
 195   @param[in]  Capability      The buffer to store the capability data.
 196
 197 **/
 198 VOID
 199 DumpCapabilityReg (
 200   IN UINT8                Slot,
 201   IN SD_MMC_HC_SLOT_CAP   *Capability
 202   );
 203
 204 /**
 205   Read SlotInfo register from SD/MMC host controller pci config space.
 206
 207   @param[in]  PciIo        The PCI IO protocol instance.
 208   @param[out] FirstBar     The buffer to store the first BAR value.
 209   @param[out] SlotNum      The buffer to store the supported slot number.
 210
 211   @retval EFI_SUCCESS      The operation succeeds.
 212   @retval Others           The operation fails.
 213
 214 **/
 215 EFI_STATUS
 216 EFIAPI
 217 SdMmcHcGetSlotInfo (
 218   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 219      OUT UINT8                 *FirstBar,
 220      OUT UINT8                 *SlotNum
 221   );
 222
 223 /**
 224   Read/Write specified SD/MMC host controller mmio register.
 225
 226   @param[in]      PciIo        The PCI IO protocol instance.
 227   @param[in]      BarIndex     The BAR index of the standard PCI Configuration
 228                                header to use as the base address for the memory
 229                                operation to perform.
 230   @param[in]      Offset       The offset within the selected BAR to start the
 231                                memory operation.
 232   @param[in]      Read         A boolean to indicate it's read or write operation.
 233   @param[in]      Count        The width of the mmio register in bytes.
 234                                Must be 1, 2 , 4 or 8 bytes.
 235   @param[in, out] Data         For read operations, the destination buffer to store
 236                                the results. For write operations, the source buffer
 237                                to write data from. The caller is responsible for
 238                                having ownership of the data buffer and ensuring its
 239                                size not less than Count bytes.
 240
 241   @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
 242   @retval EFI_SUCCESS           The read/write operation succeeds.
 243   @retval Others                The read/write operation fails.
 244
 245 **/
 246 EFI_STATUS
 247 EFIAPI
 248 SdMmcHcRwMmio (
 249   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 250   IN     UINT8                 BarIndex,
 251   IN     UINT32                Offset,
 252   IN     BOOLEAN               Read,
 253   IN     UINT8                 Count,
 254   IN OUT VOID                  *Data
 255   );
 256
 257 /**
 258   Do OR operation with the value of the specified SD/MMC host controller mmio register.
 259
 260   @param[in] PciIo             The PCI IO protocol instance.
 261   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 262                                header to use as the base address for the memory
 263                                operation to perform.
 264   @param[in] Offset            The offset within the selected BAR to start the
 265                                memory operation.
 266   @param[in] Count             The width of the mmio register in bytes.
 267                                Must be 1, 2 , 4 or 8 bytes.
 268   @param[in] OrData            The pointer to the data used to do OR operation.
 269                                The caller is responsible for having ownership of
 270                                the data buffer and ensuring its size not less than
 271                                Count bytes.
 272
 273   @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
 274   @retval EFI_SUCCESS           The OR operation succeeds.
 275   @retval Others                The OR operation fails.
 276
 277 **/
 278 EFI_STATUS
 279 EFIAPI
 280 SdMmcHcOrMmio (
 281   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 282   IN  UINT8                    BarIndex,
 283   IN  UINT32                   Offset,
 284   IN  UINT8                    Count,
 285   IN  VOID                     *OrData
 286   );
 287
 288 /**
 289   Do AND operation with the value of the specified SD/MMC host controller mmio register.
 290
 291   @param[in] PciIo             The PCI IO protocol instance.
 292   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 293                                header to use as the base address for the memory
 294                                operation to perform.
 295   @param[in] Offset            The offset within the selected BAR to start the
 296                                memory operation.
 297   @param[in] Count             The width of the mmio register in bytes.
 298                                Must be 1, 2 , 4 or 8 bytes.
 299   @param[in] AndData           The pointer to the data used to do AND operation.
 300                                The caller is responsible for having ownership of
 301                                the data buffer and ensuring its size not less than
 302                                Count bytes.
 303
 304   @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
 305   @retval EFI_SUCCESS           The AND operation succeeds.
 306   @retval Others                The AND operation fails.
 307
 308 **/
 309 EFI_STATUS
 310 EFIAPI
 311 SdMmcHcAndMmio (
 312   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 313   IN  UINT8                    BarIndex,
 314   IN  UINT32                   Offset,
 315   IN  UINT8                    Count,
 316   IN  VOID                     *AndData
 317   );
 318
 319 /**
 320   Wait for the value of the specified MMIO register set to the test value.
 321
 322   @param[in]  PciIo         The PCI IO protocol instance.
 323   @param[in]  BarIndex      The BAR index of the standard PCI Configuration
 324                             header to use as the base address for the memory
 325                             operation to perform.
 326   @param[in]  Offset        The offset within the selected BAR to start the
 327                             memory operation.
 328   @param[in]  Count         The width of the mmio register in bytes.
 329                             Must be 1, 2, 4 or 8 bytes.
 330   @param[in]  MaskValue     The mask value of memory.
 331   @param[in]  TestValue     The test value of memory.
 332   @param[in]  Timeout       The time out value for wait memory set, uses 1
 333                             microsecond as a unit.
 334
 335   @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
 336                             range.
 337   @retval EFI_SUCCESS       The MMIO register has expected value.
 338   @retval Others            The MMIO operation fails.
 339
 340 **/
 341 EFI_STATUS
 342 EFIAPI
 343 SdMmcHcWaitMmioSet (
 344   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 345   IN  UINT8                     BarIndex,
 346   IN  UINT32                    Offset,
 347   IN  UINT8                     Count,
 348   IN  UINT64                    MaskValue,
 349   IN  UINT64                    TestValue,
 350   IN  UINT64                    Timeout
 351   );
 352
 353 /**
 354   Get the controller version information from the specified slot.
 355
 356   @param[in]  PciIo           The PCI IO protocol instance.
 357   @param[in]  Slot            The slot number of the SD card to send the command to.
 358   @param[out] Version         The buffer to store the version information.
 359
 360   @retval EFI_SUCCESS         The operation executes successfully.
 361   @retval Others              The operation fails.
 362
 363 **/
 364 EFI_STATUS
 365 SdMmcHcGetControllerVersion (
 366   IN  EFI_PCI_IO_PROTOCOL  *PciIo,
 367   IN  UINT8                Slot,
 368   OUT UINT16               *Version
 369   );
 370
 371 /**
 372   Set all interrupt status bits in Normal and Error Interrupt Status Enable
 373   register.
 374
 375   @param[in] PciIo          The PCI IO protocol instance.
 376   @param[in] Slot           The slot number of the SD card to send the command to.
 377
 378   @retval EFI_SUCCESS       The operation executes successfully.
 379   @retval Others            The operation fails.
 380
 381 **/
 382 EFI_STATUS
 383 SdMmcHcEnableInterrupt (
 384   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 385   IN UINT8                  Slot
 386   );
 387
 388 /**
 389   Get the capability data from the specified slot.
 390
 391   @param[in]  PciIo           The PCI IO protocol instance.
 392   @param[in]  Slot            The slot number of the SD card to send the command to.
 393   @param[out] Capability      The buffer to store the capability data.
 394
 395   @retval EFI_SUCCESS         The operation executes successfully.
 396   @retval Others              The operation fails.
 397
 398 **/
 399 EFI_STATUS
 400 SdMmcHcGetCapability (
 401   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 402   IN     UINT8                Slot,
 403      OUT SD_MMC_HC_SLOT_CAP   *Capability
 404   );
 405
 406 /**
 407   Get the maximum current capability data from the specified slot.
 408
 409   @param[in]  PciIo           The PCI IO protocol instance.
 410   @param[in]  Slot            The slot number of the SD card to send the command to.
 411   @param[out] MaxCurrent      The buffer to store the maximum current capability data.
 412
 413   @retval EFI_SUCCESS         The operation executes successfully.
 414   @retval Others              The operation fails.
 415
 416 **/
 417 EFI_STATUS
 418 SdMmcHcGetMaxCurrent (
 419   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 420   IN     UINT8                Slot,
 421      OUT UINT64               *MaxCurrent
 422   );
 423
 424 /**
 425   Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
 426   slot.
 427
 428   Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
 429
 430   @param[in]  PciIo         The PCI IO protocol instance.
 431   @param[in]  Slot          The slot number of the SD card to send the command to.
 432   @param[out] MediaPresent  The pointer to the media present boolean value.
 433
 434   @retval EFI_SUCCESS       There is no media change happened.
 435   @retval EFI_MEDIA_CHANGED There is media change happened.
 436   @retval Others            The detection fails.
 437
 438 **/
 439 EFI_STATUS
 440 SdMmcHcCardDetect (
 441   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 442   IN UINT8                  Slot,
 443      OUT BOOLEAN            *MediaPresent
 444   );
 445
 446 /**
 447   Stop SD/MMC card clock.
 448
 449   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
 450
 451   @param[in] PciIo          The PCI IO protocol instance.
 452   @param[in] Slot           The slot number of the SD card to send the command to.
 453
 454   @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
 455   @retval Others            Fail to stop SD/MMC clock.
 456
 457 **/
 458 EFI_STATUS
 459 SdMmcHcStopClock (
 460   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 461   IN UINT8                  Slot
 462   );
 463
 464 /**
 465   SD/MMC card clock supply.
 466
 467   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
 468
 469   @param[in] PciIo          The PCI IO protocol instance.
 470   @param[in] Slot           The slot number of the SD card to send the command to.
 471   @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
 472   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 473   @param[in] ControllerVer  The version of host controller.
 474
 475   @retval EFI_SUCCESS       The clock is supplied successfully.
 476   @retval Others            The clock isn't supplied successfully.
 477
 478 **/
 479 EFI_STATUS
 480 SdMmcHcClockSupply (
 481   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 482   IN UINT8                  Slot,
 483   IN UINT64                 ClockFreq,
 484   IN UINT32                 BaseClkFreq,
 485   IN UINT16                 ControllerVer
 486   );
 487
 488 /**
 489   SD/MMC bus power control.
 490
 491   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 492
 493   @param[in] PciIo          The PCI IO protocol instance.
 494   @param[in] Slot           The slot number of the SD card to send the command to.
 495   @param[in] PowerCtrl      The value setting to the power control register.
 496
 497   @retval TRUE              There is a SD/MMC card attached.
 498   @retval FALSE             There is no a SD/MMC card attached.
 499
 500 **/
 501 EFI_STATUS
 502 SdMmcHcPowerControl (
 503   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 504   IN UINT8                  Slot,
 505   IN UINT8                  PowerCtrl
 506   );
 507
 508 /**
 509   Set the SD/MMC bus width.
 510
 511   Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
 512
 513   @param[in] PciIo          The PCI IO protocol instance.
 514   @param[in] Slot           The slot number of the SD card to send the command to.
 515   @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
 516
 517   @retval EFI_SUCCESS       The bus width is set successfully.
 518   @retval Others            The bus width isn't set successfully.
 519
 520 **/
 521 EFI_STATUS
 522 SdMmcHcSetBusWidth (
 523   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 524   IN UINT8                  Slot,
 525   IN UINT16                 BusWidth
 526   );
 527
 528 /**
 529   Supply SD/MMC card with lowest clock frequency at initialization.
 530
 531   @param[in] PciIo          The PCI IO protocol instance.
 532   @param[in] Slot           The slot number of the SD card to send the command to.
 533   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 534   @param[in] ControllerVer  The version of host controller.
 535
 536   @retval EFI_SUCCESS       The clock is supplied successfully.
 537   @retval Others            The clock isn't supplied successfully.
 538
 539 **/
 540 EFI_STATUS
 541 SdMmcHcInitClockFreq (
 542   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 543   IN UINT8                  Slot,
 544   IN UINT32                 BaseClkFreq,
 545   IN UINT16                 ControllerVer
 546   );
 547
 548 /**
 549   Supply SD/MMC card with maximum voltage at initialization.
 550
 551   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 552
 553   @param[in] PciIo          The PCI IO protocol instance.
 554   @param[in] Slot           The slot number of the SD card to send the command to.
 555   @param[in] Capability     The capability of the slot.
 556
 557   @retval EFI_SUCCESS       The voltage is supplied successfully.
 558   @retval Others            The voltage isn't supplied successfully.
 559
 560 **/
 561 EFI_STATUS
 562 SdMmcHcInitPowerVoltage (
 563   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 564   IN UINT8                  Slot,
 565   IN SD_MMC_HC_SLOT_CAP     Capability
 566   );
 567
 568 /**
 569   Initialize the Timeout Control register with most conservative value at initialization.
 570
 571   Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
 572
 573   @param[in] PciIo          The PCI IO protocol instance.
 574   @param[in] Slot           The slot number of the SD card to send the command to.
 575
 576   @retval EFI_SUCCESS       The timeout control register is configured successfully.
 577   @retval Others            The timeout control register isn't configured successfully.
 578
 579 **/
 580 EFI_STATUS
 581 SdMmcHcInitTimeoutCtrl (
 582   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 583   IN UINT8                  Slot
 584   );
 585
 586 /**
 587   Set SD Host Controller control 2 registry according to selected speed.
 588
 589   @param[in] ControllerHandle The handle of the controller.
 590   @param[in] PciIo            The PCI IO protocol instance.
 591   @param[in] Slot             The slot number of the SD card to send the command to.
 592   @param[in] Timing           The timing to select.
 593
 594   @retval EFI_SUCCESS         The timing is set successfully.
 595   @retval Others              The timing isn't set successfully.
 596 **/
 597 EFI_STATUS
 598 SdMmcHcUhsSignaling (
 599   IN EFI_HANDLE             ControllerHandle,
 600   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 601   IN UINT8                  Slot,
 602   IN SD_MMC_BUS_MODE        Timing
 603   );
 604
 605 #endif