MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h

   1 /** @file
   2
   3   Provides some data structure definitions used by the SD/MMC host controller driver.
   4
   5 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _SD_MMC_PCI_HCI_H_
  17 #define _SD_MMC_PCI_HCI_H_
  18
  19 //
  20 // SD Host Controller SlotInfo Register Offset
  21 //
  22 #define SD_MMC_HC_SLOT_OFFSET         0x40
  23
  24 #define SD_MMC_HC_MAX_SLOT            6
  25
  26 //
  27 // SD Host Controller MMIO Register Offset
  28 //
  29 #define SD_MMC_HC_SDMA_ADDR           0x00
  30 #define SD_MMC_HC_ARG2                0x00
  31 #define SD_MMC_HC_BLK_SIZE            0x04
  32 #define SD_MMC_HC_BLK_COUNT           0x06
  33 #define SD_MMC_HC_ARG1                0x08
  34 #define SD_MMC_HC_TRANS_MOD           0x0C
  35 #define SD_MMC_HC_COMMAND             0x0E
  36 #define SD_MMC_HC_RESPONSE            0x10
  37 #define SD_MMC_HC_BUF_DAT_PORT        0x20
  38 #define SD_MMC_HC_PRESENT_STATE       0x24
  39 #define SD_MMC_HC_HOST_CTRL1          0x28
  40 #define SD_MMC_HC_POWER_CTRL          0x29
  41 #define SD_MMC_HC_BLK_GAP_CTRL        0x2A
  42 #define SD_MMC_HC_WAKEUP_CTRL         0x2B
  43 #define SD_MMC_HC_CLOCK_CTRL          0x2C
  44 #define SD_MMC_HC_TIMEOUT_CTRL        0x2E
  45 #define SD_MMC_HC_SW_RST              0x2F
  46 #define SD_MMC_HC_NOR_INT_STS         0x30
  47 #define SD_MMC_HC_ERR_INT_STS         0x32
  48 #define SD_MMC_HC_NOR_INT_STS_EN      0x34
  49 #define SD_MMC_HC_ERR_INT_STS_EN      0x36
  50 #define SD_MMC_HC_NOR_INT_SIG_EN      0x38
  51 #define SD_MMC_HC_ERR_INT_SIG_EN      0x3A
  52 #define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C
  53 #define SD_MMC_HC_HOST_CTRL2          0x3E
  54 #define SD_MMC_HC_CAP                 0x40
  55 #define SD_MMC_HC_MAX_CURRENT_CAP     0x48
  56 #define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50
  57 #define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52
  58 #define SD_MMC_HC_ADMA_ERR_STS        0x54
  59 #define SD_MMC_HC_ADMA_SYS_ADDR       0x58
  60 #define SD_MMC_HC_PRESET_VAL          0x60
  61 #define SD_MMC_HC_SHARED_BUS_CTRL     0xE0
  62 #define SD_MMC_HC_SLOT_INT_STS        0xFC
  63 #define SD_MMC_HC_CTRL_VER            0xFE
  64
  65 //
  66 // The transfer modes supported by SD Host Controller
  67 // Simplified Spec 3.0 Table 1-2
  68 //
  69 typedef enum {
  70   SdMmcNoData,
  71   SdMmcPioMode,
  72   SdMmcSdmaMode,
  73   SdMmcAdmaMode
  74 } SD_MMC_HC_TRANSFER_MODE;
  75
  76 //
  77 // The maximum data length of each descriptor line
  78 //
  79 #define ADMA_MAX_DATA_PER_LINE     0x10000
  80
  81 typedef struct {
  82   UINT32 Valid:1;
  83   UINT32 End:1;
  84   UINT32 Int:1;
  85   UINT32 Reserved:1;
  86   UINT32 Act:2;
  87   UINT32 Reserved1:10;
  88   UINT32 Length:16;
  89   UINT32 Address;
  90 } SD_MMC_HC_ADMA_DESC_LINE;
  91
  92 #define SD_MMC_SDMA_BOUNDARY          512 * 1024
  93 #define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))
  94
  95 typedef struct {
  96   UINT8    FirstBar:3;        // bit 0:2
  97   UINT8    Reserved:1;        // bit 3
  98   UINT8    SlotNum:3;         // bit 4:6
  99   UINT8    Reserved1:1;       // bit 7
 100 } SD_MMC_HC_SLOT_INFO;
 101
 102 typedef struct {
 103   UINT32   TimeoutFreq:6;     // bit 0:5
 104   UINT32   Reserved:1;        // bit 6
 105   UINT32   TimeoutUnit:1;     // bit 7
 106   UINT32   BaseClkFreq:8;     // bit 8:15
 107   UINT32   MaxBlkLen:2;       // bit 16:17
 108   UINT32   BusWidth8:1;       // bit 18
 109   UINT32   Adma2:1;           // bit 19
 110   UINT32   Reserved2:1;       // bit 20
 111   UINT32   HighSpeed:1;       // bit 21
 112   UINT32   Sdma:1;            // bit 22
 113   UINT32   SuspRes:1;         // bit 23
 114   UINT32   Voltage33:1;       // bit 24
 115   UINT32   Voltage30:1;       // bit 25
 116   UINT32   Voltage18:1;       // bit 26
 117   UINT32   Reserved3:1;       // bit 27
 118   UINT32   SysBus64:1;        // bit 28
 119   UINT32   AsyncInt:1;        // bit 29
 120   UINT32   SlotType:2;        // bit 30:31
 121   UINT32   Sdr50:1;           // bit 32
 122   UINT32   Sdr104:1;          // bit 33
 123   UINT32   Ddr50:1;           // bit 34
 124   UINT32   Reserved4:1;       // bit 35
 125   UINT32   DriverTypeA:1;     // bit 36
 126   UINT32   DriverTypeC:1;     // bit 37
 127   UINT32   DriverTypeD:1;     // bit 38
 128   UINT32   DriverType4:1;     // bit 39
 129   UINT32   TimerCount:4;      // bit 40:43
 130   UINT32   Reserved5:1;       // bit 44
 131   UINT32   TuningSDR50:1;     // bit 45
 132   UINT32   RetuningMod:2;     // bit 46:47
 133   UINT32   ClkMultiplier:8;   // bit 48:55
 134   UINT32   Reserved6:7;       // bit 56:62
 135   UINT32   Hs400:1;           // bit 63
 136 } SD_MMC_HC_SLOT_CAP;
 137
 138 /**
 139   Dump the content of SD/MMC host controller's Capability Register.
 140
 141   @param[in]  Slot            The slot number of the SD card to send the command to.
 142   @param[in]  Capability      The buffer to store the capability data.
 143
 144 **/
 145 VOID
 146 DumpCapabilityReg (
 147   IN UINT8                Slot,
 148   IN SD_MMC_HC_SLOT_CAP   *Capability
 149   );
 150
 151 /**
 152   Read SlotInfo register from SD/MMC host controller pci config space.
 153
 154   @param[in]  PciIo        The PCI IO protocol instance.
 155   @param[out] FirstBar     The buffer to store the first BAR value.
 156   @param[out] SlotNum      The buffer to store the supported slot number.
 157
 158   @retval EFI_SUCCESS      The operation succeeds.
 159   @retval Others           The operation fails.
 160
 161 **/
 162 EFI_STATUS
 163 EFIAPI
 164 SdMmcHcGetSlotInfo (
 165   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 166      OUT UINT8                 *FirstBar,
 167      OUT UINT8                 *SlotNum
 168   );
 169
 170 /**
 171   Read/Write specified SD/MMC host controller mmio register.
 172
 173   @param[in]      PciIo        The PCI IO protocol instance.
 174   @param[in]      BarIndex     The BAR index of the standard PCI Configuration
 175                                header to use as the base address for the memory
 176                                operation to perform.
 177   @param[in]      Offset       The offset within the selected BAR to start the
 178                                memory operation.
 179   @param[in]      Read         A boolean to indicate it's read or write operation.
 180   @param[in]      Count        The width of the mmio register in bytes.
 181                                Must be 1, 2 , 4 or 8 bytes.
 182   @param[in, out] Data         For read operations, the destination buffer to store
 183                                the results. For write operations, the source buffer
 184                                to write data from. The caller is responsible for
 185                                having ownership of the data buffer and ensuring its
 186                                size not less than Count bytes.
 187
 188   @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
 189   @retval EFI_SUCCESS           The read/write operation succeeds.
 190   @retval Others                The read/write operation fails.
 191
 192 **/
 193 EFI_STATUS
 194 EFIAPI
 195 SdMmcHcRwMmio (
 196   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 197   IN     UINT8                 BarIndex,
 198   IN     UINT32                Offset,
 199   IN     BOOLEAN               Read,
 200   IN     UINT8                 Count,
 201   IN OUT VOID                  *Data
 202   );
 203
 204 /**
 205   Do OR operation with the value of the specified SD/MMC host controller mmio register.
 206
 207   @param[in] PciIo             The PCI IO protocol instance.
 208   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 209                                header to use as the base address for the memory
 210                                operation to perform.
 211   @param[in] Offset            The offset within the selected BAR to start the
 212                                memory operation.
 213   @param[in] Count             The width of the mmio register in bytes.
 214                                Must be 1, 2 , 4 or 8 bytes.
 215   @param[in] OrData            The pointer to the data used to do OR operation.
 216                                The caller is responsible for having ownership of
 217                                the data buffer and ensuring its size not less than
 218                                Count bytes.
 219
 220   @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
 221   @retval EFI_SUCCESS           The OR operation succeeds.
 222   @retval Others                The OR operation fails.
 223
 224 **/
 225 EFI_STATUS
 226 EFIAPI
 227 SdMmcHcOrMmio (
 228   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 229   IN  UINT8                    BarIndex,
 230   IN  UINT32                   Offset,
 231   IN  UINT8                    Count,
 232   IN  VOID                     *OrData
 233   );
 234
 235 /**
 236   Do AND operation with the value of the specified SD/MMC host controller mmio register.
 237
 238   @param[in] PciIo             The PCI IO protocol instance.
 239   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 240                                header to use as the base address for the memory
 241                                operation to perform.
 242   @param[in] Offset            The offset within the selected BAR to start the
 243                                memory operation.
 244   @param[in] Count             The width of the mmio register in bytes.
 245                                Must be 1, 2 , 4 or 8 bytes.
 246   @param[in] AndData           The pointer to the data used to do AND operation.
 247                                The caller is responsible for having ownership of
 248                                the data buffer and ensuring its size not less than
 249                                Count bytes.
 250
 251   @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
 252   @retval EFI_SUCCESS           The AND operation succeeds.
 253   @retval Others                The AND operation fails.
 254
 255 **/
 256 EFI_STATUS
 257 EFIAPI
 258 SdMmcHcAndMmio (
 259   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 260   IN  UINT8                    BarIndex,
 261   IN  UINT32                   Offset,
 262   IN  UINT8                    Count,
 263   IN  VOID                     *AndData
 264   );
 265
 266 /**
 267   Wait for the value of the specified MMIO register set to the test value.
 268
 269   @param[in]  PciIo         The PCI IO protocol instance.
 270   @param[in]  BarIndex      The BAR index of the standard PCI Configuration
 271                             header to use as the base address for the memory
 272                             operation to perform.
 273   @param[in]  Offset        The offset within the selected BAR to start the
 274                             memory operation.
 275   @param[in]  Count         The width of the mmio register in bytes.
 276                             Must be 1, 2, 4 or 8 bytes.
 277   @param[in]  MaskValue     The mask value of memory.
 278   @param[in]  TestValue     The test value of memory.
 279   @param[in]  Timeout       The time out value for wait memory set, uses 1
 280                             microsecond as a unit.
 281
 282   @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
 283                             range.
 284   @retval EFI_SUCCESS       The MMIO register has expected value.
 285   @retval Others            The MMIO operation fails.
 286
 287 **/
 288 EFI_STATUS
 289 EFIAPI
 290 SdMmcHcWaitMmioSet (
 291   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 292   IN  UINT8                     BarIndex,
 293   IN  UINT32                    Offset,
 294   IN  UINT8                     Count,
 295   IN  UINT64                    MaskValue,
 296   IN  UINT64                    TestValue,
 297   IN  UINT64                    Timeout
 298   );
 299
 300 /**
 301   Software reset the specified SD/MMC host controller.
 302
 303   @param[in] PciIo          The PCI IO protocol instance.
 304   @param[in] Slot           The slot number of the SD card to send the command to.
 305
 306   @retval EFI_SUCCESS       The software reset executes successfully.
 307   @retval Others            The software reset fails.
 308
 309 **/
 310 EFI_STATUS
 311 SdMmcHcReset (
 312   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 313   IN UINT8                  Slot
 314   );
 315
 316 /**
 317   Set all interrupt status bits in Normal and Error Interrupt Status Enable
 318   register.
 319
 320   @param[in] PciIo          The PCI IO protocol instance.
 321   @param[in] Slot           The slot number of the SD card to send the command to.
 322
 323   @retval EFI_SUCCESS       The operation executes successfully.
 324   @retval Others            The operation fails.
 325
 326 **/
 327 EFI_STATUS
 328 SdMmcHcEnableInterrupt (
 329   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 330   IN UINT8                  Slot
 331   );
 332
 333 /**
 334   Get the capability data from the specified slot.
 335
 336   @param[in]  PciIo           The PCI IO protocol instance.
 337   @param[in]  Slot            The slot number of the SD card to send the command to.
 338   @param[out] Capability      The buffer to store the capability data.
 339
 340   @retval EFI_SUCCESS         The operation executes successfully.
 341   @retval Others              The operation fails.
 342
 343 **/
 344 EFI_STATUS
 345 SdMmcHcGetCapability (
 346   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 347   IN     UINT8                Slot,
 348      OUT SD_MMC_HC_SLOT_CAP   *Capability
 349   );
 350
 351 /**
 352   Get the maximum current capability data from the specified slot.
 353
 354   @param[in]  PciIo           The PCI IO protocol instance.
 355   @param[in]  Slot            The slot number of the SD card to send the command to.
 356   @param[out] MaxCurrent      The buffer to store the maximum current capability data.
 357
 358   @retval EFI_SUCCESS         The operation executes successfully.
 359   @retval Others              The operation fails.
 360
 361 **/
 362 EFI_STATUS
 363 SdMmcHcGetMaxCurrent (
 364   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 365   IN     UINT8                Slot,
 366      OUT UINT64               *MaxCurrent
 367   );
 368
 369 /**
 370   Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
 371   slot.
 372
 373   Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
 374
 375   @param[in]  PciIo         The PCI IO protocol instance.
 376   @param[in]  Slot          The slot number of the SD card to send the command to.
 377   @param[out] MediaPresent  The pointer to the media present boolean value.
 378
 379   @retval EFI_SUCCESS       There is no media change happened.
 380   @retval EFI_MEDIA_CHANGED There is media change happened.
 381   @retval Others            The detection fails.
 382
 383 **/
 384 EFI_STATUS
 385 SdMmcHcCardDetect (
 386   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 387   IN UINT8                  Slot,
 388      OUT BOOLEAN            *MediaPresent
 389   );
 390
 391 /**
 392   Stop SD/MMC card clock.
 393
 394   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
 395
 396   @param[in] PciIo          The PCI IO protocol instance.
 397   @param[in] Slot           The slot number of the SD card to send the command to.
 398
 399   @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
 400   @retval Others            Fail to stop SD/MMC clock.
 401
 402 **/
 403 EFI_STATUS
 404 SdMmcHcStopClock (
 405   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 406   IN UINT8                  Slot
 407   );
 408
 409 /**
 410   SD/MMC card clock supply.
 411
 412   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
 413
 414   @param[in] PciIo          The PCI IO protocol instance.
 415   @param[in] Slot           The slot number of the SD card to send the command to.
 416   @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
 417   @param[in] Capability     The capability of the slot.
 418
 419   @retval EFI_SUCCESS       The clock is supplied successfully.
 420   @retval Others            The clock isn't supplied successfully.
 421
 422 **/
 423 EFI_STATUS
 424 SdMmcHcClockSupply (
 425   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 426   IN UINT8                  Slot,
 427   IN UINT64                 ClockFreq,
 428   IN SD_MMC_HC_SLOT_CAP     Capability
 429   );
 430
 431 /**
 432   SD/MMC bus power control.
 433
 434   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 435
 436   @param[in] PciIo          The PCI IO protocol instance.
 437   @param[in] Slot           The slot number of the SD card to send the command to.
 438   @param[in] PowerCtrl      The value setting to the power control register.
 439
 440   @retval TRUE              There is a SD/MMC card attached.
 441   @retval FALSE             There is no a SD/MMC card attached.
 442
 443 **/
 444 EFI_STATUS
 445 SdMmcHcPowerControl (
 446   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 447   IN UINT8                  Slot,
 448   IN UINT8                  PowerCtrl
 449   );
 450
 451 /**
 452   Set the SD/MMC bus width.
 453
 454   Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
 455
 456   @param[in] PciIo          The PCI IO protocol instance.
 457   @param[in] Slot           The slot number of the SD card to send the command to.
 458   @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
 459
 460   @retval EFI_SUCCESS       The bus width is set successfully.
 461   @retval Others            The bus width isn't set successfully.
 462
 463 **/
 464 EFI_STATUS
 465 SdMmcHcSetBusWidth (
 466   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 467   IN UINT8                  Slot,
 468   IN UINT16                 BusWidth
 469   );
 470
 471 /**
 472   Supply SD/MMC card with lowest clock frequency at initialization.
 473
 474   @param[in] PciIo          The PCI IO protocol instance.
 475   @param[in] Slot           The slot number of the SD card to send the command to.
 476   @param[in] Capability     The capability of the slot.
 477
 478   @retval EFI_SUCCESS       The clock is supplied successfully.
 479   @retval Others            The clock isn't supplied successfully.
 480
 481 **/
 482 EFI_STATUS
 483 SdMmcHcInitClockFreq (
 484   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 485   IN UINT8                  Slot,
 486   IN SD_MMC_HC_SLOT_CAP     Capability
 487   );
 488
 489 /**
 490   Supply SD/MMC card with maximum voltage at initialization.
 491
 492   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 493
 494   @param[in] PciIo          The PCI IO protocol instance.
 495   @param[in] Slot           The slot number of the SD card to send the command to.
 496   @param[in] Capability     The capability of the slot.
 497
 498   @retval EFI_SUCCESS       The voltage is supplied successfully.
 499   @retval Others            The voltage isn't supplied successfully.
 500
 501 **/
 502 EFI_STATUS
 503 SdMmcHcInitPowerVoltage (
 504   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 505   IN UINT8                  Slot,
 506   IN SD_MMC_HC_SLOT_CAP     Capability
 507   );
 508
 509 /**
 510   Initialize the Timeout Control register with most conservative value at initialization.
 511
 512   Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
 513
 514   @param[in] PciIo          The PCI IO protocol instance.
 515   @param[in] Slot           The slot number of the SD card to send the command to.
 516
 517   @retval EFI_SUCCESS       The timeout control register is configured successfully.
 518   @retval Others            The timeout control register isn't configured successfully.
 519
 520 **/
 521 EFI_STATUS
 522 SdMmcHcInitTimeoutCtrl (
 523   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 524   IN UINT8                  Slot
 525   );
 526
 527 /**
 528   Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
 529   at initialization.
 530
 531   @param[in] PciIo          The PCI IO protocol instance.
 532   @param[in] Slot           The slot number of the SD card to send the command to.
 533   @param[in] Capability     The capability of the slot.
 534
 535   @retval EFI_SUCCESS       The host controller is initialized successfully.
 536   @retval Others            The host controller isn't initialized successfully.
 537
 538 **/
 539 EFI_STATUS
 540 SdMmcHcInitHost (
 541   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 542   IN UINT8                  Slot,
 543   IN SD_MMC_HC_SLOT_CAP     Capability
 544   );
 545
 546 #endif