3 Copyright (c) 2004 - 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 The definition for UHCI driver model and HC protocol routines.
31 #include <Protocol/Usb2HostController.h>
32 #include <Protocol/UsbHostController.h>
33 #include <Protocol/PciIo.h>
35 #include <Library/DebugLib.h>
36 #include <Library/BaseMemoryLib.h>
37 #include <Library/UefiDriverEntryPoint.h>
38 #include <Library/UefiBootServicesTableLib.h>
39 #include <Library/UefiLib.h>
40 #include <Library/BaseLib.h>
41 #include <Library/MemoryAllocationLib.h>
43 #include <IndustryStandard/Pci22.h>
45 typedef struct _USB_HC_DEV USB_HC_DEV
;
48 #include "UhciQueue.h"
50 #include "UhciSched.h"
51 #include "UhciDebug.h"
54 UHC_1_MICROSECOND
= 1,
55 UHC_1_MILLISECOND
= 1000 * UHC_1_MICROSECOND
,
56 UHC_1_SECOND
= 1000 * UHC_1_MILLISECOND
,
59 // UHCI register operation timeout, set by experience
61 UHC_GENERIC_TIMEOUT
= UHC_1_SECOND
,
64 // Wait for force global resume(FGR) complete, refers to
65 // specification[UHCI11-2.1.1]
67 UHC_FORCE_GLOBAL_RESUME_STALL
= 20 * UHC_1_MILLISECOND
,
70 // Wait for roothub port reset and recovery, reset stall
71 // is set by experience, and recovery stall refers to
72 // specification[UHCI11-2.1.1]
74 UHC_ROOT_PORT_RESET_STALL
= 50 * UHC_1_MILLISECOND
,
75 UHC_ROOT_PORT_RECOVERY_STALL
= 10 * UHC_1_MILLISECOND
,
78 // Sync and Async transfer polling interval, set by experience,
79 // and the unit of Async is 100us.
81 UHC_SYNC_POLL_INTERVAL
= 50 * UHC_1_MICROSECOND
,
82 UHC_ASYNC_POLL_INTERVAL
= 50 * 10000UL,
85 // UHC raises TPL to TPL_NOTIFY to serialize all its operations
86 // to protect shared data structures.
88 UHCI_TPL
= TPL_NOTIFY
,
90 USB_HC_DEV_SIGNATURE
= EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')
101 #define UHC_FROM_USB2_HC_PROTO(This) CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)
104 // USB_HC_DEV support the UHCI hardware controller. It schedules
105 // the asynchronous interrupt transfer with the same method as
106 // EHCI: a reversed tree structure. For synchronous interrupt,
107 // control and bulk transfer, it uses three static queue head to
108 // schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is
109 // for LOW speed control transfer, and FsCtrlBulkQh is for FULL
110 // speed control or bulk transfer. This is because FULL speed contrl
111 // or bulk transfer can reclaim the unused bandwidth. Some USB
112 // device requires this bandwidth reclamation capability.
116 EFI_USB2_HC_PROTOCOL Usb2Hc
;
117 EFI_PCI_IO_PROTOCOL
*PciIo
;
118 UINT64 OriginalPciAttributes
;
121 // Schedule data structures
124 UHCI_QH_SW
*SyncIntQh
;
129 // Structures to maintain asynchronus interrupt transfers.
130 // When asynchronous interrutp transfer is unlinked from
131 // the frame list, the hardware may still hold a pointer
132 // to it. To synchronize with hardware, its resoureces are
133 // released in two steps using Recycle and RecycleWait.
134 // Check the asynchronous interrupt management routines.
136 LIST_ENTRY AsyncIntList
;
137 EFI_EVENT AsyncIntMonitor
;
138 UHCI_ASYNC_REQUEST
*Recycle
;
139 UHCI_ASYNC_REQUEST
*RecycleWait
;
143 USBHC_MEM_POOL
*MemPool
;
144 EFI_UNICODE_STRING_TABLE
*CtrlNameTable
;
148 extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding
;
149 extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName
;
150 extern EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2
;