MdeModulePkg UhciPei: Support IoMmu
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciPei / UhcPeim.h
1 /** @file
2 Private Header file for Usb Host Controller PEIM
3
4 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions
8 of the BSD License which accompanies this distribution. The
9 full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _RECOVERY_UHC_H_
18 #define _RECOVERY_UHC_H_
19
20
21 #include <PiPei.h>
22
23 #include <Ppi/UsbController.h>
24 #include <Ppi/UsbHostController.h>
25 #include <Ppi/IoMmu.h>
26 #include <Ppi/EndOfPeiPhase.h>
27
28 #include <Library/DebugLib.h>
29 #include <Library/PeimEntryPoint.h>
30 #include <Library/PeiServicesLib.h>
31 #include <Library/BaseMemoryLib.h>
32 #include <Library/TimerLib.h>
33 #include <Library/IoLib.h>
34 #include <Library/PeiServicesLib.h>
35
36 #define USB_SLOW_SPEED_DEVICE 0x01
37 #define USB_FULL_SPEED_DEVICE 0x02
38
39 //
40 // One memory block uses 16 page
41 //
42 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16
43
44 #define USBCMD 0 /* Command Register Offset 00-01h */
45 #define USBCMD_RS BIT0 /* Run/Stop */
46 #define USBCMD_HCRESET BIT1 /* Host reset */
47 #define USBCMD_GRESET BIT2 /* Global reset */
48 #define USBCMD_EGSM BIT3 /* Global Suspend Mode */
49 #define USBCMD_FGR BIT4 /* Force Global Resume */
50 #define USBCMD_SWDBG BIT5 /* SW Debug mode */
51 #define USBCMD_CF BIT6 /* Config Flag (sw only) */
52 #define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */
53
54 /* Status register */
55 #define USBSTS 2 /* Status Register Offset 02-03h */
56 #define USBSTS_USBINT BIT0 /* Interrupt due to IOC */
57 #define USBSTS_ERROR BIT1 /* Interrupt due to error */
58 #define USBSTS_RD BIT2 /* Resume Detect */
59 #define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */
60 #define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */
61 #define USBSTS_HCH BIT5 /* HC Halted */
62
63 /* Interrupt enable register */
64 #define USBINTR 4 /* Interrupt Enable Register 04-05h */
65 #define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */
66 #define USBINTR_RESUME BIT1 /* Resume interrupt enable */
67 #define USBINTR_IOC BIT2 /* Interrupt On Complete enable */
68 #define USBINTR_SP BIT3 /* Short packet interrupt enable */
69
70 /* Frame Number Register Offset 06-08h */
71 #define USBFRNUM 6
72
73 /* Frame List Base Address Register Offset 08-0Bh */
74 #define USBFLBASEADD 8
75
76 /* Start of Frame Modify Register Offset 0Ch */
77 #define USBSOF 0x0c
78
79 /* USB port status and control registers */
80 #define USBPORTSC1 0x10 /*Port 1 offset 10-11h */
81 #define USBPORTSC2 0x12 /*Port 2 offset 12-13h */
82
83 #define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */
84 #define USBPORTSC_CSC BIT1 /* Connect Status Change */
85 #define USBPORTSC_PED BIT2 /* Port Enable / Disable */
86 #define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */
87 #define USBPORTSC_LSL BIT4 /* Line Status Low bit*/
88 #define USBPORTSC_LSH BIT5 /* Line Status High bit*/
89 #define USBPORTSC_RD BIT6 /* Resume Detect */
90 #define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */
91 #define USBPORTSC_PR BIT9 /* Port Reset */
92 #define USBPORTSC_SUSP BIT12 /* Suspend */
93
94 #define SETUP_PACKET_ID 0x2D
95 #define INPUT_PACKET_ID 0x69
96 #define OUTPUT_PACKET_ID 0xE1
97 #define ERROR_PACKET_ID 0x55
98
99 #define STALL_1_MICRO_SECOND 1
100 #define STALL_1_MILLI_SECOND 1000
101
102
103 #pragma pack(1)
104
105 typedef struct {
106 UINT32 FrameListPtrTerminate : 1;
107 UINT32 FrameListPtrQSelect : 1;
108 UINT32 FrameListRsvd : 2;
109 UINT32 FrameListPtr : 28;
110 } FRAMELIST_ENTRY;
111
112 typedef struct {
113 UINT32 QHHorizontalTerminate : 1;
114 UINT32 QHHorizontalQSelect : 1;
115 UINT32 QHHorizontalRsvd : 2;
116 UINT32 QHHorizontalPtr : 28;
117 UINT32 QHVerticalTerminate : 1;
118 UINT32 QHVerticalQSelect : 1;
119 UINT32 QHVerticalRsvd : 2;
120 UINT32 QHVerticalPtr : 28;
121 } QUEUE_HEAD;
122
123 typedef struct {
124 QUEUE_HEAD QueueHead;
125 UINT32 Reserved1;
126 UINT32 Reserved2;
127 VOID *PtrNext;
128 VOID *PtrDown;
129 VOID *Reserved3;
130 UINT32 Reserved4;
131 } QH_STRUCT;
132
133 typedef struct {
134 UINT32 TDLinkPtrTerminate : 1;
135 UINT32 TDLinkPtrQSelect : 1;
136 UINT32 TDLinkPtrDepthSelect : 1;
137 UINT32 TDLinkPtrRsvd : 1;
138 UINT32 TDLinkPtr : 28;
139 UINT32 TDStatusActualLength : 11;
140 UINT32 TDStatusRsvd : 5;
141 UINT32 TDStatus : 8;
142 UINT32 TDStatusIOC : 1;
143 UINT32 TDStatusIOS : 1;
144 UINT32 TDStatusLS : 1;
145 UINT32 TDStatusErr : 2;
146 UINT32 TDStatusSPD : 1;
147 UINT32 TDStatusRsvd2 : 2;
148 UINT32 TDTokenPID : 8;
149 UINT32 TDTokenDevAddr : 7;
150 UINT32 TDTokenEndPt : 4;
151 UINT32 TDTokenDataToggle : 1;
152 UINT32 TDTokenRsvd : 1;
153 UINT32 TDTokenMaxLen : 11;
154 UINT32 TDBufferPtr;
155 } TD;
156
157 typedef struct {
158 TD TDData;
159 UINT8 *PtrTDBuffer;
160 VOID *PtrNextTD;
161 VOID *PtrNextQH;
162 UINT16 TDBufferLength;
163 UINT16 Reserved;
164 } TD_STRUCT;
165
166 #pragma pack()
167
168 typedef struct _MEMORY_MANAGE_HEADER MEMORY_MANAGE_HEADER;
169
170 struct _MEMORY_MANAGE_HEADER {
171 UINT8 *BitArrayPtr;
172 UINTN BitArraySizeInBytes;
173 UINT8 *MemoryBlockPtr;
174 UINTN MemoryBlockSizeInBytes;
175 MEMORY_MANAGE_HEADER *Next;
176 };
177
178 #define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')
179 typedef struct {
180 UINTN Signature;
181 PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;
182 EDKII_IOMMU_PPI *IoMmu;
183 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
184 //
185 // EndOfPei callback is used to stop the UHC DMA operation
186 // after exit PEI phase.
187 //
188 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
189
190 UINT32 UsbHostControllerBaseAddress;
191 FRAMELIST_ENTRY *FrameListEntry;
192 QH_STRUCT *ConfigQH;
193 QH_STRUCT *BulkQH;
194 //
195 // Header1 used for QH,TD memory blocks management
196 //
197 MEMORY_MANAGE_HEADER *Header1;
198
199 } USB_UHC_DEV;
200
201 #define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)
202 #define PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY(a) CR (a, USB_UHC_DEV, EndOfPeiNotifyList, USB_UHC_DEV_SIGNATURE)
203
204 /**
205 Submits control transfer to a target USB device.
206
207 @param PeiServices The pointer of EFI_PEI_SERVICES.
208 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
209 @param DeviceAddress The target device address.
210 @param DeviceSpeed Target device speed.
211 @param MaximumPacketLength Maximum packet size the default control transfer
212 endpoint is capable of sending or receiving.
213 @param Request USB device request to send.
214 @param TransferDirection Specifies the data direction for the data stage.
215 @param Data Data buffer to be transmitted or received from USB device.
216 @param DataLength The size (in bytes) of the data buffer.
217 @param TimeOut Indicates the maximum timeout, in millisecond.
218 @param TransferResult Return the result of this control transfer.
219
220 @retval EFI_SUCCESS Transfer was completed successfully.
221 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resources.
222 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
223 @retval EFI_TIMEOUT Transfer failed due to timeout.
224 @retval EFI_DEVICE_ERROR Transfer failed due to host controller or device error.
225
226 **/
227 EFI_STATUS
228 EFIAPI
229 UhcControlTransfer (
230 IN EFI_PEI_SERVICES **PeiServices,
231 IN PEI_USB_HOST_CONTROLLER_PPI * This,
232 IN UINT8 DeviceAddress,
233 IN UINT8 DeviceSpeed,
234 IN UINT8 MaximumPacketLength,
235 IN EFI_USB_DEVICE_REQUEST * Request,
236 IN EFI_USB_DATA_DIRECTION TransferDirection,
237 IN OUT VOID *Data OPTIONAL,
238 IN OUT UINTN *DataLength OPTIONAL,
239 IN UINTN TimeOut,
240 OUT UINT32 *TransferResult
241 );
242
243 /**
244 Submits bulk transfer to a bulk endpoint of a USB device.
245
246 @param PeiServices The pointer of EFI_PEI_SERVICES.
247 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
248 @param DeviceAddress Target device address.
249 @param EndPointAddress Endpoint number and its direction in bit 7.
250 @param MaximumPacketLength Maximum packet size the endpoint is capable of
251 sending or receiving.
252 @param Data Array of pointers to the buffers of data to transmit
253 from or receive into.
254 @param DataLength The lenght of the data buffer.
255 @param DataToggle On input, the initial data toggle for the transfer;
256 On output, it is updated to to next data toggle to use of
257 the subsequent bulk transfer.
258 @param TimeOut Indicates the maximum time, in millisecond, which the
259 transfer is allowed to complete.
260 @param TransferResult A pointer to the detailed result information of the
261 bulk transfer.
262
263 @retval EFI_SUCCESS The transfer was completed successfully.
264 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
265 @retval EFI_INVALID_PARAMETER Parameters are invalid.
266 @retval EFI_TIMEOUT The transfer failed due to timeout.
267 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
268
269 **/
270 EFI_STATUS
271 EFIAPI
272 UhcBulkTransfer (
273 IN EFI_PEI_SERVICES **PeiServices,
274 IN PEI_USB_HOST_CONTROLLER_PPI *This,
275 IN UINT8 DeviceAddress,
276 IN UINT8 EndPointAddress,
277 IN UINT8 MaximumPacketLength,
278 IN OUT VOID *Data,
279 IN OUT UINTN *DataLength,
280 IN OUT UINT8 *DataToggle,
281 IN UINTN TimeOut,
282 OUT UINT32 *TransferResult
283 );
284
285 /**
286 Retrieves the number of root hub ports.
287
288 @param[in] PeiServices The pointer to the PEI Services Table.
289 @param[in] This The pointer to this instance of the
290 PEI_USB_HOST_CONTROLLER_PPI.
291 @param[out] PortNumber The pointer to the number of the root hub ports.
292
293 @retval EFI_SUCCESS The port number was retrieved successfully.
294 @retval EFI_INVALID_PARAMETER PortNumber is NULL.
295
296 **/
297 EFI_STATUS
298 EFIAPI
299 UhcGetRootHubPortNumber (
300 IN EFI_PEI_SERVICES **PeiServices,
301 IN PEI_USB_HOST_CONTROLLER_PPI *This,
302 OUT UINT8 *PortNumber
303 );
304
305 /**
306 Retrieves the current status of a USB root hub port.
307
308 @param PeiServices The pointer of EFI_PEI_SERVICES.
309 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
310 @param PortNumber The root hub port to retrieve the state from.
311 @param PortStatus Variable to receive the port state.
312
313 @retval EFI_SUCCESS The status of the USB root hub port specified.
314 by PortNumber was returned in PortStatus.
315 @retval EFI_INVALID_PARAMETER PortNumber is invalid.
316
317 **/
318 EFI_STATUS
319 EFIAPI
320 UhcGetRootHubPortStatus (
321 IN EFI_PEI_SERVICES **PeiServices,
322 IN PEI_USB_HOST_CONTROLLER_PPI *This,
323 IN UINT8 PortNumber,
324 OUT EFI_USB_PORT_STATUS *PortStatus
325 );
326
327 /**
328 Sets a feature for the specified root hub port.
329
330 @param PeiServices The pointer of EFI_PEI_SERVICES
331 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI
332 @param PortNumber Root hub port to set.
333 @param PortFeature Feature to set.
334
335 @retval EFI_SUCCESS The feature specified by PortFeature was set.
336 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
337 @retval EFI_TIMEOUT The time out occurred.
338
339 **/
340 EFI_STATUS
341 EFIAPI
342 UhcSetRootHubPortFeature (
343 IN EFI_PEI_SERVICES **PeiServices,
344 IN PEI_USB_HOST_CONTROLLER_PPI *This,
345 IN UINT8 PortNumber,
346 IN EFI_USB_PORT_FEATURE PortFeature
347 );
348
349 /**
350 Clears a feature for the specified root hub port.
351
352 @param PeiServices The pointer of EFI_PEI_SERVICES.
353 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
354 @param PortNumber Specifies the root hub port whose feature
355 is requested to be cleared.
356 @param PortFeature Indicates the feature selector associated with the
357 feature clear request.
358
359 @retval EFI_SUCCESS The feature specified by PortFeature was cleared
360 for the USB root hub port specified by PortNumber.
361 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
362
363 **/
364 EFI_STATUS
365 EFIAPI
366 UhcClearRootHubPortFeature (
367 IN EFI_PEI_SERVICES **PeiServices,
368 IN PEI_USB_HOST_CONTROLLER_PPI *This,
369 IN UINT8 PortNumber,
370 IN EFI_USB_PORT_FEATURE PortFeature
371 );
372
373 /**
374 Initialize UHCI.
375
376 @param UhcDev UHCI Device.
377
378 @retval EFI_SUCCESS UHCI successfully initialized.
379 @retval EFI_OUT_OF_RESOURCES Resource can not be allocated.
380
381 **/
382 EFI_STATUS
383 InitializeUsbHC (
384 IN USB_UHC_DEV *UhcDev
385 );
386
387 /**
388 Create Frame List Structure.
389
390 @param UhcDev UHCI device.
391
392 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
393 @retval EFI_SUCCESS Success.
394
395 **/
396 EFI_STATUS
397 CreateFrameList (
398 USB_UHC_DEV *UhcDev
399 );
400
401 /**
402 Read a 16bit width data from Uhc HC IO space register.
403
404 @param UhcDev The UHCI device.
405 @param Port The IO space address of the register.
406
407 @retval the register content read.
408
409 **/
410 UINT16
411 USBReadPortW (
412 IN USB_UHC_DEV *UhcDev,
413 IN UINT32 Port
414 );
415
416 /**
417 Write a 16bit width data into Uhc HC IO space register.
418
419 @param UhcDev The UHCI device.
420 @param Port The IO space address of the register.
421 @param Data The data written into the register.
422
423 **/
424 VOID
425 USBWritePortW (
426 IN USB_UHC_DEV *UhcDev,
427 IN UINT32 Port,
428 IN UINT16 Data
429 );
430
431 /**
432 Write a 32bit width data into Uhc HC IO space register.
433
434 @param UhcDev The UHCI device.
435 @param Port The IO space address of the register.
436 @param Data The data written into the register.
437
438 **/
439 VOID
440 USBWritePortDW (
441 IN USB_UHC_DEV *UhcDev,
442 IN UINT32 Port,
443 IN UINT32 Data
444 );
445
446 /**
447 Clear the content of UHCI's Status Register.
448
449 @param UhcDev The UHCI device.
450 @param StatusAddr The IO space address of the register.
451
452 **/
453 VOID
454 ClearStatusReg (
455 IN USB_UHC_DEV *UhcDev,
456 IN UINT32 StatusAddr
457 );
458
459 /**
460 Check whether the host controller operates well.
461
462 @param UhcDev The UHCI device.
463 @param StatusRegAddr The io address of status register.
464
465 @retval TRUE Host controller is working.
466 @retval FALSE Host controller is halted or system error.
467
468 **/
469 BOOLEAN
470 IsStatusOK (
471 IN USB_UHC_DEV *UhcDev,
472 IN UINT32 StatusRegAddr
473 );
474
475 /**
476 Get Current Frame Number.
477
478 @param UhcDev The UHCI device.
479 @param FrameNumberAddr The address of frame list register.
480
481 @retval The content of the frame list register.
482
483 **/
484 UINT16
485 GetCurrentFrameNumber (
486 IN USB_UHC_DEV *UhcDev,
487 IN UINT32 FrameNumberAddr
488 );
489
490 /**
491 Set Frame List Base Address.
492
493 @param UhcDev The UHCI device.
494 @param FrameListRegAddr The address of frame list register.
495 @param Addr The address of frame list table.
496
497 **/
498 VOID
499 SetFrameListBaseAddress (
500 IN USB_UHC_DEV *UhcDev,
501 IN UINT32 FrameListRegAddr,
502 IN UINT32 Addr
503 );
504
505 /**
506 Create QH and initialize.
507
508 @param UhcDev The UHCI device.
509 @param PtrQH Place to store QH_STRUCT pointer.
510
511 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
512 @retval EFI_SUCCESS Success.
513
514 **/
515 EFI_STATUS
516 CreateQH (
517 IN USB_UHC_DEV *UhcDev,
518 OUT QH_STRUCT **PtrQH
519 );
520
521 /**
522 Set the horizontal link pointer in QH.
523
524 @param PtrQH Place to store QH_STRUCT pointer.
525 @param PtrNext Place to the next QH_STRUCT.
526
527 **/
528 VOID
529 SetQHHorizontalLinkPtr (
530 IN QH_STRUCT *PtrQH,
531 IN VOID *PtrNext
532 );
533
534 /**
535 Get the horizontal link pointer in QH.
536
537 @param PtrQH Place to store QH_STRUCT pointer.
538
539 @retval The horizontal link pointer in QH.
540
541 **/
542 VOID *
543 GetQHHorizontalLinkPtr (
544 IN QH_STRUCT *PtrQH
545 );
546
547 /**
548 Set a QH or TD horizontally to be connected with a specific QH.
549
550 @param PtrQH Place to store QH_STRUCT pointer.
551 @param IsQH Specify QH or TD is connected.
552
553 **/
554 VOID
555 SetQHHorizontalQHorTDSelect (
556 IN QH_STRUCT *PtrQH,
557 IN BOOLEAN IsQH
558 );
559
560 /**
561 Set the horizontal validor bit in QH.
562
563 @param PtrQH Place to store QH_STRUCT pointer.
564 @param IsValid Specify the horizontal linker is valid or not.
565
566 **/
567 VOID
568 SetQHHorizontalValidorInvalid (
569 IN QH_STRUCT *PtrQH,
570 IN BOOLEAN IsValid
571 );
572
573 /**
574 Set the vertical link pointer in QH.
575
576 @param PtrQH Place to store QH_STRUCT pointer.
577 @param PtrNext Place to the next QH_STRUCT.
578
579 **/
580 VOID
581 SetQHVerticalLinkPtr (
582 IN QH_STRUCT *PtrQH,
583 IN VOID *PtrNext
584 );
585
586 /**
587 Set a QH or TD vertically to be connected with a specific QH.
588
589 @param PtrQH Place to store QH_STRUCT pointer.
590 @param IsQH Specify QH or TD is connected.
591
592 **/
593 VOID
594 SetQHVerticalQHorTDSelect (
595 IN QH_STRUCT *PtrQH,
596 IN BOOLEAN IsQH
597 );
598
599 /**
600 Set the vertical validor bit in QH.
601
602 @param PtrQH Place to store QH_STRUCT pointer.
603 @param IsValid Specify the vertical linker is valid or not.
604
605 **/
606 VOID
607 SetQHVerticalValidorInvalid (
608 IN QH_STRUCT *PtrQH,
609 IN BOOLEAN IsValid
610 );
611
612 /**
613 Get the vertical validor bit in QH.
614
615 @param PtrQH Place to store QH_STRUCT pointer.
616
617 @retval The vertical linker is valid or not.
618
619 **/
620 BOOLEAN
621 GetQHHorizontalValidorInvalid (
622 IN QH_STRUCT *PtrQH
623 );
624
625 /**
626 Allocate TD or QH Struct.
627
628 @param UhcDev The UHCI device.
629 @param Size The size of allocation.
630 @param PtrStruct Place to store TD_STRUCT pointer.
631
632 @return EFI_SUCCESS Allocate successfully.
633 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
634
635 **/
636 EFI_STATUS
637 AllocateTDorQHStruct (
638 IN USB_UHC_DEV *UhcDev,
639 IN UINT32 Size,
640 OUT VOID **PtrStruct
641 );
642
643 /**
644 Create a TD Struct.
645
646 @param UhcDev The UHCI device.
647 @param PtrTD Place to store TD_STRUCT pointer.
648
649 @return EFI_SUCCESS Allocate successfully.
650 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
651
652 **/
653 EFI_STATUS
654 CreateTD (
655 IN USB_UHC_DEV *UhcDev,
656 OUT TD_STRUCT **PtrTD
657 );
658
659 /**
660 Generate Setup Stage TD.
661
662 @param UhcDev The UHCI device.
663 @param DevAddr Device address.
664 @param Endpoint Endpoint number.
665 @param DeviceSpeed Device Speed.
666 @param DevRequest CPU memory address of request structure buffer to transfer.
667 @param RequestPhy PCI memory address of request structure buffer to transfer.
668 @param RequestLen Request length.
669 @param PtrTD TD_STRUCT generated.
670
671 @return EFI_SUCCESS Generate setup stage TD successfully.
672 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
673
674 **/
675 EFI_STATUS
676 GenSetupStageTD (
677 IN USB_UHC_DEV *UhcDev,
678 IN UINT8 DevAddr,
679 IN UINT8 Endpoint,
680 IN UINT8 DeviceSpeed,
681 IN UINT8 *DevRequest,
682 IN UINT8 *RequestPhy,
683 IN UINT8 RequestLen,
684 OUT TD_STRUCT **PtrTD
685 );
686
687 /**
688 Generate Data Stage TD.
689
690 @param UhcDev The UHCI device.
691 @param DevAddr Device address.
692 @param Endpoint Endpoint number.
693 @param PtrData CPU memory address of user data buffer to transfer.
694 @param DataPhy PCI memory address of user data buffer to transfer.
695 @param Len Data length.
696 @param PktID PacketID.
697 @param Toggle Data toggle value.
698 @param DeviceSpeed Device Speed.
699 @param PtrTD TD_STRUCT generated.
700
701 @return EFI_SUCCESS Generate data stage TD successfully.
702 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
703
704 **/
705 EFI_STATUS
706 GenDataTD (
707 IN USB_UHC_DEV *UhcDev,
708 IN UINT8 DevAddr,
709 IN UINT8 Endpoint,
710 IN UINT8 *PtrData,
711 IN UINT8 *DataPhy,
712 IN UINT8 Len,
713 IN UINT8 PktID,
714 IN UINT8 Toggle,
715 IN UINT8 DeviceSpeed,
716 OUT TD_STRUCT **PtrTD
717 );
718
719 /**
720 Generate Status Stage TD.
721
722 @param UhcDev The UHCI device.
723 @param DevAddr Device address.
724 @param Endpoint Endpoint number.
725 @param PktID PacketID.
726 @param DeviceSpeed Device Speed.
727 @param PtrTD TD_STRUCT generated.
728
729 @return EFI_SUCCESS Generate status stage TD successfully.
730 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
731
732 **/
733 EFI_STATUS
734 CreateStatusTD (
735 IN USB_UHC_DEV *UhcDev,
736 IN UINT8 DevAddr,
737 IN UINT8 Endpoint,
738 IN UINT8 PktID,
739 IN UINT8 DeviceSpeed,
740 OUT TD_STRUCT **PtrTD
741 );
742
743 /**
744 Set the link pointer validor bit in TD.
745
746 @param PtrTDStruct Place to store TD_STRUCT pointer.
747 @param IsValid Specify the linker pointer is valid or not.
748
749 **/
750 VOID
751 SetTDLinkPtrValidorInvalid (
752 IN TD_STRUCT *PtrTDStruct,
753 IN BOOLEAN IsValid
754 );
755
756 /**
757 Set the Link Pointer pointing to a QH or TD.
758
759 @param PtrTDStruct Place to store TD_STRUCT pointer.
760 @param IsQH Specify QH or TD is connected.
761
762 **/
763 VOID
764 SetTDLinkPtrQHorTDSelect (
765 IN TD_STRUCT *PtrTDStruct,
766 IN BOOLEAN IsQH
767 );
768
769 /**
770 Set the traverse is depth-first or breadth-first.
771
772 @param PtrTDStruct Place to store TD_STRUCT pointer.
773 @param IsDepth Specify the traverse is depth-first or breadth-first.
774
775 **/
776 VOID
777 SetTDLinkPtrDepthorBreadth (
778 IN TD_STRUCT *PtrTDStruct,
779 IN BOOLEAN IsDepth
780 );
781
782 /**
783 Set TD Link Pointer in TD.
784
785 @param PtrTDStruct Place to store TD_STRUCT pointer.
786 @param PtrNext Place to the next TD_STRUCT.
787
788 **/
789 VOID
790 SetTDLinkPtr (
791 IN TD_STRUCT *PtrTDStruct,
792 IN VOID *PtrNext
793 );
794
795 /**
796 Get TD Link Pointer.
797
798 @param PtrTDStruct Place to store TD_STRUCT pointer.
799
800 @retval Get TD Link Pointer in TD.
801
802 **/
803 VOID*
804 GetTDLinkPtr (
805 IN TD_STRUCT *PtrTDStruct
806 );
807
808 /**
809 Get the information about whether the Link Pointer field pointing to
810 a QH or a TD.
811
812 @param PtrTDStruct Place to store TD_STRUCT pointer.
813
814 @retval whether the Link Pointer field pointing to a QH or a TD.
815
816 **/
817 BOOLEAN
818 IsTDLinkPtrQHOrTD (
819 IN TD_STRUCT *PtrTDStruct
820 );
821
822 /**
823 Enable/Disable short packet detection mechanism.
824
825 @param PtrTDStruct Place to store TD_STRUCT pointer.
826 @param IsEnable Enable or disable short packet detection mechanism.
827
828 **/
829 VOID
830 EnableorDisableTDShortPacket (
831 IN TD_STRUCT *PtrTDStruct,
832 IN BOOLEAN IsEnable
833 );
834
835 /**
836 Set the max error counter in TD.
837
838 @param PtrTDStruct Place to store TD_STRUCT pointer.
839 @param MaxErrors The number of allowable error.
840
841 **/
842 VOID
843 SetTDControlErrorCounter (
844 IN TD_STRUCT *PtrTDStruct,
845 IN UINT8 MaxErrors
846 );
847
848 /**
849 Set the TD is targeting a low-speed device or not.
850
851 @param PtrTDStruct Place to store TD_STRUCT pointer.
852 @param IsLowSpeedDevice Whether The device is low-speed.
853
854 **/
855 VOID
856 SetTDLoworFullSpeedDevice (
857 IN TD_STRUCT *PtrTDStruct,
858 IN BOOLEAN IsLowSpeedDevice
859 );
860
861 /**
862 Set the TD is isochronous transfer type or not.
863
864 @param PtrTDStruct Place to store TD_STRUCT pointer.
865 @param IsIsochronous Whether the transaction isochronous transfer type.
866
867 **/
868 VOID
869 SetTDControlIsochronousorNot (
870 IN TD_STRUCT *PtrTDStruct,
871 IN BOOLEAN IsIsochronous
872 );
873
874 /**
875 Set if UCHI should issue an interrupt on completion of the frame
876 in which this TD is executed
877
878 @param PtrTDStruct Place to store TD_STRUCT pointer.
879 @param IsSet Whether HC should issue an interrupt on completion.
880
881 **/
882 VOID
883 SetorClearTDControlIOC (
884 IN TD_STRUCT *PtrTDStruct,
885 IN BOOLEAN IsSet
886 );
887
888 /**
889 Set if the TD is active and can be executed.
890
891 @param PtrTDStruct Place to store TD_STRUCT pointer.
892 @param IsActive Whether the TD is active and can be executed.
893
894 **/
895 VOID
896 SetTDStatusActiveorInactive (
897 IN TD_STRUCT *PtrTDStruct,
898 IN BOOLEAN IsActive
899 );
900
901 /**
902 Specifies the maximum number of data bytes allowed for the transfer.
903
904 @param PtrTDStruct Place to store TD_STRUCT pointer.
905 @param MaxLen The maximum number of data bytes allowed.
906
907 @retval The allowed maximum number of data.
908 **/
909 UINT16
910 SetTDTokenMaxLength (
911 IN TD_STRUCT *PtrTDStruct,
912 IN UINT16 MaxLen
913 );
914
915 /**
916 Set the data toggle bit to DATA1.
917
918 @param PtrTDStruct Place to store TD_STRUCT pointer.
919
920 **/
921 VOID
922 SetTDTokenDataToggle1 (
923 IN TD_STRUCT *PtrTDStruct
924 );
925
926 /**
927 Set the data toggle bit to DATA0.
928
929 @param PtrTDStruct Place to store TD_STRUCT pointer.
930
931 **/
932 VOID
933 SetTDTokenDataToggle0 (
934 IN TD_STRUCT *PtrTDStruct
935 );
936
937 /**
938 Set EndPoint Number the TD is targeting at.
939
940 @param PtrTDStruct Place to store TD_STRUCT pointer.
941 @param EndPoint The Endport number of the target.
942
943 **/
944 VOID
945 SetTDTokenEndPoint (
946 IN TD_STRUCT *PtrTDStruct,
947 IN UINTN EndPoint
948 );
949
950 /**
951 Set Device Address the TD is targeting at.
952
953 @param PtrTDStruct Place to store TD_STRUCT pointer.
954 @param DevAddr The Device Address of the target.
955
956 **/
957 VOID
958 SetTDTokenDeviceAddress (
959 IN TD_STRUCT *PtrTDStruct,
960 IN UINTN DevAddr
961 );
962
963 /**
964 Set Packet Identification the TD is targeting at.
965
966 @param PtrTDStruct Place to store TD_STRUCT pointer.
967 @param PacketID The Packet Identification of the target.
968
969 **/
970 VOID
971 SetTDTokenPacketID (
972 IN TD_STRUCT *PtrTDStruct,
973 IN UINT8 PacketID
974 );
975
976 /**
977 Set the beginning address of the data buffer that will be used
978 during the transaction.
979
980 @param PtrTDStruct Place to store TD_STRUCT pointer.
981
982 **/
983 VOID
984 SetTDDataBuffer (
985 IN TD_STRUCT *PtrTDStruct
986 );
987
988 /**
989 Detect whether the TD is active.
990
991 @param PtrTDStruct Place to store TD_STRUCT pointer.
992
993 @retval The TD is active or not.
994
995 **/
996 BOOLEAN
997 IsTDStatusActive (
998 IN TD_STRUCT *PtrTDStruct
999 );
1000
1001 /**
1002 Detect whether the TD is stalled.
1003
1004 @param PtrTDStruct Place to store TD_STRUCT pointer.
1005
1006 @retval The TD is stalled or not.
1007
1008 **/
1009 BOOLEAN
1010 IsTDStatusStalled (
1011 IN TD_STRUCT *PtrTDStruct
1012 );
1013
1014 /**
1015 Detect whether Data Buffer Error is happened.
1016
1017 @param PtrTDStruct Place to store TD_STRUCT pointer.
1018
1019 @retval The Data Buffer Error is happened or not.
1020
1021 **/
1022 BOOLEAN
1023 IsTDStatusBufferError (
1024 IN TD_STRUCT *PtrTDStruct
1025 );
1026
1027 /**
1028 Detect whether Babble Error is happened.
1029
1030 @param PtrTDStruct Place to store TD_STRUCT pointer.
1031
1032 @retval The Babble Error is happened or not.
1033
1034 **/
1035 BOOLEAN
1036 IsTDStatusBabbleError (
1037 IN TD_STRUCT *PtrTDStruct
1038 );
1039
1040 /**
1041 Detect whether NAK is received.
1042
1043 @param PtrTDStruct Place to store TD_STRUCT pointer.
1044
1045 @retval The NAK is received or not.
1046
1047 **/
1048 BOOLEAN
1049 IsTDStatusNAKReceived (
1050 IN TD_STRUCT *PtrTDStruct
1051 );
1052
1053 /**
1054 Detect whether CRC/Time Out Error is encountered.
1055
1056 @param PtrTDStruct Place to store TD_STRUCT pointer.
1057
1058 @retval The CRC/Time Out Error is encountered or not.
1059
1060 **/
1061 BOOLEAN
1062 IsTDStatusCRCTimeOutError (
1063 IN TD_STRUCT *PtrTDStruct
1064 );
1065
1066 /**
1067 Detect whether Bitstuff Error is received.
1068
1069 @param PtrTDStruct Place to store TD_STRUCT pointer.
1070
1071 @retval The Bitstuff Error is received or not.
1072
1073 **/
1074 BOOLEAN
1075 IsTDStatusBitStuffError (
1076 IN TD_STRUCT *PtrTDStruct
1077 );
1078
1079 /**
1080 Retrieve the actual number of bytes that were tansferred.
1081
1082 @param PtrTDStruct Place to store TD_STRUCT pointer.
1083
1084 @retval The actual number of bytes that were tansferred.
1085
1086 **/
1087 UINT16
1088 GetTDStatusActualLength (
1089 IN TD_STRUCT *PtrTDStruct
1090 );
1091
1092 /**
1093 Retrieve the information of whether the Link Pointer field is valid or not.
1094
1095 @param PtrTDStruct Place to store TD_STRUCT pointer.
1096
1097 @retval The linker pointer field is valid or not.
1098
1099 **/
1100 BOOLEAN
1101 GetTDLinkPtrValidorInvalid (
1102 IN TD_STRUCT *PtrTDStruct
1103 );
1104
1105 /**
1106 Count TD Number from PtrFirstTD.
1107
1108 @param PtrFirstTD Place to store TD_STRUCT pointer.
1109
1110 @retval The queued TDs number.
1111
1112 **/
1113 UINTN
1114 CountTDsNumber (
1115 IN TD_STRUCT *PtrFirstTD
1116 );
1117
1118 /**
1119 Link TD To QH.
1120
1121 @param PtrQH Place to store QH_STRUCT pointer.
1122 @param PtrTD Place to store TD_STRUCT pointer.
1123
1124 **/
1125 VOID
1126 LinkTDToQH (
1127 IN QH_STRUCT *PtrQH,
1128 IN TD_STRUCT *PtrTD
1129 );
1130
1131 /**
1132 Link TD To TD.
1133
1134 @param PtrPreTD Place to store TD_STRUCT pointer.
1135 @param PtrTD Place to store TD_STRUCT pointer.
1136
1137 **/
1138 VOID
1139 LinkTDToTD (
1140 IN TD_STRUCT *PtrPreTD,
1141 IN TD_STRUCT *PtrTD
1142 );
1143
1144 /**
1145 Execute Control Transfer.
1146
1147 @param UhcDev The UCHI device.
1148 @param PtrTD A pointer to TD_STRUCT data.
1149 @param ActualLen Actual transfer Length.
1150 @param TimeOut TimeOut value.
1151 @param TransferResult Transfer Result.
1152
1153 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1154 @return EFI_TIMEOUT The transfer failed due to time out.
1155 @return EFI_SUCCESS The transfer finished OK.
1156
1157 **/
1158 EFI_STATUS
1159 ExecuteControlTransfer (
1160 IN USB_UHC_DEV *UhcDev,
1161 IN TD_STRUCT *PtrTD,
1162 OUT UINTN *ActualLen,
1163 IN UINTN TimeOut,
1164 OUT UINT32 *TransferResult
1165 );
1166
1167 /**
1168 Execute Bulk Transfer.
1169
1170 @param UhcDev The UCHI device.
1171 @param PtrTD A pointer to TD_STRUCT data.
1172 @param ActualLen Actual transfer Length.
1173 @param DataToggle DataToggle value.
1174 @param TimeOut TimeOut value.
1175 @param TransferResult Transfer Result.
1176
1177 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1178 @return EFI_TIMEOUT The transfer failed due to time out.
1179 @return EFI_SUCCESS The transfer finished OK.
1180
1181 **/
1182 EFI_STATUS
1183 ExecBulkTransfer (
1184 IN USB_UHC_DEV *UhcDev,
1185 IN TD_STRUCT *PtrTD,
1186 IN OUT UINTN *ActualLen,
1187 IN UINT8 *DataToggle,
1188 IN UINTN TimeOut,
1189 OUT UINT32 *TransferResult
1190 );
1191
1192 /**
1193 Delete Queued TDs.
1194
1195 @param UhcDev The UCHI device.
1196 @param PtrFirstTD Place to store TD_STRUCT pointer.
1197
1198 **/
1199 VOID
1200 DeleteQueuedTDs (
1201 IN USB_UHC_DEV *UhcDev,
1202 IN TD_STRUCT *PtrFirstTD
1203 );
1204
1205 /**
1206 Check TDs Results.
1207
1208 @param PtrTD A pointer to TD_STRUCT data.
1209 @param Result The result to return.
1210 @param ErrTDPos The Error TD position.
1211 @param ActualTransferSize Actual transfer size.
1212
1213 @retval The TD is executed successfully or not.
1214
1215 **/
1216 BOOLEAN
1217 CheckTDsResults (
1218 IN TD_STRUCT *PtrTD,
1219 OUT UINT32 *Result,
1220 OUT UINTN *ErrTDPos,
1221 OUT UINTN *ActualTransferSize
1222 );
1223
1224 /**
1225 Create Memory Block.
1226
1227 @param UhcDev The UCHI device.
1228 @param MemoryHeader The Pointer to allocated memory block.
1229 @param MemoryBlockSizeInPages The page size of memory block to be allocated.
1230
1231 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1232 @retval EFI_SUCCESS Success.
1233
1234 **/
1235 EFI_STATUS
1236 CreateMemoryBlock (
1237 IN USB_UHC_DEV *UhcDev,
1238 OUT MEMORY_MANAGE_HEADER **MemoryHeader,
1239 IN UINTN MemoryBlockSizeInPages
1240 );
1241
1242 /**
1243 Initialize UHCI memory management.
1244
1245 @param UhcDev The UCHI device.
1246
1247 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1248 @retval EFI_SUCCESS Success.
1249
1250 **/
1251 EFI_STATUS
1252 InitializeMemoryManagement (
1253 IN USB_UHC_DEV *UhcDev
1254 );
1255
1256 /**
1257 Initialize UHCI memory management.
1258
1259 @param UhcDev The UCHI device.
1260 @param Pool Buffer pointer to store the buffer pointer.
1261 @param AllocSize The size of the pool to be allocated.
1262
1263 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1264 @retval EFI_SUCCESS Success.
1265
1266 **/
1267 EFI_STATUS
1268 UhcAllocatePool (
1269 IN USB_UHC_DEV *UhcDev,
1270 OUT UINT8 **Pool,
1271 IN UINTN AllocSize
1272 );
1273
1274 /**
1275 Alloc Memory In MemoryBlock.
1276
1277 @param MemoryHeader The pointer to memory manage header.
1278 @param Pool Buffer pointer to store the buffer pointer.
1279 @param NumberOfMemoryUnit The size of the pool to be allocated.
1280
1281 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1282 @retval EFI_SUCCESS Success.
1283
1284 **/
1285 EFI_STATUS
1286 AllocMemInMemoryBlock (
1287 IN MEMORY_MANAGE_HEADER *MemoryHeader,
1288 OUT VOID **Pool,
1289 IN UINTN NumberOfMemoryUnit
1290 );
1291
1292 /**
1293 Uhci Free Pool.
1294
1295 @param UhcDev The UHCI device.
1296 @param Pool A pointer to store the buffer address.
1297 @param AllocSize The size of the pool to be freed.
1298
1299 **/
1300 VOID
1301 UhcFreePool (
1302 IN USB_UHC_DEV *UhcDev,
1303 IN UINT8 *Pool,
1304 IN UINTN AllocSize
1305 );
1306
1307 /**
1308 Insert a new memory header into list.
1309
1310 @param MemoryHeader A pointer to the memory header list.
1311 @param NewMemoryHeader A new memory header to be inserted into the list.
1312
1313 **/
1314 VOID
1315 InsertMemoryHeaderToList (
1316 IN MEMORY_MANAGE_HEADER *MemoryHeader,
1317 IN MEMORY_MANAGE_HEADER *NewMemoryHeader
1318 );
1319
1320 /**
1321 Judge the memory block in the memory header is empty or not.
1322
1323 @param MemoryHeaderPtr A pointer to the memory header list.
1324
1325 @retval Whether the memory block in the memory header is empty or not.
1326
1327 **/
1328 BOOLEAN
1329 IsMemoryBlockEmptied (
1330 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr
1331 );
1332
1333 /**
1334 remove a memory header from list.
1335
1336 @param FirstMemoryHeader A pointer to the memory header list.
1337 @param FreeMemoryHeader A memory header to be removed into the list.
1338
1339 **/
1340 VOID
1341 DelinkMemoryBlock (
1342 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,
1343 IN MEMORY_MANAGE_HEADER *FreeMemoryHeader
1344 );
1345
1346 /**
1347 Map address of request structure buffer.
1348
1349 @param Uhc The UHCI device.
1350 @param Request The user request buffer.
1351 @param MappedAddr Mapped address of request.
1352 @param Map Identificaion of this mapping to return.
1353
1354 @return EFI_SUCCESS Success.
1355 @return EFI_DEVICE_ERROR Fail to map the user request.
1356
1357 **/
1358 EFI_STATUS
1359 UhciMapUserRequest (
1360 IN USB_UHC_DEV *Uhc,
1361 IN OUT VOID *Request,
1362 OUT UINT8 **MappedAddr,
1363 OUT VOID **Map
1364 );
1365
1366 /**
1367 Map address of user data buffer.
1368
1369 @param Uhc The UHCI device.
1370 @param Direction Direction of the data transfer.
1371 @param Data The user data buffer.
1372 @param Len Length of the user data.
1373 @param PktId Packet identificaion.
1374 @param MappedAddr Mapped address to return.
1375 @param Map Identificaion of this mapping to return.
1376
1377 @return EFI_SUCCESS Success.
1378 @return EFI_DEVICE_ERROR Fail to map the user data.
1379
1380 **/
1381 EFI_STATUS
1382 UhciMapUserData (
1383 IN USB_UHC_DEV *Uhc,
1384 IN EFI_USB_DATA_DIRECTION Direction,
1385 IN VOID *Data,
1386 IN OUT UINTN *Len,
1387 OUT UINT8 *PktId,
1388 OUT UINT8 **MappedAddr,
1389 OUT VOID **Map
1390 );
1391
1392 /**
1393 Provides the controller-specific addresses required to access system memory from a
1394 DMA bus master.
1395
1396 @param IoMmu Pointer to IOMMU PPI.
1397 @param Operation Indicates if the bus master is going to read or write to system memory.
1398 @param HostAddress The system memory address to map to the PCI controller.
1399 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
1400 that were mapped.
1401 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
1402 access the hosts HostAddress.
1403 @param Mapping A resulting value to pass to Unmap().
1404
1405 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
1406 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1407 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1408 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1409 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
1410
1411 **/
1412 EFI_STATUS
1413 IoMmuMap (
1414 IN EDKII_IOMMU_PPI *IoMmu,
1415 IN EDKII_IOMMU_OPERATION Operation,
1416 IN VOID *HostAddress,
1417 IN OUT UINTN *NumberOfBytes,
1418 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
1419 OUT VOID **Mapping
1420 );
1421
1422 /**
1423 Completes the Map() operation and releases any corresponding resources.
1424
1425 @param IoMmu Pointer to IOMMU PPI.
1426 @param Mapping The mapping value returned from Map().
1427
1428 **/
1429 VOID
1430 IoMmuUnmap (
1431 IN EDKII_IOMMU_PPI *IoMmu,
1432 IN VOID *Mapping
1433 );
1434
1435 /**
1436 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
1437 OperationBusMasterCommonBuffer64 mapping.
1438
1439 @param IoMmu Pointer to IOMMU PPI.
1440 @param Pages The number of pages to allocate.
1441 @param HostAddress A pointer to store the base system memory address of the
1442 allocated range.
1443 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
1444 access the hosts HostAddress.
1445 @param Mapping A resulting value to pass to Unmap().
1446
1447 @retval EFI_SUCCESS The requested memory pages were allocated.
1448 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
1449 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
1450 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1451 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1452
1453 **/
1454 EFI_STATUS
1455 IoMmuAllocateBuffer (
1456 IN EDKII_IOMMU_PPI *IoMmu,
1457 IN UINTN Pages,
1458 OUT VOID **HostAddress,
1459 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
1460 OUT VOID **Mapping
1461 );
1462
1463 /**
1464 Frees memory that was allocated with AllocateBuffer().
1465
1466 @param IoMmu Pointer to IOMMU PPI.
1467 @param Pages The number of pages to free.
1468 @param HostAddress The base system memory address of the allocated range.
1469 @param Mapping The mapping value returned from Map().
1470
1471 **/
1472 VOID
1473 IoMmuFreeBuffer (
1474 IN EDKII_IOMMU_PPI *IoMmu,
1475 IN UINTN Pages,
1476 IN VOID *HostAddress,
1477 IN VOID *Mapping
1478 );
1479
1480 /**
1481 Initialize IOMMU.
1482
1483 @param IoMmu Pointer to pointer to IOMMU PPI.
1484
1485 **/
1486 VOID
1487 IoMmuInit (
1488 OUT EDKII_IOMMU_PPI **IoMmu
1489 );
1490
1491 #endif