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SecurityPkg/Tcg2Dxe: Properly shutdown TPM before reset
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.c
1 /** @file
2
3 XHCI transfer scheduling routines.
4
5 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include "Xhci.h"
17
18 /**
19 Create a command transfer TRB to support XHCI command interfaces.
20
21 @param Xhc The XHCI Instance.
22 @param CmdTrb The cmd TRB to be executed.
23
24 @return Created URB or NULL.
25
26 **/
27 URB*
28 XhcCreateCmdTrb (
29 IN USB_XHCI_INSTANCE *Xhc,
30 IN TRB_TEMPLATE *CmdTrb
31 )
32 {
33 URB *Urb;
34
35 Urb = AllocateZeroPool (sizeof (URB));
36 if (Urb == NULL) {
37 return NULL;
38 }
39
40 Urb->Signature = XHC_URB_SIG;
41
42 Urb->Ring = &Xhc->CmdRing;
43 XhcSyncTrsRing (Xhc, Urb->Ring);
44 Urb->TrbNum = 1;
45 Urb->TrbStart = Urb->Ring->RingEnqueue;
46 CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
47 Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
48 Urb->TrbEnd = Urb->TrbStart;
49
50 return Urb;
51 }
52
53 /**
54 Execute a XHCI cmd TRB pointed by CmdTrb.
55
56 @param Xhc The XHCI Instance.
57 @param CmdTrb The cmd TRB to be executed.
58 @param Timeout Indicates the maximum time, in millisecond, which the
59 transfer is allowed to complete.
60 @param EvtTrb The event TRB corresponding to the cmd TRB.
61
62 @retval EFI_SUCCESS The transfer was completed successfully.
63 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
64 @retval EFI_TIMEOUT The transfer failed due to timeout.
65 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
66
67 **/
68 EFI_STATUS
69 EFIAPI
70 XhcCmdTransfer (
71 IN USB_XHCI_INSTANCE *Xhc,
72 IN TRB_TEMPLATE *CmdTrb,
73 IN UINTN Timeout,
74 OUT TRB_TEMPLATE **EvtTrb
75 )
76 {
77 EFI_STATUS Status;
78 URB *Urb;
79
80 //
81 // Validate the parameters
82 //
83 if ((Xhc == NULL) || (CmdTrb == NULL)) {
84 return EFI_INVALID_PARAMETER;
85 }
86
87 Status = EFI_DEVICE_ERROR;
88
89 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
90 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));
91 goto ON_EXIT;
92 }
93
94 //
95 // Create a new URB, then poll the execution status.
96 //
97 Urb = XhcCreateCmdTrb (Xhc, CmdTrb);
98
99 if (Urb == NULL) {
100 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));
101 Status = EFI_OUT_OF_RESOURCES;
102 goto ON_EXIT;
103 }
104
105 Status = XhcExecTransfer (Xhc, TRUE, Urb, Timeout);
106 *EvtTrb = Urb->EvtTrb;
107
108 if (Urb->Result == EFI_USB_NOERROR) {
109 Status = EFI_SUCCESS;
110 }
111
112 XhcFreeUrb (Xhc, Urb);
113
114 ON_EXIT:
115 return Status;
116 }
117
118 /**
119 Create a new URB for a new transaction.
120
121 @param Xhc The XHCI Instance
122 @param BusAddr The logical device address assigned by UsbBus driver
123 @param EpAddr Endpoint addrress
124 @param DevSpeed The device speed
125 @param MaxPacket The max packet length of the endpoint
126 @param Type The transaction type
127 @param Request The standard USB request for control transfer
128 @param Data The user data to transfer
129 @param DataLen The length of data buffer
130 @param Callback The function to call when data is transferred
131 @param Context The context to the callback
132
133 @return Created URB or NULL
134
135 **/
136 URB*
137 XhcCreateUrb (
138 IN USB_XHCI_INSTANCE *Xhc,
139 IN UINT8 BusAddr,
140 IN UINT8 EpAddr,
141 IN UINT8 DevSpeed,
142 IN UINTN MaxPacket,
143 IN UINTN Type,
144 IN EFI_USB_DEVICE_REQUEST *Request,
145 IN VOID *Data,
146 IN UINTN DataLen,
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
148 IN VOID *Context
149 )
150 {
151 USB_ENDPOINT *Ep;
152 EFI_STATUS Status;
153 URB *Urb;
154
155 Urb = AllocateZeroPool (sizeof (URB));
156 if (Urb == NULL) {
157 return NULL;
158 }
159
160 Urb->Signature = XHC_URB_SIG;
161 InitializeListHead (&Urb->UrbList);
162
163 Ep = &Urb->Ep;
164 Ep->BusAddr = BusAddr;
165 Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
166 Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
167 Ep->DevSpeed = DevSpeed;
168 Ep->MaxPacket = MaxPacket;
169 Ep->Type = Type;
170
171 Urb->Request = Request;
172 Urb->Data = Data;
173 Urb->DataLen = DataLen;
174 Urb->Callback = Callback;
175 Urb->Context = Context;
176
177 Status = XhcCreateTransferTrb (Xhc, Urb);
178 ASSERT_EFI_ERROR (Status);
179 if (EFI_ERROR (Status)) {
180 DEBUG ((EFI_D_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
181 FreePool (Urb);
182 Urb = NULL;
183 }
184
185 return Urb;
186 }
187
188 /**
189 Free an allocated URB.
190
191 @param Xhc The XHCI device.
192 @param Urb The URB to free.
193
194 **/
195 VOID
196 XhcFreeUrb (
197 IN USB_XHCI_INSTANCE *Xhc,
198 IN URB *Urb
199 )
200 {
201 if ((Xhc == NULL) || (Urb == NULL)) {
202 return;
203 }
204
205 if (Urb->DataMap != NULL) {
206 Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);
207 }
208
209 FreePool (Urb);
210 }
211
212 /**
213 Create a transfer TRB.
214
215 @param Xhc The XHCI Instance
216 @param Urb The urb used to construct the transfer TRB.
217
218 @return Created TRB or NULL
219
220 **/
221 EFI_STATUS
222 XhcCreateTransferTrb (
223 IN USB_XHCI_INSTANCE *Xhc,
224 IN URB *Urb
225 )
226 {
227 VOID *OutputContext;
228 TRANSFER_RING *EPRing;
229 UINT8 EPType;
230 UINT8 SlotId;
231 UINT8 Dci;
232 TRB *TrbStart;
233 UINTN TotalLen;
234 UINTN Len;
235 UINTN TrbNum;
236 EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
237 EFI_PHYSICAL_ADDRESS PhyAddr;
238 VOID *Map;
239 EFI_STATUS Status;
240
241 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
242 if (SlotId == 0) {
243 return EFI_DEVICE_ERROR;
244 }
245
246 Urb->Finished = FALSE;
247 Urb->StartDone = FALSE;
248 Urb->EndDone = FALSE;
249 Urb->Completed = 0;
250 Urb->Result = EFI_USB_NOERROR;
251
252 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
253 ASSERT (Dci < 32);
254 EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
255 Urb->Ring = EPRing;
256 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
257 if (Xhc->HcCParams.Data.Csz == 0) {
258 EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
259 } else {
260 EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
261 }
262
263 if (Urb->Data != NULL) {
264 if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
265 MapOp = EfiPciIoOperationBusMasterWrite;
266 } else {
267 MapOp = EfiPciIoOperationBusMasterRead;
268 }
269
270 Len = Urb->DataLen;
271 Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
272
273 if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
274 DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
275 return EFI_OUT_OF_RESOURCES;
276 }
277
278 Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
279 Urb->DataMap = Map;
280 }
281
282 //
283 // Construct the TRB
284 //
285 XhcSyncTrsRing (Xhc, EPRing);
286 Urb->TrbStart = EPRing->RingEnqueue;
287 switch (EPType) {
288 case ED_CONTROL_BIDIR:
289 //
290 // For control transfer, create SETUP_STAGE_TRB first.
291 //
292 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
293 TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
294 TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
295 TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
296 TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;
297 TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;
298 TrbStart->TrbCtrSetup.Length = 8;
299 TrbStart->TrbCtrSetup.IntTarget = 0;
300 TrbStart->TrbCtrSetup.IOC = 1;
301 TrbStart->TrbCtrSetup.IDT = 1;
302 TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;
303 if (Urb->Ep.Direction == EfiUsbDataIn) {
304 TrbStart->TrbCtrSetup.TRT = 3;
305 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
306 TrbStart->TrbCtrSetup.TRT = 2;
307 } else {
308 TrbStart->TrbCtrSetup.TRT = 0;
309 }
310 //
311 // Update the cycle bit
312 //
313 TrbStart->TrbCtrSetup.CycleBit = EPRing->RingPCS & BIT0;
314 Urb->TrbNum++;
315
316 //
317 // For control transfer, create DATA_STAGE_TRB.
318 //
319 if (Urb->DataLen > 0) {
320 XhcSyncTrsRing (Xhc, EPRing);
321 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
322 TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);
323 TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);
324 TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
325 TrbStart->TrbCtrData.TDSize = 0;
326 TrbStart->TrbCtrData.IntTarget = 0;
327 TrbStart->TrbCtrData.ISP = 1;
328 TrbStart->TrbCtrData.IOC = 1;
329 TrbStart->TrbCtrData.IDT = 0;
330 TrbStart->TrbCtrData.CH = 0;
331 TrbStart->TrbCtrData.Type = TRB_TYPE_DATA_STAGE;
332 if (Urb->Ep.Direction == EfiUsbDataIn) {
333 TrbStart->TrbCtrData.DIR = 1;
334 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
335 TrbStart->TrbCtrData.DIR = 0;
336 } else {
337 TrbStart->TrbCtrData.DIR = 0;
338 }
339 //
340 // Update the cycle bit
341 //
342 TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;
343 Urb->TrbNum++;
344 }
345 //
346 // For control transfer, create STATUS_STAGE_TRB.
347 // Get the pointer to next TRB for status stage use
348 //
349 XhcSyncTrsRing (Xhc, EPRing);
350 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
351 TrbStart->TrbCtrStatus.IntTarget = 0;
352 TrbStart->TrbCtrStatus.IOC = 1;
353 TrbStart->TrbCtrStatus.CH = 0;
354 TrbStart->TrbCtrStatus.Type = TRB_TYPE_STATUS_STAGE;
355 if (Urb->Ep.Direction == EfiUsbDataIn) {
356 TrbStart->TrbCtrStatus.DIR = 0;
357 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
358 TrbStart->TrbCtrStatus.DIR = 1;
359 } else {
360 TrbStart->TrbCtrStatus.DIR = 0;
361 }
362 //
363 // Update the cycle bit
364 //
365 TrbStart->TrbCtrStatus.CycleBit = EPRing->RingPCS & BIT0;
366 //
367 // Update the enqueue pointer
368 //
369 XhcSyncTrsRing (Xhc, EPRing);
370 Urb->TrbNum++;
371 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
372
373 break;
374
375 case ED_BULK_OUT:
376 case ED_BULK_IN:
377 TotalLen = 0;
378 Len = 0;
379 TrbNum = 0;
380 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
381 while (TotalLen < Urb->DataLen) {
382 if ((TotalLen + 0x10000) >= Urb->DataLen) {
383 Len = Urb->DataLen - TotalLen;
384 } else {
385 Len = 0x10000;
386 }
387 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
388 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
389 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
390 TrbStart->TrbNormal.Length = (UINT32) Len;
391 TrbStart->TrbNormal.TDSize = 0;
392 TrbStart->TrbNormal.IntTarget = 0;
393 TrbStart->TrbNormal.ISP = 1;
394 TrbStart->TrbNormal.IOC = 1;
395 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;
396 //
397 // Update the cycle bit
398 //
399 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
400
401 XhcSyncTrsRing (Xhc, EPRing);
402 TrbNum++;
403 TotalLen += Len;
404 }
405
406 Urb->TrbNum = TrbNum;
407 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
408 break;
409
410 case ED_INTERRUPT_OUT:
411 case ED_INTERRUPT_IN:
412 TotalLen = 0;
413 Len = 0;
414 TrbNum = 0;
415 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
416 while (TotalLen < Urb->DataLen) {
417 if ((TotalLen + 0x10000) >= Urb->DataLen) {
418 Len = Urb->DataLen - TotalLen;
419 } else {
420 Len = 0x10000;
421 }
422 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
423 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
424 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
425 TrbStart->TrbNormal.Length = (UINT32) Len;
426 TrbStart->TrbNormal.TDSize = 0;
427 TrbStart->TrbNormal.IntTarget = 0;
428 TrbStart->TrbNormal.ISP = 1;
429 TrbStart->TrbNormal.IOC = 1;
430 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;
431 //
432 // Update the cycle bit
433 //
434 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
435
436 XhcSyncTrsRing (Xhc, EPRing);
437 TrbNum++;
438 TotalLen += Len;
439 }
440
441 Urb->TrbNum = TrbNum;
442 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
443 break;
444
445 default:
446 DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
447 ASSERT (FALSE);
448 break;
449 }
450
451 return EFI_SUCCESS;
452 }
453
454
455 /**
456 Initialize the XHCI host controller for schedule.
457
458 @param Xhc The XHCI Instance to be initialized.
459
460 **/
461 VOID
462 XhcInitSched (
463 IN USB_XHCI_INSTANCE *Xhc
464 )
465 {
466 VOID *Dcbaa;
467 EFI_PHYSICAL_ADDRESS DcbaaPhy;
468 UINT64 CmdRing;
469 EFI_PHYSICAL_ADDRESS CmdRingPhy;
470 UINTN Entries;
471 UINT32 MaxScratchpadBufs;
472 UINT64 *ScratchBuf;
473 EFI_PHYSICAL_ADDRESS ScratchPhy;
474 UINT64 *ScratchEntry;
475 EFI_PHYSICAL_ADDRESS ScratchEntryPhy;
476 UINT32 Index;
477 UINTN *ScratchEntryMap;
478 EFI_STATUS Status;
479
480 //
481 // Initialize memory management.
482 //
483 Xhc->MemPool = UsbHcInitMemPool (Xhc->PciIo);
484 ASSERT (Xhc->MemPool != NULL);
485
486 //
487 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
488 // to enable the device slots that system software is going to use.
489 //
490 Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;
491 ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);
492 XhcWriteOpReg (Xhc, XHC_CONFIG_OFFSET, Xhc->MaxSlotsEn);
493
494 //
495 // The Device Context Base Address Array entry associated with each allocated Device Slot
496 // shall contain a 64-bit pointer to the base of the associated Device Context.
497 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
498 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
499 //
500 Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
501 Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
502 ASSERT (Dcbaa != NULL);
503 ZeroMem (Dcbaa, Entries);
504
505 //
506 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
507 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
508 // mode (Run/Stop(R/S) ='1').
509 //
510 MaxScratchpadBufs = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);
511 Xhc->MaxScratchpadBufs = MaxScratchpadBufs;
512 ASSERT (MaxScratchpadBufs <= 1023);
513 if (MaxScratchpadBufs != 0) {
514 //
515 // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
516 //
517 ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);
518 ASSERT (ScratchEntryMap != NULL);
519 Xhc->ScratchEntryMap = ScratchEntryMap;
520
521 //
522 // Allocate the buffer to record the host address for each entry
523 //
524 ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);
525 ASSERT (ScratchEntry != NULL);
526 Xhc->ScratchEntry = ScratchEntry;
527
528 ScratchPhy = 0;
529 Status = UsbHcAllocateAlignedPages (
530 Xhc->PciIo,
531 EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
532 Xhc->PageSize,
533 (VOID **) &ScratchBuf,
534 &ScratchPhy,
535 &Xhc->ScratchMap
536 );
537 ASSERT_EFI_ERROR (Status);
538
539 ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
540 Xhc->ScratchBuf = ScratchBuf;
541
542 //
543 // Allocate each scratch buffer
544 //
545 for (Index = 0; Index < MaxScratchpadBufs; Index++) {
546 ScratchEntryPhy = 0;
547 Status = UsbHcAllocateAlignedPages (
548 Xhc->PciIo,
549 EFI_SIZE_TO_PAGES (Xhc->PageSize),
550 Xhc->PageSize,
551 (VOID **) &ScratchEntry[Index],
552 &ScratchEntryPhy,
553 (VOID **) &ScratchEntryMap[Index]
554 );
555 ASSERT_EFI_ERROR (Status);
556 ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
557 //
558 // Fill with the PCI device address
559 //
560 *ScratchBuf++ = ScratchEntryPhy;
561 }
562 //
563 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
564 // Device Context Base Address Array points to the Scratchpad Buffer Array.
565 //
566 *(UINT64 *)Dcbaa = (UINT64)(UINTN) ScratchPhy;
567 }
568
569 //
570 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
571 // a 64-bit address pointing to where the Device Context Base Address Array is located.
572 //
573 Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;
574 //
575 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
576 // So divide it to two 32-bytes width register access.
577 //
578 DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);
579 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
580 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
581
582 DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
583
584 //
585 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
586 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
587 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
588 // always be '0'.
589 //
590 CreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);
591 //
592 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
593 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
594 // So we set RCS as inverted PCS init value to let Command Ring empty
595 //
596 CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
597 CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN) CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
598 ASSERT ((CmdRingPhy & 0x3F) == 0);
599 CmdRingPhy |= XHC_CRCR_RCS;
600 //
601 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
602 // So divide it to two 32-bytes width register access.
603 //
604 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
605 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
606
607 //
608 // Disable the 'interrupter enable' bit in USB_CMD
609 // and clear IE & IP bit in all Interrupter X Management Registers.
610 //
611 XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);
612 for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {
613 XhcClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);
614 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);
615 }
616
617 //
618 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
619 //
620 CreateEventRing (Xhc, &Xhc->EventRing);
621 DEBUG ((DEBUG_INFO, "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
622 Xhc->CmdRing.RingSeg0, (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
623 Xhc->EventRing.EventRingSeg0, (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
624 ));
625 }
626
627 /**
628 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
629 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
630 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
631 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
632 Stopped to the Running state.
633
634 @param Xhc The XHCI Instance.
635 @param Urb The urb which makes the endpoint halted.
636
637 @retval EFI_SUCCESS The recovery is successful.
638 @retval Others Failed to recovery halted endpoint.
639
640 **/
641 EFI_STATUS
642 EFIAPI
643 XhcRecoverHaltedEndpoint (
644 IN USB_XHCI_INSTANCE *Xhc,
645 IN URB *Urb
646 )
647 {
648 EFI_STATUS Status;
649 UINT8 Dci;
650 UINT8 SlotId;
651
652 Status = EFI_SUCCESS;
653 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
654 if (SlotId == 0) {
655 return EFI_DEVICE_ERROR;
656 }
657 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
658 ASSERT (Dci < 32);
659
660 DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
661
662 //
663 // 1) Send Reset endpoint command to transit from halt to stop state
664 //
665 Status = XhcResetEndpoint(Xhc, SlotId, Dci);
666 if (EFI_ERROR(Status)) {
667 DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
668 goto Done;
669 }
670
671 //
672 // 2)Set dequeue pointer
673 //
674 Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
675 if (EFI_ERROR(Status)) {
676 DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
677 goto Done;
678 }
679
680 //
681 // 3)Ring the doorbell to transit from stop to active
682 //
683 XhcRingDoorBell (Xhc, SlotId, Dci);
684
685 Done:
686 return Status;
687 }
688
689 /**
690 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
691 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
692 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
693 state.
694
695 @param Xhc The XHCI Instance.
696 @param Urb The urb which doesn't get completed in a specified timeout range.
697
698 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
699 @retval EFI_ALREADY_STARTED The Urb is finished so no deque is needed.
700 @retval Others Failed to stop the endpoint and dequeue the TDs.
701
702 **/
703 EFI_STATUS
704 EFIAPI
705 XhcDequeueTrbFromEndpoint (
706 IN USB_XHCI_INSTANCE *Xhc,
707 IN URB *Urb
708 )
709 {
710 EFI_STATUS Status;
711 UINT8 Dci;
712 UINT8 SlotId;
713
714 Status = EFI_SUCCESS;
715 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
716 if (SlotId == 0) {
717 return EFI_DEVICE_ERROR;
718 }
719 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
720 ASSERT (Dci < 32);
721
722 DEBUG ((EFI_D_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
723
724 //
725 // 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
726 //
727 Status = XhcStopEndpoint(Xhc, SlotId, Dci, Urb);
728 if (EFI_ERROR(Status)) {
729 DEBUG ((EFI_D_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
730 goto Done;
731 }
732
733 //
734 // 2)Set dequeue pointer
735 //
736 if (Urb->Finished && Urb->Result == EFI_USB_NOERROR) {
737 //
738 // Return Already Started to indicate the pending URB is finished.
739 // This fixes BULK data loss when transfer is detected as timeout
740 // but finished just before stopping endpoint.
741 //
742 Status = EFI_ALREADY_STARTED;
743 DEBUG ((DEBUG_INFO, "XhcDequeueTrbFromEndpoint: Pending URB is finished: Length Actual/Expect = %d/%d!\n", Urb->Completed, Urb->DataLen));
744 } else {
745 Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
746 if (EFI_ERROR (Status)) {
747 DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
748 goto Done;
749 }
750 }
751
752 //
753 // 3)Ring the doorbell to transit from stop to active
754 //
755 XhcRingDoorBell (Xhc, SlotId, Dci);
756
757 Done:
758 return Status;
759 }
760
761 /**
762 Create XHCI event ring.
763
764 @param Xhc The XHCI Instance.
765 @param EventRing The created event ring.
766
767 **/
768 VOID
769 CreateEventRing (
770 IN USB_XHCI_INSTANCE *Xhc,
771 OUT EVENT_RING *EventRing
772 )
773 {
774 VOID *Buf;
775 EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
776 UINTN Size;
777 EFI_PHYSICAL_ADDRESS ERSTPhy;
778 EFI_PHYSICAL_ADDRESS DequeuePhy;
779
780 ASSERT (EventRing != NULL);
781
782 Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
783 Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
784 ASSERT (Buf != NULL);
785 ASSERT (((UINTN) Buf & 0x3F) == 0);
786 ZeroMem (Buf, Size);
787
788 EventRing->EventRingSeg0 = Buf;
789 EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
790 EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
791 EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
792
793 DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
794
795 //
796 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
797 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
798 //
799 EventRing->EventRingCCS = 1;
800
801 Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
802 Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
803 ASSERT (Buf != NULL);
804 ASSERT (((UINTN) Buf & 0x3F) == 0);
805 ZeroMem (Buf, Size);
806
807 ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
808 EventRing->ERSTBase = ERSTBase;
809 ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
810 ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
811 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
812
813 ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);
814
815 //
816 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
817 //
818 XhcWriteRuntimeReg (
819 Xhc,
820 XHC_ERSTSZ_OFFSET,
821 ERST_NUMBER
822 );
823 //
824 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
825 //
826 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
827 // So divide it to two 32-bytes width register access.
828 //
829 XhcWriteRuntimeReg (
830 Xhc,
831 XHC_ERDP_OFFSET,
832 XHC_LOW_32BIT((UINT64)(UINTN)DequeuePhy)
833 );
834 XhcWriteRuntimeReg (
835 Xhc,
836 XHC_ERDP_OFFSET + 4,
837 XHC_HIGH_32BIT((UINT64)(UINTN)DequeuePhy)
838 );
839 //
840 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
841 //
842 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
843 // So divide it to two 32-bytes width register access.
844 //
845 XhcWriteRuntimeReg (
846 Xhc,
847 XHC_ERSTBA_OFFSET,
848 XHC_LOW_32BIT((UINT64)(UINTN)ERSTPhy)
849 );
850 XhcWriteRuntimeReg (
851 Xhc,
852 XHC_ERSTBA_OFFSET + 4,
853 XHC_HIGH_32BIT((UINT64)(UINTN)ERSTPhy)
854 );
855 //
856 // Need set IMAN IE bit to enble the ring interrupt
857 //
858 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET, XHC_IMAN_IE);
859 }
860
861 /**
862 Create XHCI transfer ring.
863
864 @param Xhc The XHCI Instance.
865 @param TrbNum The number of TRB in the ring.
866 @param TransferRing The created transfer ring.
867
868 **/
869 VOID
870 CreateTransferRing (
871 IN USB_XHCI_INSTANCE *Xhc,
872 IN UINTN TrbNum,
873 OUT TRANSFER_RING *TransferRing
874 )
875 {
876 VOID *Buf;
877 LINK_TRB *EndTrb;
878 EFI_PHYSICAL_ADDRESS PhyAddr;
879
880 Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
881 ASSERT (Buf != NULL);
882 ASSERT (((UINTN) Buf & 0x3F) == 0);
883 ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
884
885 TransferRing->RingSeg0 = Buf;
886 TransferRing->TrbNumber = TrbNum;
887 TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
888 TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
889 TransferRing->RingPCS = 1;
890 //
891 // 4.9.2 Transfer Ring Management
892 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
893 // point to the first TRB in the ring.
894 //
895 EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
896 EndTrb->Type = TRB_TYPE_LINK;
897 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
898 EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
899 EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
900 //
901 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
902 //
903 EndTrb->TC = 1;
904 //
905 // Set Cycle bit as other TRB PCS init value
906 //
907 EndTrb->CycleBit = 0;
908 }
909
910 /**
911 Free XHCI event ring.
912
913 @param Xhc The XHCI Instance.
914 @param EventRing The event ring to be freed.
915
916 **/
917 EFI_STATUS
918 EFIAPI
919 XhcFreeEventRing (
920 IN USB_XHCI_INSTANCE *Xhc,
921 IN EVENT_RING *EventRing
922 )
923 {
924 if(EventRing->EventRingSeg0 == NULL) {
925 return EFI_SUCCESS;
926 }
927
928 //
929 // Free EventRing Segment 0
930 //
931 UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
932
933 //
934 // Free ESRT table
935 //
936 UsbHcFreeMem (Xhc->MemPool, EventRing->ERSTBase, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
937 return EFI_SUCCESS;
938 }
939
940 /**
941 Free the resouce allocated at initializing schedule.
942
943 @param Xhc The XHCI Instance.
944
945 **/
946 VOID
947 XhcFreeSched (
948 IN USB_XHCI_INSTANCE *Xhc
949 )
950 {
951 UINT32 Index;
952 UINT64 *ScratchEntry;
953
954 if (Xhc->ScratchBuf != NULL) {
955 ScratchEntry = Xhc->ScratchEntry;
956 for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {
957 //
958 // Free Scratchpad Buffers
959 //
960 UsbHcFreeAlignedPages (Xhc->PciIo, (VOID*)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
961 }
962 //
963 // Free Scratchpad Buffer Array
964 //
965 UsbHcFreeAlignedPages (Xhc->PciIo, Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)), Xhc->ScratchMap);
966 FreePool (Xhc->ScratchEntryMap);
967 FreePool (Xhc->ScratchEntry);
968 }
969
970 if (Xhc->CmdRing.RingSeg0 != NULL) {
971 UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
972 Xhc->CmdRing.RingSeg0 = NULL;
973 }
974
975 XhcFreeEventRing (Xhc,&Xhc->EventRing);
976
977 if (Xhc->DCBAA != NULL) {
978 UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));
979 Xhc->DCBAA = NULL;
980 }
981
982 //
983 // Free memory pool at last
984 //
985 if (Xhc->MemPool != NULL) {
986 UsbHcFreeMemPool (Xhc->MemPool);
987 Xhc->MemPool = NULL;
988 }
989 }
990
991 /**
992 Check if the Trb is a transaction of the URB.
993
994 @param Xhc The XHCI Instance.
995 @param Trb The TRB to be checked
996 @param Urb The URB to be checked.
997
998 @retval TRUE It is a transaction of the URB.
999 @retval FALSE It is not any transaction of the URB.
1000
1001 **/
1002 BOOLEAN
1003 IsTransferRingTrb (
1004 IN USB_XHCI_INSTANCE *Xhc,
1005 IN TRB_TEMPLATE *Trb,
1006 IN URB *Urb
1007 )
1008 {
1009 LINK_TRB *LinkTrb;
1010 TRB_TEMPLATE *CheckedTrb;
1011 UINTN Index;
1012 EFI_PHYSICAL_ADDRESS PhyAddr;
1013
1014 CheckedTrb = Urb->TrbStart;
1015 for (Index = 0; Index < Urb->TrbNum; Index++) {
1016 if (Trb == CheckedTrb) {
1017 return TRUE;
1018 }
1019 CheckedTrb++;
1020 //
1021 // If the checked TRB is the link TRB at the end of the transfer ring,
1022 // recircle it to the head of the ring.
1023 //
1024 if (CheckedTrb->Type == TRB_TYPE_LINK) {
1025 LinkTrb = (LINK_TRB *) CheckedTrb;
1026 PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64) LinkTrb->PtrHi, 32));
1027 CheckedTrb = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
1028 ASSERT (CheckedTrb == Urb->Ring->RingSeg0);
1029 }
1030 }
1031
1032 return FALSE;
1033 }
1034
1035 /**
1036 Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.
1037
1038 @param Xhc The XHCI Instance.
1039 @param Trb The TRB to be checked.
1040 @param Urb The pointer to the matched Urb.
1041
1042 @retval TRUE The Trb is matched with a transaction of the URBs in the async list.
1043 @retval FALSE The Trb is not matched with any URBs in the async list.
1044
1045 **/
1046 BOOLEAN
1047 IsAsyncIntTrb (
1048 IN USB_XHCI_INSTANCE *Xhc,
1049 IN TRB_TEMPLATE *Trb,
1050 OUT URB **Urb
1051 )
1052 {
1053 LIST_ENTRY *Entry;
1054 LIST_ENTRY *Next;
1055 URB *CheckedUrb;
1056
1057 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1058 CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1059 if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) {
1060 *Urb = CheckedUrb;
1061 return TRUE;
1062 }
1063 }
1064
1065 return FALSE;
1066 }
1067
1068
1069 /**
1070 Check the URB's execution result and update the URB's
1071 result accordingly.
1072
1073 @param Xhc The XHCI Instance.
1074 @param Urb The URB to check result.
1075
1076 @return Whether the result of URB transfer is finialized.
1077
1078 **/
1079 BOOLEAN
1080 XhcCheckUrbResult (
1081 IN USB_XHCI_INSTANCE *Xhc,
1082 IN URB *Urb
1083 )
1084 {
1085 EVT_TRB_TRANSFER *EvtTrb;
1086 TRB_TEMPLATE *TRBPtr;
1087 UINTN Index;
1088 UINT8 TRBType;
1089 EFI_STATUS Status;
1090 URB *AsyncUrb;
1091 URB *CheckedUrb;
1092 UINT64 XhcDequeue;
1093 UINT32 High;
1094 UINT32 Low;
1095 EFI_PHYSICAL_ADDRESS PhyAddr;
1096
1097 ASSERT ((Xhc != NULL) && (Urb != NULL));
1098
1099 Status = EFI_SUCCESS;
1100 AsyncUrb = NULL;
1101
1102 if (Urb->Finished) {
1103 goto EXIT;
1104 }
1105
1106 EvtTrb = NULL;
1107
1108 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
1109 Urb->Result |= EFI_USB_ERR_SYSTEM;
1110 goto EXIT;
1111 }
1112
1113 //
1114 // Traverse the event ring to find out all new events from the previous check.
1115 //
1116 XhcSyncEventRing (Xhc, &Xhc->EventRing);
1117 for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {
1118 Status = XhcCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
1119 if (Status == EFI_NOT_READY) {
1120 //
1121 // All new events are handled, return directly.
1122 //
1123 goto EXIT;
1124 }
1125
1126 //
1127 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.
1128 //
1129 if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
1130 continue;
1131 }
1132
1133 //
1134 // Need convert pci device address to host address
1135 //
1136 PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
1137 TRBPtr = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
1138
1139 //
1140 // Update the status of URB including the pending URB, the URB that is currently checked,
1141 // and URBs in the XHCI's async interrupt transfer list.
1142 // This way is used to avoid that those completed async transfer events don't get
1143 // handled in time and are flushed by newer coming events.
1144 //
1145 if (Xhc->PendingUrb != NULL && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {
1146 CheckedUrb = Xhc->PendingUrb;
1147 } else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {
1148 CheckedUrb = Urb;
1149 } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {
1150 CheckedUrb = AsyncUrb;
1151 } else {
1152 continue;
1153 }
1154
1155 switch (EvtTrb->Completecode) {
1156 case TRB_COMPLETION_STALL_ERROR:
1157 CheckedUrb->Result |= EFI_USB_ERR_STALL;
1158 CheckedUrb->Finished = TRUE;
1159 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
1160 goto EXIT;
1161
1162 case TRB_COMPLETION_BABBLE_ERROR:
1163 CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
1164 CheckedUrb->Finished = TRUE;
1165 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
1166 goto EXIT;
1167
1168 case TRB_COMPLETION_DATA_BUFFER_ERROR:
1169 CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
1170 CheckedUrb->Finished = TRUE;
1171 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
1172 goto EXIT;
1173
1174 case TRB_COMPLETION_USB_TRANSACTION_ERROR:
1175 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
1176 CheckedUrb->Finished = TRUE;
1177 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
1178 goto EXIT;
1179
1180 case TRB_COMPLETION_STOPPED:
1181 case TRB_COMPLETION_STOPPED_LENGTH_INVALID:
1182 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
1183 CheckedUrb->Finished = TRUE;
1184 //
1185 // The pending URB is timeout and force stopped when stopping endpoint.
1186 // Continue the loop to receive the Command Complete Event for stopping endpoint.
1187 //
1188 continue;
1189
1190 case TRB_COMPLETION_SHORT_PACKET:
1191 case TRB_COMPLETION_SUCCESS:
1192 if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {
1193 DEBUG ((EFI_D_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
1194 }
1195
1196 TRBType = (UINT8) (TRBPtr->Type);
1197 if ((TRBType == TRB_TYPE_DATA_STAGE) ||
1198 (TRBType == TRB_TYPE_NORMAL) ||
1199 (TRBType == TRB_TYPE_ISOCH)) {
1200 CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
1201 }
1202
1203 break;
1204
1205 default:
1206 DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
1207 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
1208 CheckedUrb->Finished = TRUE;
1209 goto EXIT;
1210 }
1211
1212 //
1213 // Only check first and end Trb event address
1214 //
1215 if (TRBPtr == CheckedUrb->TrbStart) {
1216 CheckedUrb->StartDone = TRUE;
1217 }
1218
1219 if (TRBPtr == CheckedUrb->TrbEnd) {
1220 CheckedUrb->EndDone = TRUE;
1221 }
1222
1223 if (CheckedUrb->StartDone && CheckedUrb->EndDone) {
1224 CheckedUrb->Finished = TRUE;
1225 CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;
1226 }
1227 }
1228
1229 EXIT:
1230
1231 //
1232 // Advance event ring to last available entry
1233 //
1234 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1235 // So divide it to two 32-bytes width register access.
1236 //
1237 Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
1238 High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
1239 XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
1240
1241 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
1242
1243 if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {
1244 //
1245 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1246 // So divide it to two 32-bytes width register access.
1247 //
1248 XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (PhyAddr) | BIT3);
1249 XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (PhyAddr));
1250 }
1251
1252 return Urb->Finished;
1253 }
1254
1255
1256 /**
1257 Execute the transfer by polling the URB. This is a synchronous operation.
1258
1259 @param Xhc The XHCI Instance.
1260 @param CmdTransfer The executed URB is for cmd transfer or not.
1261 @param Urb The URB to execute.
1262 @param Timeout The time to wait before abort, in millisecond.
1263
1264 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1265 @return EFI_TIMEOUT The transfer failed due to time out.
1266 @return EFI_SUCCESS The transfer finished OK.
1267
1268 **/
1269 EFI_STATUS
1270 XhcExecTransfer (
1271 IN USB_XHCI_INSTANCE *Xhc,
1272 IN BOOLEAN CmdTransfer,
1273 IN URB *Urb,
1274 IN UINTN Timeout
1275 )
1276 {
1277 EFI_STATUS Status;
1278 UINTN Index;
1279 UINT64 Loop;
1280 UINT8 SlotId;
1281 UINT8 Dci;
1282 BOOLEAN Finished;
1283
1284 if (CmdTransfer) {
1285 SlotId = 0;
1286 Dci = 0;
1287 } else {
1288 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
1289 if (SlotId == 0) {
1290 return EFI_DEVICE_ERROR;
1291 }
1292 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
1293 ASSERT (Dci < 32);
1294 }
1295
1296 Status = EFI_SUCCESS;
1297 Loop = Timeout * XHC_1_MILLISECOND;
1298 if (Timeout == 0) {
1299 Loop = 0xFFFFFFFF;
1300 }
1301
1302 XhcRingDoorBell (Xhc, SlotId, Dci);
1303
1304 for (Index = 0; Index < Loop; Index++) {
1305 Finished = XhcCheckUrbResult (Xhc, Urb);
1306 if (Finished) {
1307 break;
1308 }
1309 gBS->Stall (XHC_1_MICROSECOND);
1310 }
1311
1312 if (Index == Loop) {
1313 Urb->Result = EFI_USB_ERR_TIMEOUT;
1314 Status = EFI_TIMEOUT;
1315 } else if (Urb->Result != EFI_USB_NOERROR) {
1316 Status = EFI_DEVICE_ERROR;
1317 }
1318
1319 return Status;
1320 }
1321
1322 /**
1323 Delete a single asynchronous interrupt transfer for
1324 the device and endpoint.
1325
1326 @param Xhc The XHCI Instance.
1327 @param BusAddr The logical device address assigned by UsbBus driver.
1328 @param EpNum The endpoint of the target.
1329
1330 @retval EFI_SUCCESS An asynchronous transfer is removed.
1331 @retval EFI_NOT_FOUND No transfer for the device is found.
1332
1333 **/
1334 EFI_STATUS
1335 XhciDelAsyncIntTransfer (
1336 IN USB_XHCI_INSTANCE *Xhc,
1337 IN UINT8 BusAddr,
1338 IN UINT8 EpNum
1339 )
1340 {
1341 LIST_ENTRY *Entry;
1342 LIST_ENTRY *Next;
1343 URB *Urb;
1344 EFI_USB_DATA_DIRECTION Direction;
1345 EFI_STATUS Status;
1346
1347 Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
1348 EpNum &= 0x0F;
1349
1350 Urb = NULL;
1351
1352 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1353 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1354 if ((Urb->Ep.BusAddr == BusAddr) &&
1355 (Urb->Ep.EpAddr == EpNum) &&
1356 (Urb->Ep.Direction == Direction)) {
1357 //
1358 // Device doesn't finish the IntTransfer until real data comes
1359 // So the TRB should be removed as well.
1360 //
1361 Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
1362 if (EFI_ERROR (Status)) {
1363 DEBUG ((EFI_D_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
1364 }
1365
1366 RemoveEntryList (&Urb->UrbList);
1367 FreePool (Urb->Data);
1368 XhcFreeUrb (Xhc, Urb);
1369 return EFI_SUCCESS;
1370 }
1371 }
1372
1373 return EFI_NOT_FOUND;
1374 }
1375
1376 /**
1377 Remove all the asynchronous interrutp transfers.
1378
1379 @param Xhc The XHCI Instance.
1380
1381 **/
1382 VOID
1383 XhciDelAllAsyncIntTransfers (
1384 IN USB_XHCI_INSTANCE *Xhc
1385 )
1386 {
1387 LIST_ENTRY *Entry;
1388 LIST_ENTRY *Next;
1389 URB *Urb;
1390 EFI_STATUS Status;
1391
1392 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1393 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1394
1395 //
1396 // Device doesn't finish the IntTransfer until real data comes
1397 // So the TRB should be removed as well.
1398 //
1399 Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
1400 if (EFI_ERROR (Status)) {
1401 DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
1402 }
1403
1404 RemoveEntryList (&Urb->UrbList);
1405 FreePool (Urb->Data);
1406 XhcFreeUrb (Xhc, Urb);
1407 }
1408 }
1409
1410 /**
1411 Update the queue head for next round of asynchronous transfer
1412
1413 @param Xhc The XHCI Instance.
1414 @param Urb The URB to update
1415
1416 **/
1417 VOID
1418 XhcUpdateAsyncRequest (
1419 IN USB_XHCI_INSTANCE *Xhc,
1420 IN URB *Urb
1421 )
1422 {
1423 EFI_STATUS Status;
1424
1425 if (Urb->Result == EFI_USB_NOERROR) {
1426 Status = XhcCreateTransferTrb (Xhc, Urb);
1427 if (EFI_ERROR (Status)) {
1428 return;
1429 }
1430 Status = RingIntTransferDoorBell (Xhc, Urb);
1431 if (EFI_ERROR (Status)) {
1432 return;
1433 }
1434 }
1435 }
1436
1437 /**
1438 Flush data from PCI controller specific address to mapped system
1439 memory address.
1440
1441 @param Xhc The XHCI device.
1442 @param Urb The URB to unmap.
1443
1444 @retval EFI_SUCCESS Success to flush data to mapped system memory.
1445 @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.
1446
1447 **/
1448 EFI_STATUS
1449 XhcFlushAsyncIntMap (
1450 IN USB_XHCI_INSTANCE *Xhc,
1451 IN URB *Urb
1452 )
1453 {
1454 EFI_STATUS Status;
1455 EFI_PHYSICAL_ADDRESS PhyAddr;
1456 EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
1457 EFI_PCI_IO_PROTOCOL *PciIo;
1458 UINTN Len;
1459 VOID *Map;
1460
1461 PciIo = Xhc->PciIo;
1462 Len = Urb->DataLen;
1463
1464 if (Urb->Ep.Direction == EfiUsbDataIn) {
1465 MapOp = EfiPciIoOperationBusMasterWrite;
1466 } else {
1467 MapOp = EfiPciIoOperationBusMasterRead;
1468 }
1469
1470 if (Urb->DataMap != NULL) {
1471 Status = PciIo->Unmap (PciIo, Urb->DataMap);
1472 if (EFI_ERROR (Status)) {
1473 goto ON_ERROR;
1474 }
1475 }
1476
1477 Urb->DataMap = NULL;
1478
1479 Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
1480 if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
1481 goto ON_ERROR;
1482 }
1483
1484 Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
1485 Urb->DataMap = Map;
1486 return EFI_SUCCESS;
1487
1488 ON_ERROR:
1489 return EFI_DEVICE_ERROR;
1490 }
1491
1492 /**
1493 Interrupt transfer periodic check handler.
1494
1495 @param Event Interrupt event.
1496 @param Context Pointer to USB_XHCI_INSTANCE.
1497
1498 **/
1499 VOID
1500 EFIAPI
1501 XhcMonitorAsyncRequests (
1502 IN EFI_EVENT Event,
1503 IN VOID *Context
1504 )
1505 {
1506 USB_XHCI_INSTANCE *Xhc;
1507 LIST_ENTRY *Entry;
1508 LIST_ENTRY *Next;
1509 UINT8 *ProcBuf;
1510 URB *Urb;
1511 UINT8 SlotId;
1512 EFI_STATUS Status;
1513 EFI_TPL OldTpl;
1514
1515 OldTpl = gBS->RaiseTPL (XHC_TPL);
1516
1517 Xhc = (USB_XHCI_INSTANCE*) Context;
1518
1519 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1520 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1521
1522 //
1523 // Make sure that the device is available before every check.
1524 //
1525 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
1526 if (SlotId == 0) {
1527 continue;
1528 }
1529
1530 //
1531 // Check the result of URB execution. If it is still
1532 // active, check the next one.
1533 //
1534 XhcCheckUrbResult (Xhc, Urb);
1535
1536 if (!Urb->Finished) {
1537 continue;
1538 }
1539
1540 //
1541 // Flush any PCI posted write transactions from a PCI host
1542 // bridge to system memory.
1543 //
1544 Status = XhcFlushAsyncIntMap (Xhc, Urb);
1545 if (EFI_ERROR (Status)) {
1546 DEBUG ((EFI_D_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
1547 }
1548
1549 //
1550 // Allocate a buffer then copy the transferred data for user.
1551 // If failed to allocate the buffer, update the URB for next
1552 // round of transfer. Ignore the data of this round.
1553 //
1554 ProcBuf = NULL;
1555 if (Urb->Result == EFI_USB_NOERROR) {
1556 ASSERT (Urb->Completed <= Urb->DataLen);
1557
1558 ProcBuf = AllocateZeroPool (Urb->Completed);
1559
1560 if (ProcBuf == NULL) {
1561 XhcUpdateAsyncRequest (Xhc, Urb);
1562 continue;
1563 }
1564
1565 CopyMem (ProcBuf, Urb->Data, Urb->Completed);
1566 }
1567
1568 //
1569 // Leave error recovery to its related device driver. A
1570 // common case of the error recovery is to re-submit the
1571 // interrupt transfer which is linked to the head of the
1572 // list. This function scans from head to tail. So the
1573 // re-submitted interrupt transfer's callback function
1574 // will not be called again in this round. Don't touch this
1575 // URB after the callback, it may have been removed by the
1576 // callback.
1577 //
1578 if (Urb->Callback != NULL) {
1579 //
1580 // Restore the old TPL, USB bus maybe connect device in
1581 // his callback. Some drivers may has a lower TPL restriction.
1582 //
1583 gBS->RestoreTPL (OldTpl);
1584 (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
1585 OldTpl = gBS->RaiseTPL (XHC_TPL);
1586 }
1587
1588 if (ProcBuf != NULL) {
1589 gBS->FreePool (ProcBuf);
1590 }
1591
1592 XhcUpdateAsyncRequest (Xhc, Urb);
1593 }
1594 gBS->RestoreTPL (OldTpl);
1595 }
1596
1597 /**
1598 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
1599
1600 @param Xhc The XHCI Instance.
1601 @param ParentRouteChart The route string pointed to the parent device if it exists.
1602 @param Port The port to be polled.
1603 @param PortState The port state.
1604
1605 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
1606 @retval Others Should not appear.
1607
1608 **/
1609 EFI_STATUS
1610 EFIAPI
1611 XhcPollPortStatusChange (
1612 IN USB_XHCI_INSTANCE *Xhc,
1613 IN USB_DEV_ROUTE ParentRouteChart,
1614 IN UINT8 Port,
1615 IN EFI_USB_PORT_STATUS *PortState
1616 )
1617 {
1618 EFI_STATUS Status;
1619 UINT8 Speed;
1620 UINT8 SlotId;
1621 USB_DEV_ROUTE RouteChart;
1622
1623 Status = EFI_SUCCESS;
1624
1625 if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {
1626 return EFI_SUCCESS;
1627 }
1628
1629 if (ParentRouteChart.Dword == 0) {
1630 RouteChart.Route.RouteString = 0;
1631 RouteChart.Route.RootPortNum = Port + 1;
1632 RouteChart.Route.TierNum = 1;
1633 } else {
1634 if(Port < 14) {
1635 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));
1636 } else {
1637 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));
1638 }
1639 RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
1640 RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
1641 }
1642
1643 SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
1644 if (SlotId != 0) {
1645 if (Xhc->HcCParams.Data.Csz == 0) {
1646 Status = XhcDisableSlotCmd (Xhc, SlotId);
1647 } else {
1648 Status = XhcDisableSlotCmd64 (Xhc, SlotId);
1649 }
1650 }
1651
1652 if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
1653 ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
1654 //
1655 // Has a device attached, Identify device speed after port is enabled.
1656 //
1657 Speed = EFI_USB_SPEED_FULL;
1658 if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {
1659 Speed = EFI_USB_SPEED_LOW;
1660 } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {
1661 Speed = EFI_USB_SPEED_HIGH;
1662 } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {
1663 Speed = EFI_USB_SPEED_SUPER;
1664 }
1665 //
1666 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
1667 //
1668 SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
1669 if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {
1670 if (Xhc->HcCParams.Data.Csz == 0) {
1671 Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);
1672 } else {
1673 Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);
1674 }
1675 }
1676 }
1677
1678 return Status;
1679 }
1680
1681
1682 /**
1683 Calculate the device context index by endpoint address and direction.
1684
1685 @param EpAddr The target endpoint number.
1686 @param Direction The direction of the target endpoint.
1687
1688 @return The device context index of endpoint.
1689
1690 **/
1691 UINT8
1692 XhcEndpointToDci (
1693 IN UINT8 EpAddr,
1694 IN UINT8 Direction
1695 )
1696 {
1697 UINT8 Index;
1698
1699 if (EpAddr == 0) {
1700 return 1;
1701 } else {
1702 Index = (UINT8) (2 * EpAddr);
1703 if (Direction == EfiUsbDataIn) {
1704 Index += 1;
1705 }
1706 return Index;
1707 }
1708 }
1709
1710 /**
1711 Find out the actual device address according to the requested device address from UsbBus.
1712
1713 @param Xhc The XHCI Instance.
1714 @param BusDevAddr The requested device address by UsbBus upper driver.
1715
1716 @return The actual device address assigned to the device.
1717
1718 **/
1719 UINT8
1720 EFIAPI
1721 XhcBusDevAddrToSlotId (
1722 IN USB_XHCI_INSTANCE *Xhc,
1723 IN UINT8 BusDevAddr
1724 )
1725 {
1726 UINT8 Index;
1727
1728 for (Index = 0; Index < 255; Index++) {
1729 if (Xhc->UsbDevContext[Index + 1].Enabled &&
1730 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
1731 (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
1732 break;
1733 }
1734 }
1735
1736 if (Index == 255) {
1737 return 0;
1738 }
1739
1740 return Xhc->UsbDevContext[Index + 1].SlotId;
1741 }
1742
1743 /**
1744 Find out the slot id according to the device's route string.
1745
1746 @param Xhc The XHCI Instance.
1747 @param RouteString The route string described the device location.
1748
1749 @return The slot id used by the device.
1750
1751 **/
1752 UINT8
1753 EFIAPI
1754 XhcRouteStringToSlotId (
1755 IN USB_XHCI_INSTANCE *Xhc,
1756 IN USB_DEV_ROUTE RouteString
1757 )
1758 {
1759 UINT8 Index;
1760
1761 for (Index = 0; Index < 255; Index++) {
1762 if (Xhc->UsbDevContext[Index + 1].Enabled &&
1763 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
1764 (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
1765 break;
1766 }
1767 }
1768
1769 if (Index == 255) {
1770 return 0;
1771 }
1772
1773 return Xhc->UsbDevContext[Index + 1].SlotId;
1774 }
1775
1776 /**
1777 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1778
1779 @param Xhc The XHCI Instance.
1780 @param EvtRing The event ring to sync.
1781
1782 @retval EFI_SUCCESS The event ring is synchronized successfully.
1783
1784 **/
1785 EFI_STATUS
1786 EFIAPI
1787 XhcSyncEventRing (
1788 IN USB_XHCI_INSTANCE *Xhc,
1789 IN EVENT_RING *EvtRing
1790 )
1791 {
1792 UINTN Index;
1793 TRB_TEMPLATE *EvtTrb1;
1794
1795 ASSERT (EvtRing != NULL);
1796
1797 //
1798 // Calculate the EventRingEnqueue and EventRingCCS.
1799 // Note: only support single Segment
1800 //
1801 EvtTrb1 = EvtRing->EventRingDequeue;
1802
1803 for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
1804 if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {
1805 break;
1806 }
1807
1808 EvtTrb1++;
1809
1810 if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
1811 EvtTrb1 = EvtRing->EventRingSeg0;
1812 EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
1813 }
1814 }
1815
1816 if (Index < EvtRing->TrbNumber) {
1817 EvtRing->EventRingEnqueue = EvtTrb1;
1818 } else {
1819 ASSERT (FALSE);
1820 }
1821
1822 return EFI_SUCCESS;
1823 }
1824
1825 /**
1826 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1827
1828 @param Xhc The XHCI Instance.
1829 @param TrsRing The transfer ring to sync.
1830
1831 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1832
1833 **/
1834 EFI_STATUS
1835 EFIAPI
1836 XhcSyncTrsRing (
1837 IN USB_XHCI_INSTANCE *Xhc,
1838 IN TRANSFER_RING *TrsRing
1839 )
1840 {
1841 UINTN Index;
1842 TRB_TEMPLATE *TrsTrb;
1843
1844 ASSERT (TrsRing != NULL);
1845 //
1846 // Calculate the latest RingEnqueue and RingPCS
1847 //
1848 TrsTrb = TrsRing->RingEnqueue;
1849 ASSERT (TrsTrb != NULL);
1850
1851 for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
1852 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
1853 break;
1854 }
1855 TrsTrb++;
1856 if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
1857 ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
1858 //
1859 // set cycle bit in Link TRB as normal
1860 //
1861 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
1862 //
1863 // Toggle PCS maintained by software
1864 //
1865 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
1866 TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
1867 }
1868 }
1869
1870 ASSERT (Index != TrsRing->TrbNumber);
1871
1872 if (TrsTrb != TrsRing->RingEnqueue) {
1873 TrsRing->RingEnqueue = TrsTrb;
1874 }
1875
1876 //
1877 // Clear the Trb context for enqueue, but reserve the PCS bit
1878 //
1879 TrsTrb->Parameter1 = 0;
1880 TrsTrb->Parameter2 = 0;
1881 TrsTrb->Status = 0;
1882 TrsTrb->RsvdZ1 = 0;
1883 TrsTrb->Type = 0;
1884 TrsTrb->Control = 0;
1885
1886 return EFI_SUCCESS;
1887 }
1888
1889 /**
1890 Check if there is a new generated event.
1891
1892 @param Xhc The XHCI Instance.
1893 @param EvtRing The event ring to check.
1894 @param NewEvtTrb The new event TRB found.
1895
1896 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1897 @retval EFI_NOT_READY The event ring has no new event.
1898
1899 **/
1900 EFI_STATUS
1901 EFIAPI
1902 XhcCheckNewEvent (
1903 IN USB_XHCI_INSTANCE *Xhc,
1904 IN EVENT_RING *EvtRing,
1905 OUT TRB_TEMPLATE **NewEvtTrb
1906 )
1907 {
1908 ASSERT (EvtRing != NULL);
1909
1910 *NewEvtTrb = EvtRing->EventRingDequeue;
1911
1912 if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
1913 return EFI_NOT_READY;
1914 }
1915
1916 EvtRing->EventRingDequeue++;
1917 //
1918 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
1919 //
1920 if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
1921 EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
1922 }
1923
1924 return EFI_SUCCESS;
1925 }
1926
1927 /**
1928 Ring the door bell to notify XHCI there is a transaction to be executed.
1929
1930 @param Xhc The XHCI Instance.
1931 @param SlotId The slot id of the target device.
1932 @param Dci The device context index of the target slot or endpoint.
1933
1934 @retval EFI_SUCCESS Successfully ring the door bell.
1935
1936 **/
1937 EFI_STATUS
1938 EFIAPI
1939 XhcRingDoorBell (
1940 IN USB_XHCI_INSTANCE *Xhc,
1941 IN UINT8 SlotId,
1942 IN UINT8 Dci
1943 )
1944 {
1945 if (SlotId == 0) {
1946 XhcWriteDoorBellReg (Xhc, 0, 0);
1947 } else {
1948 XhcWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);
1949 }
1950
1951 return EFI_SUCCESS;
1952 }
1953
1954 /**
1955 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
1956
1957 @param Xhc The XHCI Instance.
1958 @param Urb The URB to be rung.
1959
1960 @retval EFI_SUCCESS Successfully ring the door bell.
1961
1962 **/
1963 EFI_STATUS
1964 RingIntTransferDoorBell (
1965 IN USB_XHCI_INSTANCE *Xhc,
1966 IN URB *Urb
1967 )
1968 {
1969 UINT8 SlotId;
1970 UINT8 Dci;
1971
1972 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
1973 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
1974 XhcRingDoorBell (Xhc, SlotId, Dci);
1975 return EFI_SUCCESS;
1976 }
1977
1978 /**
1979 Assign and initialize the device slot for a new device.
1980
1981 @param Xhc The XHCI Instance.
1982 @param ParentRouteChart The route string pointed to the parent device.
1983 @param ParentPort The port at which the device is located.
1984 @param RouteChart The route string pointed to the device.
1985 @param DeviceSpeed The device speed.
1986
1987 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1988
1989 **/
1990 EFI_STATUS
1991 EFIAPI
1992 XhcInitializeDeviceSlot (
1993 IN USB_XHCI_INSTANCE *Xhc,
1994 IN USB_DEV_ROUTE ParentRouteChart,
1995 IN UINT16 ParentPort,
1996 IN USB_DEV_ROUTE RouteChart,
1997 IN UINT8 DeviceSpeed
1998 )
1999 {
2000 EFI_STATUS Status;
2001 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2002 INPUT_CONTEXT *InputContext;
2003 DEVICE_CONTEXT *OutputContext;
2004 TRANSFER_RING *EndpointTransferRing;
2005 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
2006 UINT8 DeviceAddress;
2007 CMD_TRB_ENABLE_SLOT CmdTrb;
2008 UINT8 SlotId;
2009 UINT8 ParentSlotId;
2010 DEVICE_CONTEXT *ParentDeviceContext;
2011 EFI_PHYSICAL_ADDRESS PhyAddr;
2012
2013 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
2014 CmdTrb.CycleBit = 1;
2015 CmdTrb.Type = TRB_TYPE_EN_SLOT;
2016
2017 Status = XhcCmdTransfer (
2018 Xhc,
2019 (TRB_TEMPLATE *) (UINTN) &CmdTrb,
2020 XHC_GENERIC_TIMEOUT,
2021 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2022 );
2023 if (EFI_ERROR (Status)) {
2024 DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
2025 return Status;
2026 }
2027 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
2028 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
2029 SlotId = (UINT8)EvtTrb->SlotId;
2030 ASSERT (SlotId != 0);
2031
2032 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
2033 Xhc->UsbDevContext[SlotId].Enabled = TRUE;
2034 Xhc->UsbDevContext[SlotId].SlotId = SlotId;
2035 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
2036 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
2037
2038 //
2039 // 4.3.3 Device Slot Initialization
2040 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2041 //
2042 InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
2043 ASSERT (InputContext != NULL);
2044 ASSERT (((UINTN) InputContext & 0x3F) == 0);
2045 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2046
2047 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
2048
2049 //
2050 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2051 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2052 // Context are affected by the command.
2053 //
2054 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
2055
2056 //
2057 // 3) Initialize the Input Slot Context data structure
2058 //
2059 InputContext->Slot.RouteString = RouteChart.Route.RouteString;
2060 InputContext->Slot.Speed = DeviceSpeed + 1;
2061 InputContext->Slot.ContextEntries = 1;
2062 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;
2063
2064 if (RouteChart.Route.RouteString) {
2065 //
2066 // The device is behind of hub device.
2067 //
2068 ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
2069 ASSERT (ParentSlotId != 0);
2070 //
2071 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2072 //
2073 ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
2074 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
2075 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
2076 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
2077 //
2078 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2079 // environment from Full/Low speed signaling environment for a device
2080 //
2081 InputContext->Slot.TTPortNum = ParentPort;
2082 InputContext->Slot.TTHubSlotId = ParentSlotId;
2083 }
2084 } else {
2085 //
2086 // Inherit the TT parameters from parent device.
2087 //
2088 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
2089 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
2090 //
2091 // If the device is a High speed device then down the speed to be the same as its parent Hub
2092 //
2093 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2094 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
2095 }
2096 }
2097 }
2098
2099 //
2100 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2101 //
2102 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
2103 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
2104 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
2105 //
2106 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2107 //
2108 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
2109
2110 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2111 InputContext->EP[0].MaxPacketSize = 512;
2112 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2113 InputContext->EP[0].MaxPacketSize = 64;
2114 } else {
2115 InputContext->EP[0].MaxPacketSize = 8;
2116 }
2117 //
2118 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2119 // 1KB, and Bulk and Isoch endpoints 3KB.
2120 //
2121 InputContext->EP[0].AverageTRBLength = 8;
2122 InputContext->EP[0].MaxBurstSize = 0;
2123 InputContext->EP[0].Interval = 0;
2124 InputContext->EP[0].MaxPStreams = 0;
2125 InputContext->EP[0].Mult = 0;
2126 InputContext->EP[0].CErr = 3;
2127
2128 //
2129 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2130 //
2131 PhyAddr = UsbHcGetPciAddrForHostAddr (
2132 Xhc->MemPool,
2133 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
2134 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2135 );
2136 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
2137 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2138
2139 //
2140 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2141 //
2142 OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
2143 ASSERT (OutputContext != NULL);
2144 ASSERT (((UINTN) OutputContext & 0x3F) == 0);
2145 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
2146
2147 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
2148 //
2149 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2150 // a pointer to the Output Device Context data structure (6.2.1).
2151 //
2152 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));
2153 //
2154 // Fill DCBAA with PCI device address
2155 //
2156 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
2157
2158 //
2159 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2160 // Context data structure described above.
2161 //
2162 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2163 // to device.
2164 //
2165 gBS->Stall (XHC_RESET_RECOVERY_DELAY);
2166 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
2167 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
2168 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
2169 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2170 CmdTrbAddr.CycleBit = 1;
2171 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
2172 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2173 Status = XhcCmdTransfer (
2174 Xhc,
2175 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
2176 XHC_GENERIC_TIMEOUT,
2177 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2178 );
2179 if (!EFI_ERROR (Status)) {
2180 DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
2181 DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
2182 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
2183 }
2184
2185 return Status;
2186 }
2187
2188 /**
2189 Assign and initialize the device slot for a new device.
2190
2191 @param Xhc The XHCI Instance.
2192 @param ParentRouteChart The route string pointed to the parent device.
2193 @param ParentPort The port at which the device is located.
2194 @param RouteChart The route string pointed to the device.
2195 @param DeviceSpeed The device speed.
2196
2197 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
2198
2199 **/
2200 EFI_STATUS
2201 EFIAPI
2202 XhcInitializeDeviceSlot64 (
2203 IN USB_XHCI_INSTANCE *Xhc,
2204 IN USB_DEV_ROUTE ParentRouteChart,
2205 IN UINT16 ParentPort,
2206 IN USB_DEV_ROUTE RouteChart,
2207 IN UINT8 DeviceSpeed
2208 )
2209 {
2210 EFI_STATUS Status;
2211 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2212 INPUT_CONTEXT_64 *InputContext;
2213 DEVICE_CONTEXT_64 *OutputContext;
2214 TRANSFER_RING *EndpointTransferRing;
2215 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
2216 UINT8 DeviceAddress;
2217 CMD_TRB_ENABLE_SLOT CmdTrb;
2218 UINT8 SlotId;
2219 UINT8 ParentSlotId;
2220 DEVICE_CONTEXT_64 *ParentDeviceContext;
2221 EFI_PHYSICAL_ADDRESS PhyAddr;
2222
2223 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
2224 CmdTrb.CycleBit = 1;
2225 CmdTrb.Type = TRB_TYPE_EN_SLOT;
2226
2227 Status = XhcCmdTransfer (
2228 Xhc,
2229 (TRB_TEMPLATE *) (UINTN) &CmdTrb,
2230 XHC_GENERIC_TIMEOUT,
2231 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2232 );
2233 if (EFI_ERROR (Status)) {
2234 DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
2235 return Status;
2236 }
2237 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
2238 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
2239 SlotId = (UINT8)EvtTrb->SlotId;
2240 ASSERT (SlotId != 0);
2241
2242 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
2243 Xhc->UsbDevContext[SlotId].Enabled = TRUE;
2244 Xhc->UsbDevContext[SlotId].SlotId = SlotId;
2245 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
2246 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
2247
2248 //
2249 // 4.3.3 Device Slot Initialization
2250 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2251 //
2252 InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
2253 ASSERT (InputContext != NULL);
2254 ASSERT (((UINTN) InputContext & 0x3F) == 0);
2255 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
2256
2257 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
2258
2259 //
2260 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2261 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2262 // Context are affected by the command.
2263 //
2264 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
2265
2266 //
2267 // 3) Initialize the Input Slot Context data structure
2268 //
2269 InputContext->Slot.RouteString = RouteChart.Route.RouteString;
2270 InputContext->Slot.Speed = DeviceSpeed + 1;
2271 InputContext->Slot.ContextEntries = 1;
2272 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;
2273
2274 if (RouteChart.Route.RouteString) {
2275 //
2276 // The device is behind of hub device.
2277 //
2278 ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
2279 ASSERT (ParentSlotId != 0);
2280 //
2281 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2282 //
2283 ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
2284 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
2285 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
2286 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
2287 //
2288 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2289 // environment from Full/Low speed signaling environment for a device
2290 //
2291 InputContext->Slot.TTPortNum = ParentPort;
2292 InputContext->Slot.TTHubSlotId = ParentSlotId;
2293 }
2294 } else {
2295 //
2296 // Inherit the TT parameters from parent device.
2297 //
2298 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
2299 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
2300 //
2301 // If the device is a High speed device then down the speed to be the same as its parent Hub
2302 //
2303 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2304 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
2305 }
2306 }
2307 }
2308
2309 //
2310 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2311 //
2312 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
2313 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
2314 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
2315 //
2316 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2317 //
2318 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
2319
2320 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2321 InputContext->EP[0].MaxPacketSize = 512;
2322 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2323 InputContext->EP[0].MaxPacketSize = 64;
2324 } else {
2325 InputContext->EP[0].MaxPacketSize = 8;
2326 }
2327 //
2328 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2329 // 1KB, and Bulk and Isoch endpoints 3KB.
2330 //
2331 InputContext->EP[0].AverageTRBLength = 8;
2332 InputContext->EP[0].MaxBurstSize = 0;
2333 InputContext->EP[0].Interval = 0;
2334 InputContext->EP[0].MaxPStreams = 0;
2335 InputContext->EP[0].Mult = 0;
2336 InputContext->EP[0].CErr = 3;
2337
2338 //
2339 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2340 //
2341 PhyAddr = UsbHcGetPciAddrForHostAddr (
2342 Xhc->MemPool,
2343 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
2344 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2345 );
2346 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
2347 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2348
2349 //
2350 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2351 //
2352 OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
2353 ASSERT (OutputContext != NULL);
2354 ASSERT (((UINTN) OutputContext & 0x3F) == 0);
2355 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
2356
2357 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
2358 //
2359 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2360 // a pointer to the Output Device Context data structure (6.2.1).
2361 //
2362 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));
2363 //
2364 // Fill DCBAA with PCI device address
2365 //
2366 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
2367
2368 //
2369 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2370 // Context data structure described above.
2371 //
2372 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2373 // to device.
2374 //
2375 gBS->Stall (XHC_RESET_RECOVERY_DELAY);
2376 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
2377 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
2378 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
2379 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2380 CmdTrbAddr.CycleBit = 1;
2381 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
2382 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2383 Status = XhcCmdTransfer (
2384 Xhc,
2385 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
2386 XHC_GENERIC_TIMEOUT,
2387 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2388 );
2389 if (!EFI_ERROR (Status)) {
2390 DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
2391 DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
2392 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
2393 }
2394 return Status;
2395 }
2396
2397
2398 /**
2399 Disable the specified device slot.
2400
2401 @param Xhc The XHCI Instance.
2402 @param SlotId The slot id to be disabled.
2403
2404 @retval EFI_SUCCESS Successfully disable the device slot.
2405
2406 **/
2407 EFI_STATUS
2408 EFIAPI
2409 XhcDisableSlotCmd (
2410 IN USB_XHCI_INSTANCE *Xhc,
2411 IN UINT8 SlotId
2412 )
2413 {
2414 EFI_STATUS Status;
2415 TRB_TEMPLATE *EvtTrb;
2416 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;
2417 UINT8 Index;
2418 VOID *RingSeg;
2419
2420 //
2421 // Disable the device slots occupied by these devices on its downstream ports.
2422 // Entry 0 is reserved.
2423 //
2424 for (Index = 0; Index < 255; Index++) {
2425 if (!Xhc->UsbDevContext[Index + 1].Enabled ||
2426 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
2427 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
2428 continue;
2429 }
2430
2431 Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
2432
2433 if (EFI_ERROR (Status)) {
2434 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2435 Xhc->UsbDevContext[Index + 1].SlotId = 0;
2436 }
2437 }
2438
2439 //
2440 // Construct the disable slot command
2441 //
2442 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
2443
2444 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
2445 CmdTrbDisSlot.CycleBit = 1;
2446 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
2447 CmdTrbDisSlot.SlotId = SlotId;
2448 Status = XhcCmdTransfer (
2449 Xhc,
2450 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
2451 XHC_GENERIC_TIMEOUT,
2452 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2453 );
2454 if (EFI_ERROR (Status)) {
2455 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
2456 return Status;
2457 }
2458 //
2459 // Free the slot's device context entry
2460 //
2461 Xhc->DCBAA[SlotId] = 0;
2462
2463 //
2464 // Free the slot related data structure
2465 //
2466 for (Index = 0; Index < 31; Index++) {
2467 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
2468 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
2469 if (RingSeg != NULL) {
2470 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
2471 }
2472 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
2473 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
2474 }
2475 }
2476
2477 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
2478 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
2479 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
2480 }
2481 }
2482
2483 if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
2484 FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
2485 }
2486
2487 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
2488 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
2489 }
2490
2491 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
2492 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
2493 }
2494 //
2495 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2496 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2497 // remove urb from XHCI's asynchronous transfer list.
2498 //
2499 Xhc->UsbDevContext[SlotId].Enabled = FALSE;
2500 Xhc->UsbDevContext[SlotId].SlotId = 0;
2501
2502 return Status;
2503 }
2504
2505 /**
2506 Disable the specified device slot.
2507
2508 @param Xhc The XHCI Instance.
2509 @param SlotId The slot id to be disabled.
2510
2511 @retval EFI_SUCCESS Successfully disable the device slot.
2512
2513 **/
2514 EFI_STATUS
2515 EFIAPI
2516 XhcDisableSlotCmd64 (
2517 IN USB_XHCI_INSTANCE *Xhc,
2518 IN UINT8 SlotId
2519 )
2520 {
2521 EFI_STATUS Status;
2522 TRB_TEMPLATE *EvtTrb;
2523 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;
2524 UINT8 Index;
2525 VOID *RingSeg;
2526
2527 //
2528 // Disable the device slots occupied by these devices on its downstream ports.
2529 // Entry 0 is reserved.
2530 //
2531 for (Index = 0; Index < 255; Index++) {
2532 if (!Xhc->UsbDevContext[Index + 1].Enabled ||
2533 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
2534 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
2535 continue;
2536 }
2537
2538 Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
2539
2540 if (EFI_ERROR (Status)) {
2541 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2542 Xhc->UsbDevContext[Index + 1].SlotId = 0;
2543 }
2544 }
2545
2546 //
2547 // Construct the disable slot command
2548 //
2549 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
2550
2551 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
2552 CmdTrbDisSlot.CycleBit = 1;
2553 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
2554 CmdTrbDisSlot.SlotId = SlotId;
2555 Status = XhcCmdTransfer (
2556 Xhc,
2557 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
2558 XHC_GENERIC_TIMEOUT,
2559 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2560 );
2561 if (EFI_ERROR (Status)) {
2562 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
2563 return Status;
2564 }
2565 //
2566 // Free the slot's device context entry
2567 //
2568 Xhc->DCBAA[SlotId] = 0;
2569
2570 //
2571 // Free the slot related data structure
2572 //
2573 for (Index = 0; Index < 31; Index++) {
2574 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
2575 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
2576 if (RingSeg != NULL) {
2577 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
2578 }
2579 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
2580 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
2581 }
2582 }
2583
2584 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
2585 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
2586 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
2587 }
2588 }
2589
2590 if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
2591 FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
2592 }
2593
2594 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
2595 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
2596 }
2597
2598 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
2599 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
2600 }
2601 //
2602 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2603 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2604 // remove urb from XHCI's asynchronous transfer list.
2605 //
2606 Xhc->UsbDevContext[SlotId].Enabled = FALSE;
2607 Xhc->UsbDevContext[SlotId].SlotId = 0;
2608
2609 return Status;
2610 }
2611
2612 /**
2613 Initialize endpoint context in input context.
2614
2615 @param Xhc The XHCI Instance.
2616 @param SlotId The slot id to be configured.
2617 @param DeviceSpeed The device's speed.
2618 @param InputContext The pointer to the input context.
2619 @param IfDesc The pointer to the usb device interface descriptor.
2620
2621 @return The maximum device context index of endpoint.
2622
2623 **/
2624 UINT8
2625 EFIAPI
2626 XhcInitializeEndpointContext (
2627 IN USB_XHCI_INSTANCE *Xhc,
2628 IN UINT8 SlotId,
2629 IN UINT8 DeviceSpeed,
2630 IN INPUT_CONTEXT *InputContext,
2631 IN USB_INTERFACE_DESCRIPTOR *IfDesc
2632 )
2633 {
2634 USB_ENDPOINT_DESCRIPTOR *EpDesc;
2635 UINTN NumEp;
2636 UINTN EpIndex;
2637 UINT8 EpAddr;
2638 UINT8 Direction;
2639 UINT8 Dci;
2640 UINT8 MaxDci;
2641 EFI_PHYSICAL_ADDRESS PhyAddr;
2642 UINT8 Interval;
2643 TRANSFER_RING *EndpointTransferRing;
2644
2645 MaxDci = 0;
2646
2647 NumEp = IfDesc->NumEndpoints;
2648
2649 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
2650 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
2651 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
2652 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2653 }
2654
2655 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
2656 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2657 continue;
2658 }
2659
2660 EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
2661 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
2662
2663 Dci = XhcEndpointToDci (EpAddr, Direction);
2664 ASSERT (Dci < 32);
2665 if (Dci > MaxDci) {
2666 MaxDci = Dci;
2667 }
2668
2669 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
2670 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
2671
2672 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2673 //
2674 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2675 //
2676 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2677 } else {
2678 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2679 }
2680
2681 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
2682 case USB_ENDPOINT_BULK:
2683 if (Direction == EfiUsbDataIn) {
2684 InputContext->EP[Dci-1].CErr = 3;
2685 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
2686 } else {
2687 InputContext->EP[Dci-1].CErr = 3;
2688 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
2689 }
2690
2691 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2692 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2693 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2694 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2695 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2696 DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created BULK ring [%p~%p)\n",
2697 EpDesc->EndpointAddress,
2698 EndpointTransferRing->RingSeg0,
2699 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2700 ));
2701 }
2702
2703 break;
2704 case USB_ENDPOINT_ISO:
2705 if (Direction == EfiUsbDataIn) {
2706 InputContext->EP[Dci-1].CErr = 0;
2707 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
2708 } else {
2709 InputContext->EP[Dci-1].CErr = 0;
2710 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
2711 }
2712 //
2713 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2714 // Refer to XHCI 1.1 spec section 6.2.3.6.
2715 //
2716 if (DeviceSpeed == EFI_USB_SPEED_FULL) {
2717 Interval = EpDesc->Interval;
2718 ASSERT (Interval >= 1 && Interval <= 16);
2719 InputContext->EP[Dci-1].Interval = Interval + 2;
2720 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2721 Interval = EpDesc->Interval;
2722 ASSERT (Interval >= 1 && Interval <= 16);
2723 InputContext->EP[Dci-1].Interval = Interval - 1;
2724 }
2725
2726 //
2727 // Do not support isochronous transfer now.
2728 //
2729 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2730 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2731 continue;
2732 case USB_ENDPOINT_INTERRUPT:
2733 if (Direction == EfiUsbDataIn) {
2734 InputContext->EP[Dci-1].CErr = 3;
2735 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
2736 } else {
2737 InputContext->EP[Dci-1].CErr = 3;
2738 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
2739 }
2740 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2741 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
2742 //
2743 // Get the bInterval from descriptor and init the the interval field of endpoint context
2744 //
2745 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
2746 Interval = EpDesc->Interval;
2747 //
2748 // Calculate through the bInterval field of Endpoint descriptor.
2749 //
2750 ASSERT (Interval != 0);
2751 InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
2752 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2753 Interval = EpDesc->Interval;
2754 ASSERT (Interval >= 1 && Interval <= 16);
2755 //
2756 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2757 //
2758 InputContext->EP[Dci-1].Interval = Interval - 1;
2759 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2760 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;
2761 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2762 InputContext->EP[Dci-1].CErr = 3;
2763 }
2764
2765 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2766 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2767 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2768 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2769 DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created INT ring [%p~%p)\n",
2770 EpDesc->EndpointAddress,
2771 EndpointTransferRing->RingSeg0,
2772 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2773 ));
2774 }
2775 break;
2776
2777 case USB_ENDPOINT_CONTROL:
2778 //
2779 // Do not support control transfer now.
2780 //
2781 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2782 default:
2783 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
2784 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2785 continue;
2786 }
2787
2788 PhyAddr = UsbHcGetPciAddrForHostAddr (
2789 Xhc->MemPool,
2790 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
2791 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2792 );
2793 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
2794 PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
2795 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
2796 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2797
2798 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2799 }
2800
2801 return MaxDci;
2802 }
2803
2804 /**
2805 Initialize endpoint context in input context.
2806
2807 @param Xhc The XHCI Instance.
2808 @param SlotId The slot id to be configured.
2809 @param DeviceSpeed The device's speed.
2810 @param InputContext The pointer to the input context.
2811 @param IfDesc The pointer to the usb device interface descriptor.
2812
2813 @return The maximum device context index of endpoint.
2814
2815 **/
2816 UINT8
2817 EFIAPI
2818 XhcInitializeEndpointContext64 (
2819 IN USB_XHCI_INSTANCE *Xhc,
2820 IN UINT8 SlotId,
2821 IN UINT8 DeviceSpeed,
2822 IN INPUT_CONTEXT_64 *InputContext,
2823 IN USB_INTERFACE_DESCRIPTOR *IfDesc
2824 )
2825 {
2826 USB_ENDPOINT_DESCRIPTOR *EpDesc;
2827 UINTN NumEp;
2828 UINTN EpIndex;
2829 UINT8 EpAddr;
2830 UINT8 Direction;
2831 UINT8 Dci;
2832 UINT8 MaxDci;
2833 EFI_PHYSICAL_ADDRESS PhyAddr;
2834 UINT8 Interval;
2835 TRANSFER_RING *EndpointTransferRing;
2836
2837 MaxDci = 0;
2838
2839 NumEp = IfDesc->NumEndpoints;
2840
2841 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
2842 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
2843 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
2844 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2845 }
2846
2847 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
2848 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2849 continue;
2850 }
2851
2852 EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
2853 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
2854
2855 Dci = XhcEndpointToDci (EpAddr, Direction);
2856 ASSERT (Dci < 32);
2857 if (Dci > MaxDci) {
2858 MaxDci = Dci;
2859 }
2860
2861 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
2862 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
2863
2864 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2865 //
2866 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2867 //
2868 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2869 } else {
2870 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2871 }
2872
2873 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
2874 case USB_ENDPOINT_BULK:
2875 if (Direction == EfiUsbDataIn) {
2876 InputContext->EP[Dci-1].CErr = 3;
2877 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
2878 } else {
2879 InputContext->EP[Dci-1].CErr = 3;
2880 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
2881 }
2882
2883 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2884 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2885 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2886 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2887 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2888 DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
2889 EpDesc->EndpointAddress,
2890 EndpointTransferRing->RingSeg0,
2891 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2892 ));
2893 }
2894
2895 break;
2896 case USB_ENDPOINT_ISO:
2897 if (Direction == EfiUsbDataIn) {
2898 InputContext->EP[Dci-1].CErr = 0;
2899 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
2900 } else {
2901 InputContext->EP[Dci-1].CErr = 0;
2902 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
2903 }
2904 //
2905 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2906 // Refer to XHCI 1.1 spec section 6.2.3.6.
2907 //
2908 if (DeviceSpeed == EFI_USB_SPEED_FULL) {
2909 Interval = EpDesc->Interval;
2910 ASSERT (Interval >= 1 && Interval <= 16);
2911 InputContext->EP[Dci-1].Interval = Interval + 2;
2912 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2913 Interval = EpDesc->Interval;
2914 ASSERT (Interval >= 1 && Interval <= 16);
2915 InputContext->EP[Dci-1].Interval = Interval - 1;
2916 }
2917
2918 //
2919 // Do not support isochronous transfer now.
2920 //
2921 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2922 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2923 continue;
2924 case USB_ENDPOINT_INTERRUPT:
2925 if (Direction == EfiUsbDataIn) {
2926 InputContext->EP[Dci-1].CErr = 3;
2927 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
2928 } else {
2929 InputContext->EP[Dci-1].CErr = 3;
2930 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
2931 }
2932 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2933 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
2934 //
2935 // Get the bInterval from descriptor and init the the interval field of endpoint context
2936 //
2937 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
2938 Interval = EpDesc->Interval;
2939 //
2940 // Calculate through the bInterval field of Endpoint descriptor.
2941 //
2942 ASSERT (Interval != 0);
2943 InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
2944 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2945 Interval = EpDesc->Interval;
2946 ASSERT (Interval >= 1 && Interval <= 16);
2947 //
2948 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2949 //
2950 InputContext->EP[Dci-1].Interval = Interval - 1;
2951 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2952 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;
2953 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2954 InputContext->EP[Dci-1].CErr = 3;
2955 }
2956
2957 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2958 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2959 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2960 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2961 DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created INT ring [%p~%p)\n",
2962 EpDesc->EndpointAddress,
2963 EndpointTransferRing->RingSeg0,
2964 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2965 ));
2966 }
2967 break;
2968
2969 case USB_ENDPOINT_CONTROL:
2970 //
2971 // Do not support control transfer now.
2972 //
2973 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2974 default:
2975 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
2976 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2977 continue;
2978 }
2979
2980 PhyAddr = UsbHcGetPciAddrForHostAddr (
2981 Xhc->MemPool,
2982 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
2983 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2984 );
2985 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
2986 PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
2987 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
2988 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2989
2990 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2991 }
2992
2993 return MaxDci;
2994 }
2995
2996 /**
2997 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2998
2999 @param Xhc The XHCI Instance.
3000 @param SlotId The slot id to be configured.
3001 @param DeviceSpeed The device's speed.
3002 @param ConfigDesc The pointer to the usb device configuration descriptor.
3003
3004 @retval EFI_SUCCESS Successfully configure all the device endpoints.
3005
3006 **/
3007 EFI_STATUS
3008 EFIAPI
3009 XhcSetConfigCmd (
3010 IN USB_XHCI_INSTANCE *Xhc,
3011 IN UINT8 SlotId,
3012 IN UINT8 DeviceSpeed,
3013 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
3014 )
3015 {
3016 EFI_STATUS Status;
3017 USB_INTERFACE_DESCRIPTOR *IfDesc;
3018 UINT8 Index;
3019 UINT8 Dci;
3020 UINT8 MaxDci;
3021 EFI_PHYSICAL_ADDRESS PhyAddr;
3022
3023 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3024 INPUT_CONTEXT *InputContext;
3025 DEVICE_CONTEXT *OutputContext;
3026 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3027 //
3028 // 4.6.6 Configure Endpoint
3029 //
3030 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3031 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3032 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
3033 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
3034
3035 ASSERT (ConfigDesc != NULL);
3036
3037 MaxDci = 0;
3038
3039 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
3040 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
3041 while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
3042 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3043 }
3044
3045 if (IfDesc->Length < sizeof (USB_INTERFACE_DESCRIPTOR)) {
3046 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3047 continue;
3048 }
3049
3050 Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);
3051 if (Dci > MaxDci) {
3052 MaxDci = Dci;
3053 }
3054
3055 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3056 }
3057
3058 InputContext->InputControlContext.Dword2 |= BIT0;
3059 InputContext->Slot.ContextEntries = MaxDci;
3060 //
3061 // configure endpoint
3062 //
3063 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3064 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
3065 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3066 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3067 CmdTrbCfgEP.CycleBit = 1;
3068 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3069 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3070 DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
3071 Status = XhcCmdTransfer (
3072 Xhc,
3073 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3074 XHC_GENERIC_TIMEOUT,
3075 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3076 );
3077 if (EFI_ERROR (Status)) {
3078 DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
3079 } else {
3080 Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
3081 }
3082
3083 return Status;
3084 }
3085
3086 /**
3087 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
3088
3089 @param Xhc The XHCI Instance.
3090 @param SlotId The slot id to be configured.
3091 @param DeviceSpeed The device's speed.
3092 @param ConfigDesc The pointer to the usb device configuration descriptor.
3093
3094 @retval EFI_SUCCESS Successfully configure all the device endpoints.
3095
3096 **/
3097 EFI_STATUS
3098 EFIAPI
3099 XhcSetConfigCmd64 (
3100 IN USB_XHCI_INSTANCE *Xhc,
3101 IN UINT8 SlotId,
3102 IN UINT8 DeviceSpeed,
3103 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
3104 )
3105 {
3106 EFI_STATUS Status;
3107 USB_INTERFACE_DESCRIPTOR *IfDesc;
3108 UINT8 Index;
3109 UINT8 Dci;
3110 UINT8 MaxDci;
3111 EFI_PHYSICAL_ADDRESS PhyAddr;
3112
3113 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3114 INPUT_CONTEXT_64 *InputContext;
3115 DEVICE_CONTEXT_64 *OutputContext;
3116 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3117 //
3118 // 4.6.6 Configure Endpoint
3119 //
3120 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3121 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3122 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
3123 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
3124
3125 ASSERT (ConfigDesc != NULL);
3126
3127 MaxDci = 0;
3128
3129 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
3130 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
3131 while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
3132 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3133 }
3134
3135 if (IfDesc->Length < sizeof (USB_INTERFACE_DESCRIPTOR)) {
3136 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3137 continue;
3138 }
3139
3140 Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);
3141 if (Dci > MaxDci) {
3142 MaxDci = Dci;
3143 }
3144
3145 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3146 }
3147
3148 InputContext->InputControlContext.Dword2 |= BIT0;
3149 InputContext->Slot.ContextEntries = MaxDci;
3150 //
3151 // configure endpoint
3152 //
3153 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3154 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
3155 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3156 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3157 CmdTrbCfgEP.CycleBit = 1;
3158 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3159 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3160 DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
3161 Status = XhcCmdTransfer (
3162 Xhc,
3163 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3164 XHC_GENERIC_TIMEOUT,
3165 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3166 );
3167 if (EFI_ERROR (Status)) {
3168 DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
3169 } else {
3170 Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
3171 }
3172
3173 return Status;
3174 }
3175
3176 /**
3177 Stop endpoint through XHCI's Stop_Endpoint cmd.
3178
3179 @param Xhc The XHCI Instance.
3180 @param SlotId The slot id to be configured.
3181 @param Dci The device context index of endpoint.
3182 @param PendingUrb The pending URB to check completion status when stopping the end point.
3183
3184 @retval EFI_SUCCESS Stop endpoint successfully.
3185 @retval Others Failed to stop endpoint.
3186
3187 **/
3188 EFI_STATUS
3189 EFIAPI
3190 XhcStopEndpoint (
3191 IN USB_XHCI_INSTANCE *Xhc,
3192 IN UINT8 SlotId,
3193 IN UINT8 Dci,
3194 IN URB *PendingUrb OPTIONAL
3195 )
3196 {
3197 EFI_STATUS Status;
3198 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3199 CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
3200
3201 DEBUG ((EFI_D_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
3202
3203 //
3204 // When XhcCheckUrbResult waits for the Stop_Endpoint completion, it also checks
3205 // the PendingUrb completion status, because it's possible that the PendingUrb is
3206 // finished just before stopping the end point, but after the looping check.
3207 //
3208 // The PendingUrb could be passed to XhcCmdTransfer to XhcExecTransfer to XhcCheckUrbResult
3209 // through function parameter, but That will cause every consumer of XhcCmdTransfer,
3210 // XhcExecTransfer and XhcCheckUrbResult pass a NULL PendingUrb.
3211 // But actually only XhcCheckUrbResult is aware of the PendingUrb.
3212 // So we choose to save the PendingUrb into the USB_XHCI_INSTANCE and use it in XhcCheckUrbResult.
3213 //
3214 ASSERT (Xhc->PendingUrb == NULL);
3215 Xhc->PendingUrb = PendingUrb;
3216 //
3217 // Reset the URB result from Timeout to NoError.
3218 // The USB result will be:
3219 // changed to Timeout when Stop/StopInvalidLength Transfer Event is received, or
3220 // remain NoError when Success/ShortPacket Transfer Event is received.
3221 //
3222 if (PendingUrb != NULL) {
3223 PendingUrb->Result = EFI_USB_NOERROR;
3224 }
3225
3226 //
3227 // Send stop endpoint command to transit Endpoint from running to stop state
3228 //
3229 ZeroMem (&CmdTrbStopED, sizeof (CmdTrbStopED));
3230 CmdTrbStopED.CycleBit = 1;
3231 CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;
3232 CmdTrbStopED.EDID = Dci;
3233 CmdTrbStopED.SlotId = SlotId;
3234 Status = XhcCmdTransfer (
3235 Xhc,
3236 (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,
3237 XHC_GENERIC_TIMEOUT,
3238 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3239 );
3240 if (EFI_ERROR(Status)) {
3241 DEBUG ((EFI_D_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
3242 }
3243
3244 Xhc->PendingUrb = NULL;
3245
3246 return Status;
3247 }
3248
3249 /**
3250 Reset endpoint through XHCI's Reset_Endpoint cmd.
3251
3252 @param Xhc The XHCI Instance.
3253 @param SlotId The slot id to be configured.
3254 @param Dci The device context index of endpoint.
3255
3256 @retval EFI_SUCCESS Reset endpoint successfully.
3257 @retval Others Failed to reset endpoint.
3258
3259 **/
3260 EFI_STATUS
3261 EFIAPI
3262 XhcResetEndpoint (
3263 IN USB_XHCI_INSTANCE *Xhc,
3264 IN UINT8 SlotId,
3265 IN UINT8 Dci
3266 )
3267 {
3268 EFI_STATUS Status;
3269 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3270 CMD_TRB_RESET_ENDPOINT CmdTrbResetED;
3271
3272 DEBUG ((EFI_D_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
3273
3274 //
3275 // Send stop endpoint command to transit Endpoint from running to stop state
3276 //
3277 ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));
3278 CmdTrbResetED.CycleBit = 1;
3279 CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
3280 CmdTrbResetED.EDID = Dci;
3281 CmdTrbResetED.SlotId = SlotId;
3282 Status = XhcCmdTransfer (
3283 Xhc,
3284 (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,
3285 XHC_GENERIC_TIMEOUT,
3286 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3287 );
3288 if (EFI_ERROR(Status)) {
3289 DEBUG ((EFI_D_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
3290 }
3291
3292 return Status;
3293 }
3294
3295 /**
3296 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
3297
3298 @param Xhc The XHCI Instance.
3299 @param SlotId The slot id to be configured.
3300 @param Dci The device context index of endpoint.
3301 @param Urb The dequeue pointer of the transfer ring specified
3302 by the urb to be updated.
3303
3304 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
3305 @retval Others Failed to set transfer ring dequeue pointer.
3306
3307 **/
3308 EFI_STATUS
3309 EFIAPI
3310 XhcSetTrDequeuePointer (
3311 IN USB_XHCI_INSTANCE *Xhc,
3312 IN UINT8 SlotId,
3313 IN UINT8 Dci,
3314 IN URB *Urb
3315 )
3316 {
3317 EFI_STATUS Status;
3318 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3319 CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;
3320 EFI_PHYSICAL_ADDRESS PhyAddr;
3321
3322 DEBUG ((EFI_D_INFO, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
3323
3324 //
3325 // Send stop endpoint command to transit Endpoint from running to stop state
3326 //
3327 ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
3328 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
3329 CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
3330 CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3331 CmdSetTRDeq.CycleBit = 1;
3332 CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
3333 CmdSetTRDeq.Endpoint = Dci;
3334 CmdSetTRDeq.SlotId = SlotId;
3335 Status = XhcCmdTransfer (
3336 Xhc,
3337 (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,
3338 XHC_GENERIC_TIMEOUT,
3339 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3340 );
3341 if (EFI_ERROR(Status)) {
3342 DEBUG ((EFI_D_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
3343 }
3344
3345 return Status;
3346 }
3347
3348 /**
3349 Set interface through XHCI's Configure_Endpoint cmd.
3350
3351 @param Xhc The XHCI Instance.
3352 @param SlotId The slot id to be configured.
3353 @param DeviceSpeed The device's speed.
3354 @param ConfigDesc The pointer to the usb device configuration descriptor.
3355 @param Request USB device request to send.
3356
3357 @retval EFI_SUCCESS Successfully set interface.
3358
3359 **/
3360 EFI_STATUS
3361 EFIAPI
3362 XhcSetInterface (
3363 IN USB_XHCI_INSTANCE *Xhc,
3364 IN UINT8 SlotId,
3365 IN UINT8 DeviceSpeed,
3366 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
3367 IN EFI_USB_DEVICE_REQUEST *Request
3368 )
3369 {
3370 EFI_STATUS Status;
3371 USB_INTERFACE_DESCRIPTOR *IfDescActive;
3372 USB_INTERFACE_DESCRIPTOR *IfDescSet;
3373 USB_INTERFACE_DESCRIPTOR *IfDesc;
3374 USB_ENDPOINT_DESCRIPTOR *EpDesc;
3375 UINTN NumEp;
3376 UINTN EpIndex;
3377 UINT8 EpAddr;
3378 UINT8 Direction;
3379 UINT8 Dci;
3380 UINT8 MaxDci;
3381 EFI_PHYSICAL_ADDRESS PhyAddr;
3382 VOID *RingSeg;
3383
3384 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3385 INPUT_CONTEXT *InputContext;
3386 DEVICE_CONTEXT *OutputContext;
3387 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3388
3389 Status = EFI_SUCCESS;
3390
3391 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3392 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3393 //
3394 // XHCI 4.6.6 Configure Endpoint
3395 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3396 // Context and Add Context flags as follows:
3397 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3398 // Context and Add Context flags to '0'.
3399 //
3400 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3401 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3402 //
3403 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
3404 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
3405
3406 ASSERT (ConfigDesc != NULL);
3407
3408 MaxDci = 0;
3409
3410 IfDescActive = NULL;
3411 IfDescSet = NULL;
3412
3413 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
3414 while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
3415 if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
3416 if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
3417 if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
3418 //
3419 // Find out the active interface descriptor.
3420 //
3421 IfDescActive = IfDesc;
3422 } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
3423 //
3424 // Find out the interface descriptor to set.
3425 //
3426 IfDescSet = IfDesc;
3427 }
3428 }
3429 }
3430 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3431 }
3432
3433 //
3434 // XHCI 4.6.6 Configure Endpoint
3435 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3436 // Context and Add Context flags as follows:
3437 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3438 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3439 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3440 // the Drop Context flag to '1' and Add Context flag to '0'.
3441 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3442 // and Add Context flags shall be set to '1'.
3443 //
3444 // Below codes are to cover 2), 3) and 4).
3445 //
3446
3447 if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
3448 NumEp = IfDescActive->NumEndpoints;
3449 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
3450 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
3451 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
3452 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3453 }
3454
3455 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
3456 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3457 continue;
3458 }
3459
3460 EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
3461 Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
3462
3463 Dci = XhcEndpointToDci (EpAddr, Direction);
3464 ASSERT (Dci < 32);
3465 if (Dci > MaxDci) {
3466 MaxDci = Dci;
3467 }
3468 //
3469 // XHCI 4.3.6 - Setting Alternate Interfaces
3470 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3471 //
3472 Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);
3473 if (EFI_ERROR (Status)) {
3474 return Status;
3475 }
3476 //
3477 // XHCI 4.3.6 - Setting Alternate Interfaces
3478 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3479 //
3480 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {
3481 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;
3482 if (RingSeg != NULL) {
3483 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
3484 }
3485 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
3486 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
3487 }
3488
3489 //
3490 // Set the Drop Context flag to '1'.
3491 //
3492 InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);
3493
3494 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3495 }
3496
3497 //
3498 // XHCI 4.3.6 - Setting Alternate Interfaces
3499 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3500 // Interface setting, to '0'.
3501 //
3502 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3503 //
3504
3505 //
3506 // XHCI 4.3.6 - Setting Alternate Interfaces
3507 // 4) For each endpoint enabled by the Configure Endpoint Command:
3508 // a. Allocate a Transfer Ring.
3509 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3510 // c. Initialize the Endpoint Context data structure.
3511 //
3512 Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);
3513 if (Dci > MaxDci) {
3514 MaxDci = Dci;
3515 }
3516
3517 InputContext->InputControlContext.Dword2 |= BIT0;
3518 InputContext->Slot.ContextEntries = MaxDci;
3519 //
3520 // XHCI 4.3.6 - Setting Alternate Interfaces
3521 // 5) Issue and successfully complete a Configure Endpoint Command.
3522 //
3523 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3524 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
3525 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3526 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3527 CmdTrbCfgEP.CycleBit = 1;
3528 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3529 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3530 DEBUG ((EFI_D_INFO, "SetInterface: Configure Endpoint\n"));
3531 Status = XhcCmdTransfer (
3532 Xhc,
3533 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3534 XHC_GENERIC_TIMEOUT,
3535 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3536 );
3537 if (EFI_ERROR (Status)) {
3538 DEBUG ((EFI_D_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
3539 } else {
3540 //
3541 // Update the active AlternateSetting.
3542 //
3543 Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
3544 }
3545 }
3546
3547 return Status;
3548 }
3549
3550 /**
3551 Set interface through XHCI's Configure_Endpoint cmd.
3552
3553 @param Xhc The XHCI Instance.
3554 @param SlotId The slot id to be configured.
3555 @param DeviceSpeed The device's speed.
3556 @param ConfigDesc The pointer to the usb device configuration descriptor.
3557 @param Request USB device request to send.
3558
3559 @retval EFI_SUCCESS Successfully set interface.
3560
3561 **/
3562 EFI_STATUS
3563 EFIAPI
3564 XhcSetInterface64 (
3565 IN USB_XHCI_INSTANCE *Xhc,
3566 IN UINT8 SlotId,
3567 IN UINT8 DeviceSpeed,
3568 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
3569 IN EFI_USB_DEVICE_REQUEST *Request
3570 )
3571 {
3572 EFI_STATUS Status;
3573 USB_INTERFACE_DESCRIPTOR *IfDescActive;
3574 USB_INTERFACE_DESCRIPTOR *IfDescSet;
3575 USB_INTERFACE_DESCRIPTOR *IfDesc;
3576 USB_ENDPOINT_DESCRIPTOR *EpDesc;
3577 UINTN NumEp;
3578 UINTN EpIndex;
3579 UINT8 EpAddr;
3580 UINT8 Direction;
3581 UINT8 Dci;
3582 UINT8 MaxDci;
3583 EFI_PHYSICAL_ADDRESS PhyAddr;
3584 VOID *RingSeg;
3585
3586 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3587 INPUT_CONTEXT_64 *InputContext;
3588 DEVICE_CONTEXT_64 *OutputContext;
3589 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3590
3591 Status = EFI_SUCCESS;
3592
3593 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3594 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3595 //
3596 // XHCI 4.6.6 Configure Endpoint
3597 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3598 // Context and Add Context flags as follows:
3599 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3600 // Context and Add Context flags to '0'.
3601 //
3602 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3603 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3604 //
3605 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
3606 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
3607
3608 ASSERT (ConfigDesc != NULL);
3609
3610 MaxDci = 0;
3611
3612 IfDescActive = NULL;
3613 IfDescSet = NULL;
3614
3615 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
3616 while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
3617 if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
3618 if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
3619 if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
3620 //
3621 // Find out the active interface descriptor.
3622 //
3623 IfDescActive = IfDesc;
3624 } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
3625 //
3626 // Find out the interface descriptor to set.
3627 //
3628 IfDescSet = IfDesc;
3629 }
3630 }
3631 }
3632 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3633 }
3634
3635 //
3636 // XHCI 4.6.6 Configure Endpoint
3637 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3638 // Context and Add Context flags as follows:
3639 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3640 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3641 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3642 // the Drop Context flag to '1' and Add Context flag to '0'.
3643 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3644 // and Add Context flags shall be set to '1'.
3645 //
3646 // Below codes are to cover 2), 3) and 4).
3647 //
3648
3649 if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
3650 NumEp = IfDescActive->NumEndpoints;
3651 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
3652 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
3653 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
3654 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3655 }
3656
3657 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
3658 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3659 continue;
3660 }
3661
3662 EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
3663 Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
3664
3665 Dci = XhcEndpointToDci (EpAddr, Direction);
3666 ASSERT (Dci < 32);
3667 if (Dci > MaxDci) {
3668 MaxDci = Dci;
3669 }
3670 //
3671 // XHCI 4.3.6 - Setting Alternate Interfaces
3672 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3673 //
3674 Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);
3675 if (EFI_ERROR (Status)) {
3676 return Status;
3677 }
3678 //
3679 // XHCI 4.3.6 - Setting Alternate Interfaces
3680 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3681 //
3682 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {
3683 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;
3684 if (RingSeg != NULL) {
3685 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
3686 }
3687 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
3688 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
3689 }
3690
3691 //
3692 // Set the Drop Context flag to '1'.
3693 //
3694 InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);
3695
3696 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3697 }
3698
3699 //
3700 // XHCI 4.3.6 - Setting Alternate Interfaces
3701 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3702 // Interface setting, to '0'.
3703 //
3704 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3705 //
3706
3707 //
3708 // XHCI 4.3.6 - Setting Alternate Interfaces
3709 // 4) For each endpoint enabled by the Configure Endpoint Command:
3710 // a. Allocate a Transfer Ring.
3711 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3712 // c. Initialize the Endpoint Context data structure.
3713 //
3714 Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);
3715 if (Dci > MaxDci) {
3716 MaxDci = Dci;
3717 }
3718
3719 InputContext->InputControlContext.Dword2 |= BIT0;
3720 InputContext->Slot.ContextEntries = MaxDci;
3721 //
3722 // XHCI 4.3.6 - Setting Alternate Interfaces
3723 // 5) Issue and successfully complete a Configure Endpoint Command.
3724 //
3725 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3726 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
3727 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3728 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3729 CmdTrbCfgEP.CycleBit = 1;
3730 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3731 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3732 DEBUG ((EFI_D_INFO, "SetInterface64: Configure Endpoint\n"));
3733 Status = XhcCmdTransfer (
3734 Xhc,
3735 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3736 XHC_GENERIC_TIMEOUT,
3737 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3738 );
3739 if (EFI_ERROR (Status)) {
3740 DEBUG ((EFI_D_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
3741 } else {
3742 //
3743 // Update the active AlternateSetting.
3744 //
3745 Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
3746 }
3747 }
3748
3749 return Status;
3750 }
3751
3752 /**
3753 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3754
3755 @param Xhc The XHCI Instance.
3756 @param SlotId The slot id to be evaluated.
3757 @param MaxPacketSize The max packet size supported by the device control transfer.
3758
3759 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3760
3761 **/
3762 EFI_STATUS
3763 EFIAPI
3764 XhcEvaluateContext (
3765 IN USB_XHCI_INSTANCE *Xhc,
3766 IN UINT8 SlotId,
3767 IN UINT32 MaxPacketSize
3768 )
3769 {
3770 EFI_STATUS Status;
3771 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
3772 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3773 INPUT_CONTEXT *InputContext;
3774 EFI_PHYSICAL_ADDRESS PhyAddr;
3775
3776 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
3777
3778 //
3779 // 4.6.7 Evaluate Context
3780 //
3781 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3782 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
3783
3784 InputContext->InputControlContext.Dword2 |= BIT1;
3785 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
3786
3787 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
3788 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
3789 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
3790 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3791 CmdTrbEvalu.CycleBit = 1;
3792 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
3793 CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3794 DEBUG ((EFI_D_INFO, "Evaluate context\n"));
3795 Status = XhcCmdTransfer (
3796 Xhc,
3797 (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
3798 XHC_GENERIC_TIMEOUT,
3799 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3800 );
3801 if (EFI_ERROR (Status)) {
3802 DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
3803 }
3804 return Status;
3805 }
3806
3807 /**
3808 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3809
3810 @param Xhc The XHCI Instance.
3811 @param SlotId The slot id to be evaluated.
3812 @param MaxPacketSize The max packet size supported by the device control transfer.
3813
3814 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3815
3816 **/
3817 EFI_STATUS
3818 EFIAPI
3819 XhcEvaluateContext64 (
3820 IN USB_XHCI_INSTANCE *Xhc,
3821 IN UINT8 SlotId,
3822 IN UINT32 MaxPacketSize
3823 )
3824 {
3825 EFI_STATUS Status;
3826 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
3827 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3828 INPUT_CONTEXT_64 *InputContext;
3829 EFI_PHYSICAL_ADDRESS PhyAddr;
3830
3831 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
3832
3833 //
3834 // 4.6.7 Evaluate Context
3835 //
3836 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3837 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
3838
3839 InputContext->InputControlContext.Dword2 |= BIT1;
3840 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
3841
3842 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
3843 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
3844 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
3845 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3846 CmdTrbEvalu.CycleBit = 1;
3847 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
3848 CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3849 DEBUG ((EFI_D_INFO, "Evaluate context\n"));
3850 Status = XhcCmdTransfer (
3851 Xhc,
3852 (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
3853 XHC_GENERIC_TIMEOUT,
3854 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3855 );
3856 if (EFI_ERROR (Status)) {
3857 DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
3858 }
3859 return Status;
3860 }
3861
3862
3863 /**
3864 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3865
3866 @param Xhc The XHCI Instance.
3867 @param SlotId The slot id to be configured.
3868 @param PortNum The total number of downstream port supported by the hub.
3869 @param TTT The TT think time of the hub device.
3870 @param MTT The multi-TT of the hub device.
3871
3872 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3873
3874 **/
3875 EFI_STATUS
3876 XhcConfigHubContext (
3877 IN USB_XHCI_INSTANCE *Xhc,
3878 IN UINT8 SlotId,
3879 IN UINT8 PortNum,
3880 IN UINT8 TTT,
3881 IN UINT8 MTT
3882 )
3883 {
3884 EFI_STATUS Status;
3885 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3886 INPUT_CONTEXT *InputContext;
3887 DEVICE_CONTEXT *OutputContext;
3888 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3889 EFI_PHYSICAL_ADDRESS PhyAddr;
3890
3891 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
3892 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3893 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3894
3895 //
3896 // 4.6.7 Evaluate Context
3897 //
3898 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
3899
3900 InputContext->InputControlContext.Dword2 |= BIT0;
3901
3902 //
3903 // Copy the slot context from OutputContext to Input context
3904 //
3905 CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
3906 InputContext->Slot.Hub = 1;
3907 InputContext->Slot.PortNum = PortNum;
3908 InputContext->Slot.TTT = TTT;
3909 InputContext->Slot.MTT = MTT;
3910
3911 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3912 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
3913 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3914 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3915 CmdTrbCfgEP.CycleBit = 1;
3916 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3917 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3918 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
3919 Status = XhcCmdTransfer (
3920 Xhc,
3921 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3922 XHC_GENERIC_TIMEOUT,
3923 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3924 );
3925 if (EFI_ERROR (Status)) {
3926 DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
3927 }
3928 return Status;
3929 }
3930
3931 /**
3932 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3933
3934 @param Xhc The XHCI Instance.
3935 @param SlotId The slot id to be configured.
3936 @param PortNum The total number of downstream port supported by the hub.
3937 @param TTT The TT think time of the hub device.
3938 @param MTT The multi-TT of the hub device.
3939
3940 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3941
3942 **/
3943 EFI_STATUS
3944 XhcConfigHubContext64 (
3945 IN USB_XHCI_INSTANCE *Xhc,
3946 IN UINT8 SlotId,
3947 IN UINT8 PortNum,
3948 IN UINT8 TTT,
3949 IN UINT8 MTT
3950 )
3951 {
3952 EFI_STATUS Status;
3953 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3954 INPUT_CONTEXT_64 *InputContext;
3955 DEVICE_CONTEXT_64 *OutputContext;
3956 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3957 EFI_PHYSICAL_ADDRESS PhyAddr;
3958
3959 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
3960 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3961 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3962
3963 //
3964 // 4.6.7 Evaluate Context
3965 //
3966 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
3967
3968 InputContext->InputControlContext.Dword2 |= BIT0;
3969
3970 //
3971 // Copy the slot context from OutputContext to Input context
3972 //
3973 CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
3974 InputContext->Slot.Hub = 1;
3975 InputContext->Slot.PortNum = PortNum;
3976 InputContext->Slot.TTT = TTT;
3977 InputContext->Slot.MTT = MTT;
3978
3979 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3980 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
3981 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3982 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3983 CmdTrbCfgEP.CycleBit = 1;
3984 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3985 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3986 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
3987 Status = XhcCmdTransfer (
3988 Xhc,
3989 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3990 XHC_GENERIC_TIMEOUT,
3991 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3992 );
3993 if (EFI_ERROR (Status)) {
3994 DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
3995 }
3996 return Status;
3997 }
3998
3999
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