]> git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
projects / mirror_edk2.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
MdeModulePkg/XhciDxe: Event Ring traverse algorithm enhancement to avoid that those...
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.h
1 /** @file
2
3 This file contains the definition for XHCI host controller schedule routines.
4
5 Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _EFI_XHCI_SCHED_H_
17 #define _EFI_XHCI_SCHED_H_
18
19 #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
20
21 //
22 // Transfer types, used in URB to identify the transfer type
23 //
24 #define XHC_CTRL_TRANSFER 0x01
25 #define XHC_BULK_TRANSFER 0x02
26 #define XHC_INT_TRANSFER_SYNC 0x04
27 #define XHC_INT_TRANSFER_ASYNC 0x08
28 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
29
30 //
31 // 6.4.6 TRB Types
32 //
33 #define TRB_TYPE_NORMAL 1
34 #define TRB_TYPE_SETUP_STAGE 2
35 #define TRB_TYPE_DATA_STAGE 3
36 #define TRB_TYPE_STATUS_STAGE 4
37 #define TRB_TYPE_ISOCH 5
38 #define TRB_TYPE_LINK 6
39 #define TRB_TYPE_EVENT_DATA 7
40 #define TRB_TYPE_NO_OP 8
41 #define TRB_TYPE_EN_SLOT 9
42 #define TRB_TYPE_DIS_SLOT 10
43 #define TRB_TYPE_ADDRESS_DEV 11
44 #define TRB_TYPE_CON_ENDPOINT 12
45 #define TRB_TYPE_EVALU_CONTXT 13
46 #define TRB_TYPE_RESET_ENDPOINT 14
47 #define TRB_TYPE_STOP_ENDPOINT 15
48 #define TRB_TYPE_SET_TR_DEQUE 16
49 #define TRB_TYPE_RESET_DEV 17
50 #define TRB_TYPE_GET_PORT_BANW 21
51 #define TRB_TYPE_FORCE_HEADER 22
52 #define TRB_TYPE_NO_OP_COMMAND 23
53 #define TRB_TYPE_TRANS_EVENT 32
54 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
55 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
56 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
57 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
58 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
59
60 //
61 // Endpoint Type (EP Type).
62 //
63 #define ED_NOT_VALID 0
64 #define ED_ISOCH_OUT 1
65 #define ED_BULK_OUT 2
66 #define ED_INTERRUPT_OUT 3
67 #define ED_CONTROL_BIDIR 4
68 #define ED_ISOCH_IN 5
69 #define ED_BULK_IN 6
70 #define ED_INTERRUPT_IN 7
71
72 //
73 // 6.4.5 TRB Completion Codes
74 //
75 #define TRB_COMPLETION_INVALID 0
76 #define TRB_COMPLETION_SUCCESS 1
77 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
78 #define TRB_COMPLETION_BABBLE_ERROR 3
79 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
80 #define TRB_COMPLETION_TRB_ERROR 5
81 #define TRB_COMPLETION_STALL_ERROR 6
82 #define TRB_COMPLETION_SHORT_PACKET 13
83
84 //
85 // The topology string used to present usb device location
86 //
87 typedef struct _USB_DEV_TOPOLOGY {
88 //
89 // The tier concatenation of down stream port.
90 //
91 UINT32 RouteString:20;
92 //
93 // The root port number of the chain.
94 //
95 UINT32 RootPortNum:8;
96 //
97 // The Tier the device reside.
98 //
99 UINT32 TierNum:4;
100 } USB_DEV_TOPOLOGY;
101
102 //
103 // USB Device's RouteChart
104 //
105 typedef union _USB_DEV_ROUTE {
106 UINT32 Dword;
107 USB_DEV_TOPOLOGY Route;
108 } USB_DEV_ROUTE;
109
110 //
111 // Endpoint address and its capabilities
112 //
113 typedef struct _USB_ENDPOINT {
114 //
115 // Store logical device address assigned by UsbBus
116 // It's because some XHCI host controllers may assign the same physcial device
117 // address for those devices inserted at different root port.
118 //
119 UINT8 BusAddr;
120 UINT8 DevAddr;
121 UINT8 EpAddr;
122 EFI_USB_DATA_DIRECTION Direction;
123 UINT8 DevSpeed;
124 UINTN MaxPacket;
125 UINTN Type;
126 } USB_ENDPOINT;
127
128 //
129 // TRB Template
130 //
131 typedef struct _TRB_TEMPLATE {
132 UINT32 Parameter1;
133
134 UINT32 Parameter2;
135
136 UINT32 Status;
137
138 UINT32 CycleBit:1;
139 UINT32 RsvdZ1:9;
140 UINT32 Type:6;
141 UINT32 Control:16;
142 } TRB_TEMPLATE;
143
144 typedef struct _TRANSFER_RING {
145 VOID *RingSeg0;
146 UINTN TrbNumber;
147 TRB_TEMPLATE *RingEnqueue;
148 TRB_TEMPLATE *RingDequeue;
149 UINT32 RingPCS;
150 } TRANSFER_RING;
151
152 typedef struct _EVENT_RING {
153 VOID *ERSTBase;
154 VOID *EventRingSeg0;
155 UINTN TrbNumber;
156 TRB_TEMPLATE *EventRingEnqueue;
157 TRB_TEMPLATE *EventRingDequeue;
158 UINT32 EventRingCCS;
159 } EVENT_RING;
160
161 //
162 // URB (Usb Request Block) contains information for all kinds of
163 // usb requests.
164 //
165 typedef struct _URB {
166 UINT32 Signature;
167 LIST_ENTRY UrbList;
168 //
169 // Usb Device URB related information
170 //
171 USB_ENDPOINT Ep;
172 EFI_USB_DEVICE_REQUEST *Request;
173 VOID *Data;
174 UINTN DataLen;
175 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
176 VOID *Context;
177 //
178 // Execute result
179 //
180 UINT32 Result;
181 //
182 // completed data length
183 //
184 UINTN Completed;
185 //
186 // Command/Tranfer Ring info
187 //
188 TRANSFER_RING *Ring;
189 TRB_TEMPLATE *TrbStart;
190 TRB_TEMPLATE *TrbEnd;
191 UINTN TrbNum;
192 BOOLEAN StartDone;
193 BOOLEAN EndDone;
194 BOOLEAN Finished;
195
196 TRB_TEMPLATE *EvtTrb;
197 } URB;
198
199 //
200 // 6.5 Event Ring Segment Table
201 // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
202 // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
203 // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
204 // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
205 //
206 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
207 UINT32 PtrLo;
208 UINT32 PtrHi;
209 UINT32 RingTrbSize:16;
210 UINT32 RsvdZ1:16;
211 UINT32 RsvdZ2;
212 } EVENT_RING_SEG_TABLE_ENTRY;
213
214 //
215 // 6.4.1.1 Normal TRB
216 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
217 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
218 // Rings, and to define the Data stage information for Control Transfer Rings.
219 //
220 typedef struct _TRANSFER_TRB_NORMAL {
221 UINT32 TRBPtrLo;
222
223 UINT32 TRBPtrHi;
224
225 UINT32 Lenth:17;
226 UINT32 TDSize:5;
227 UINT32 IntTarget:10;
228
229 UINT32 CycleBit:1;
230 UINT32 ENT:1;
231 UINT32 ISP:1;
232 UINT32 NS:1;
233 UINT32 CH:1;
234 UINT32 IOC:1;
235 UINT32 IDT:1;
236 UINT32 RsvdZ1:2;
237 UINT32 BEI:1;
238 UINT32 Type:6;
239 UINT32 RsvdZ2:16;
240 } TRANSFER_TRB_NORMAL;
241
242 //
243 // 6.4.1.2.1 Setup Stage TRB
244 // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
245 //
246 typedef struct _TRANSFER_TRB_CONTROL_SETUP {
247 UINT32 bmRequestType:8;
248 UINT32 bRequest:8;
249 UINT32 wValue:16;
250
251 UINT32 wIndex:16;
252 UINT32 wLength:16;
253
254 UINT32 Lenth:17;
255 UINT32 RsvdZ1:5;
256 UINT32 IntTarget:10;
257
258 UINT32 CycleBit:1;
259 UINT32 RsvdZ2:4;
260 UINT32 IOC:1;
261 UINT32 IDT:1;
262 UINT32 RsvdZ3:3;
263 UINT32 Type:6;
264 UINT32 TRT:2;
265 UINT32 RsvdZ4:14;
266 } TRANSFER_TRB_CONTROL_SETUP;
267
268 //
269 // 6.4.1.2.2 Data Stage TRB
270 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
271 //
272 typedef struct _TRANSFER_TRB_CONTROL_DATA {
273 UINT32 TRBPtrLo;
274
275 UINT32 TRBPtrHi;
276
277 UINT32 Lenth:17;
278 UINT32 TDSize:5;
279 UINT32 IntTarget:10;
280
281 UINT32 CycleBit:1;
282 UINT32 ENT:1;
283 UINT32 ISP:1;
284 UINT32 NS:1;
285 UINT32 CH:1;
286 UINT32 IOC:1;
287 UINT32 IDT:1;
288 UINT32 RsvdZ1:3;
289 UINT32 Type:6;
290 UINT32 DIR:1;
291 UINT32 RsvdZ2:15;
292 } TRANSFER_TRB_CONTROL_DATA;
293
294 //
295 // 6.4.1.2.2 Data Stage TRB
296 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
297 //
298 typedef struct _TRANSFER_TRB_CONTROL_STATUS {
299 UINT32 RsvdZ1;
300 UINT32 RsvdZ2;
301
302 UINT32 RsvdZ3:22;
303 UINT32 IntTarget:10;
304
305 UINT32 CycleBit:1;
306 UINT32 ENT:1;
307 UINT32 RsvdZ4:2;
308 UINT32 CH:1;
309 UINT32 IOC:1;
310 UINT32 RsvdZ5:4;
311 UINT32 Type:6;
312 UINT32 DIR:1;
313 UINT32 RsvdZ6:15;
314 } TRANSFER_TRB_CONTROL_STATUS;
315
316 //
317 // 6.4.2.1 Transfer Event TRB
318 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
319 // for more information on the use and operation of Transfer Events.
320 //
321 typedef struct _EVT_TRB_TRANSFER {
322 UINT32 TRBPtrLo;
323
324 UINT32 TRBPtrHi;
325
326 UINT32 Lenth:24;
327 UINT32 Completecode:8;
328
329 UINT32 CycleBit:1;
330 UINT32 RsvdZ1:1;
331 UINT32 ED:1;
332 UINT32 RsvdZ2:7;
333 UINT32 Type:6;
334 UINT32 EndpointId:5;
335 UINT32 RsvdZ3:3;
336 UINT32 SlotId:8;
337 } EVT_TRB_TRANSFER;
338
339 //
340 // 6.4.2.2 Command Completion Event TRB
341 // A Command Completion Event TRB shall be generated by the xHC when a command completes on the
342 // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
343 //
344 typedef struct _EVT_TRB_COMMAND_COMPLETION {
345 UINT32 TRBPtrLo;
346
347 UINT32 TRBPtrHi;
348
349 UINT32 RsvdZ2:24;
350 UINT32 Completecode:8;
351
352 UINT32 CycleBit:1;
353 UINT32 RsvdZ3:9;
354 UINT32 Type:6;
355 UINT32 VFID:8;
356 UINT32 SlotId:8;
357 } EVT_TRB_COMMAND_COMPLETION;
358
359 typedef union _TRB {
360 TRB_TEMPLATE TrbTemplate;
361 TRANSFER_TRB_NORMAL TrbNormal;
362 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
363 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
364 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
365 } TRB;
366
367 //
368 // 6.4.3.1 No Op Command TRB
369 // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
370 // mechanisms offered by the xHCI.
371 //
372 typedef struct _CMD_TRB_NO_OP {
373 UINT32 RsvdZ0;
374 UINT32 RsvdZ1;
375 UINT32 RsvdZ2;
376
377 UINT32 CycleBit:1;
378 UINT32 RsvdZ3:9;
379 UINT32 Type:6;
380 UINT32 RsvdZ4:16;
381 } CMD_TRB_NO_OP;
382
383 //
384 // 6.4.3.2 Enable Slot Command TRB
385 // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
386 // selected slot to the host in a Command Completion Event.
387 //
388 typedef struct _CMD_TRB_ENABLE_SLOT {
389 UINT32 RsvdZ0;
390 UINT32 RsvdZ1;
391 UINT32 RsvdZ2;
392
393 UINT32 CycleBit:1;
394 UINT32 RsvdZ3:9;
395 UINT32 Type:6;
396 UINT32 RsvdZ4:16;
397 } CMD_TRB_ENABLE_SLOT;
398
399 //
400 // 6.4.3.3 Disable Slot Command TRB
401 // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
402 // internal xHC resources assigned to the slot.
403 //
404 typedef struct _CMD_TRB_DISABLE_SLOT {
405 UINT32 RsvdZ0;
406 UINT32 RsvdZ1;
407 UINT32 RsvdZ2;
408
409 UINT32 CycleBit:1;
410 UINT32 RsvdZ3:9;
411 UINT32 Type:6;
412 UINT32 RsvdZ4:8;
413 UINT32 SlotId:8;
414 } CMD_TRB_DISABLE_SLOT;
415
416 //
417 // 6.4.3.4 Address Device Command TRB
418 // The Address Device Command TRB transitions the selected Device Context from the Default to the
419 // Addressed state and causes the xHC to select an address for the USB device in the Default State and
420 // issue a SET_ADDRESS request to the USB device.
421 //
422 typedef struct _CMD_TRB_ADDRESS_DEVICE {
423 UINT32 PtrLo;
424
425 UINT32 PtrHi;
426
427 UINT32 RsvdZ1;
428
429 UINT32 CycleBit:1;
430 UINT32 RsvdZ2:8;
431 UINT32 BSR:1;
432 UINT32 Type:6;
433 UINT32 RsvdZ3:8;
434 UINT32 SlotId:8;
435 } CMD_TRB_ADDRESS_DEVICE;
436
437 //
438 // 6.4.3.5 Configure Endpoint Command TRB
439 // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
440 // endpoints selected by the command.
441 //
442 typedef struct _CMD_TRB_CONFIG_ENDPOINT {
443 UINT32 PtrLo;
444
445 UINT32 PtrHi;
446
447 UINT32 RsvdZ1;
448
449 UINT32 CycleBit:1;
450 UINT32 RsvdZ2:8;
451 UINT32 DC:1;
452 UINT32 Type:6;
453 UINT32 RsvdZ3:8;
454 UINT32 SlotId:8;
455 } CMD_TRB_CONFIG_ENDPOINT;
456
457 //
458 // 6.4.3.6 Evaluate Context Command TRB
459 // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
460 // Context data structures in the Device Context have been modified by system software and that the xHC
461 // shall evaluate any changes
462 //
463 typedef struct _CMD_TRB_EVALUATE_CONTEXT {
464 UINT32 PtrLo;
465
466 UINT32 PtrHi;
467
468 UINT32 RsvdZ1;
469
470 UINT32 CycleBit:1;
471 UINT32 RsvdZ2:9;
472 UINT32 Type:6;
473 UINT32 RsvdZ3:8;
474 UINT32 SlotId:8;
475 } CMD_TRB_EVALUATE_CONTEXT;
476
477 //
478 // 6.4.3.7 Reset Endpoint Command TRB
479 // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
480 //
481 typedef struct _CMD_TRB_RESET_ENDPOINT {
482 UINT32 RsvdZ0;
483 UINT32 RsvdZ1;
484 UINT32 RsvdZ2;
485
486 UINT32 CycleBit:1;
487 UINT32 RsvdZ3:8;
488 UINT32 TSP:1;
489 UINT32 Type:6;
490 UINT32 EDID:5;
491 UINT32 RsvdZ4:3;
492 UINT32 SlotId:8;
493 } CMD_TRB_RESET_ENDPOINT;
494
495 //
496 // 6.4.3.8 Stop Endpoint Command TRB
497 // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
498 // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
499 //
500 typedef struct _CMD_TRB_STOP_ENDPOINT {
501 UINT32 RsvdZ0;
502 UINT32 RsvdZ1;
503 UINT32 RsvdZ2;
504
505 UINT32 CycleBit:1;
506 UINT32 RsvdZ3:9;
507 UINT32 Type:6;
508 UINT32 EDID:5;
509 UINT32 RsvdZ4:2;
510 UINT32 SP:1;
511 UINT32 SlotId:8;
512 } CMD_TRB_STOP_ENDPOINT;
513
514 //
515 // 6.4.3.9 Set TR Dequeue Pointer Command TRB
516 // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
517 // Pointer and DCS fields of an Endpoint or Stream Context.
518 //
519 typedef struct _CMD_SET_TR_DEQ_POINTER {
520 UINT32 PtrLo;
521
522 UINT32 PtrHi;
523
524 UINT32 RsvdZ1:16;
525 UINT32 StreamID:16;
526
527 UINT32 CycleBit:1;
528 UINT32 RsvdZ2:9;
529 UINT32 Type:6;
530 UINT32 Endpoint:5;
531 UINT32 RsvdZ3:3;
532 UINT32 SlotId:8;
533 } CMD_SET_TR_DEQ_POINTER;
534
535 //
536 // 6.4.4.1 Link TRB
537 // A Link TRB provides support for non-contiguous TRB Rings.
538 //
539 typedef struct _LINK_TRB {
540 UINT32 PtrLo;
541
542 UINT32 PtrHi;
543
544 UINT32 RsvdZ1:22;
545 UINT32 InterTarget:10;
546
547 UINT32 CycleBit:1;
548 UINT32 TC:1;
549 UINT32 RsvdZ2:2;
550 UINT32 CH:1;
551 UINT32 IOC:1;
552 UINT32 RsvdZ3:4;
553 UINT32 Type:6;
554 UINT32 RsvdZ4:16;
555 } LINK_TRB;
556
557 //
558 // 6.2.2 Slot Context
559 //
560 typedef struct _SLOT_CONTEXT {
561 UINT32 RouteString:20;
562 UINT32 Speed:4;
563 UINT32 RsvdZ1:1;
564 UINT32 MTT:1;
565 UINT32 Hub:1;
566 UINT32 ContextEntries:5;
567
568 UINT32 MaxExitLatency:16;
569 UINT32 RootHubPortNum:8;
570 UINT32 PortNum:8;
571
572 UINT32 TTHubSlotId:8;
573 UINT32 TTPortNum:8;
574 UINT32 TTT:2;
575 UINT32 RsvdZ2:4;
576 UINT32 InterTarget:10;
577
578 UINT32 DeviceAddress:8;
579 UINT32 RsvdZ3:19;
580 UINT32 SlotState:5;
581
582 UINT32 RsvdZ4;
583 UINT32 RsvdZ5;
584 UINT32 RsvdZ6;
585 UINT32 RsvdZ7;
586 } SLOT_CONTEXT;
587
588 typedef struct _SLOT_CONTEXT_64 {
589 UINT32 RouteString:20;
590 UINT32 Speed:4;
591 UINT32 RsvdZ1:1;
592 UINT32 MTT:1;
593 UINT32 Hub:1;
594 UINT32 ContextEntries:5;
595
596 UINT32 MaxExitLatency:16;
597 UINT32 RootHubPortNum:8;
598 UINT32 PortNum:8;
599
600 UINT32 TTHubSlotId:8;
601 UINT32 TTPortNum:8;
602 UINT32 TTT:2;
603 UINT32 RsvdZ2:4;
604 UINT32 InterTarget:10;
605
606 UINT32 DeviceAddress:8;
607 UINT32 RsvdZ3:19;
608 UINT32 SlotState:5;
609
610 UINT32 RsvdZ4;
611 UINT32 RsvdZ5;
612 UINT32 RsvdZ6;
613 UINT32 RsvdZ7;
614
615 UINT32 RsvdZ8;
616 UINT32 RsvdZ9;
617 UINT32 RsvdZ10;
618 UINT32 RsvdZ11;
619
620 UINT32 RsvdZ12;
621 UINT32 RsvdZ13;
622 UINT32 RsvdZ14;
623 UINT32 RsvdZ15;
624
625 } SLOT_CONTEXT_64;
626
627
628 //
629 // 6.2.3 Endpoint Context
630 //
631 typedef struct _ENDPOINT_CONTEXT {
632 UINT32 EPState:3;
633 UINT32 RsvdZ1:5;
634 UINT32 Mult:2;
635 UINT32 MaxPStreams:5;
636 UINT32 LSA:1;
637 UINT32 Interval:8;
638 UINT32 RsvdZ2:8;
639
640 UINT32 RsvdZ3:1;
641 UINT32 CErr:2;
642 UINT32 EPType:3;
643 UINT32 RsvdZ4:1;
644 UINT32 HID:1;
645 UINT32 MaxBurstSize:8;
646 UINT32 MaxPacketSize:16;
647
648 UINT32 PtrLo;
649
650 UINT32 PtrHi;
651
652 UINT32 AverageTRBLength:16;
653 UINT32 MaxESITPayload:16;
654
655 UINT32 RsvdZ5;
656 UINT32 RsvdZ6;
657 UINT32 RsvdZ7;
658 } ENDPOINT_CONTEXT;
659
660 typedef struct _ENDPOINT_CONTEXT_64 {
661 UINT32 EPState:3;
662 UINT32 RsvdZ1:5;
663 UINT32 Mult:2;
664 UINT32 MaxPStreams:5;
665 UINT32 LSA:1;
666 UINT32 Interval:8;
667 UINT32 RsvdZ2:8;
668
669 UINT32 RsvdZ3:1;
670 UINT32 CErr:2;
671 UINT32 EPType:3;
672 UINT32 RsvdZ4:1;
673 UINT32 HID:1;
674 UINT32 MaxBurstSize:8;
675 UINT32 MaxPacketSize:16;
676
677 UINT32 PtrLo;
678
679 UINT32 PtrHi;
680
681 UINT32 AverageTRBLength:16;
682 UINT32 MaxESITPayload:16;
683
684 UINT32 RsvdZ5;
685 UINT32 RsvdZ6;
686 UINT32 RsvdZ7;
687
688 UINT32 RsvdZ8;
689 UINT32 RsvdZ9;
690 UINT32 RsvdZ10;
691 UINT32 RsvdZ11;
692
693 UINT32 RsvdZ12;
694 UINT32 RsvdZ13;
695 UINT32 RsvdZ14;
696 UINT32 RsvdZ15;
697
698 } ENDPOINT_CONTEXT_64;
699
700
701 //
702 // 6.2.5.1 Input Control Context
703 //
704 typedef struct _INPUT_CONTRL_CONTEXT {
705 UINT32 Dword1;
706 UINT32 Dword2;
707 UINT32 RsvdZ1;
708 UINT32 RsvdZ2;
709 UINT32 RsvdZ3;
710 UINT32 RsvdZ4;
711 UINT32 RsvdZ5;
712 UINT32 RsvdZ6;
713 } INPUT_CONTRL_CONTEXT;
714
715 typedef struct _INPUT_CONTRL_CONTEXT_64 {
716 UINT32 Dword1;
717 UINT32 Dword2;
718 UINT32 RsvdZ1;
719 UINT32 RsvdZ2;
720 UINT32 RsvdZ3;
721 UINT32 RsvdZ4;
722 UINT32 RsvdZ5;
723 UINT32 RsvdZ6;
724 UINT32 RsvdZ7;
725 UINT32 RsvdZ8;
726 UINT32 RsvdZ9;
727 UINT32 RsvdZ10;
728 UINT32 RsvdZ11;
729 UINT32 RsvdZ12;
730 UINT32 RsvdZ13;
731 UINT32 RsvdZ14;
732 } INPUT_CONTRL_CONTEXT_64;
733
734 //
735 // 6.2.1 Device Context
736 //
737 typedef struct _DEVICE_CONTEXT {
738 SLOT_CONTEXT Slot;
739 ENDPOINT_CONTEXT EP[31];
740 } DEVICE_CONTEXT;
741
742 typedef struct _DEVICE_CONTEXT_64 {
743 SLOT_CONTEXT_64 Slot;
744 ENDPOINT_CONTEXT_64 EP[31];
745 } DEVICE_CONTEXT_64;
746
747 //
748 // 6.2.5 Input Context
749 //
750 typedef struct _INPUT_CONTEXT {
751 INPUT_CONTRL_CONTEXT InputControlContext;
752 SLOT_CONTEXT Slot;
753 ENDPOINT_CONTEXT EP[31];
754 } INPUT_CONTEXT;
755
756 typedef struct _INPUT_CONTEXT_64 {
757 INPUT_CONTRL_CONTEXT_64 InputControlContext;
758 SLOT_CONTEXT_64 Slot;
759 ENDPOINT_CONTEXT_64 EP[31];
760 } INPUT_CONTEXT_64;
761
762
763 /**
764 Initialize the XHCI host controller for schedule.
765
766 @param Xhc The XHCI Instance to be initialized.
767
768 **/
769 VOID
770 XhcInitSched (
771 IN USB_XHCI_INSTANCE *Xhc
772 );
773
774 /**
775 Free the resouce allocated at initializing schedule.
776
777 @param Xhc The XHCI Instance.
778
779 **/
780 VOID
781 XhcFreeSched (
782 IN USB_XHCI_INSTANCE *Xhc
783 );
784
785 /**
786 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
787
788 @param Xhc The XHCI Instance.
789 @param Urb The URB to be rung.
790
791 @retval EFI_SUCCESS Successfully ring the door bell.
792
793 **/
794 EFI_STATUS
795 RingIntTransferDoorBell (
796 IN USB_XHCI_INSTANCE *Xhc,
797 IN URB *Urb
798 );
799
800 /**
801 Execute the transfer by polling the URB. This is a synchronous operation.
802
803 @param Xhc The XHCI Instance.
804 @param CmdTransfer The executed URB is for cmd transfer or not.
805 @param Urb The URB to execute.
806 @param Timeout The time to wait before abort, in millisecond.
807
808 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
809 @return EFI_TIMEOUT The transfer failed due to time out.
810 @return EFI_SUCCESS The transfer finished OK.
811
812 **/
813 EFI_STATUS
814 XhcExecTransfer (
815 IN USB_XHCI_INSTANCE *Xhc,
816 IN BOOLEAN CmdTransfer,
817 IN URB *Urb,
818 IN UINTN Timeout
819 );
820
821 /**
822 Delete a single asynchronous interrupt transfer for
823 the device and endpoint.
824
825 @param Xhc The XHCI Instance.
826 @param BusAddr The logical device address assigned by UsbBus driver.
827 @param EpNum The endpoint of the target.
828
829 @retval EFI_SUCCESS An asynchronous transfer is removed.
830 @retval EFI_NOT_FOUND No transfer for the device is found.
831
832 **/
833 EFI_STATUS
834 XhciDelAsyncIntTransfer (
835 IN USB_XHCI_INSTANCE *Xhc,
836 IN UINT8 BusAddr,
837 IN UINT8 EpNum
838 );
839
840 /**
841 Remove all the asynchronous interrupt transfers.
842
843 @param Xhc The XHCI Instance.
844
845 **/
846 VOID
847 XhciDelAllAsyncIntTransfers (
848 IN USB_XHCI_INSTANCE *Xhc
849 );
850
851 /**
852 Set Bios Ownership
853
854 @param Xhc The XHCI Instance.
855
856 **/
857 VOID
858 XhcSetBiosOwnership (
859 IN USB_XHCI_INSTANCE *Xhc
860 );
861
862 /**
863 Clear Bios Ownership
864
865 @param Xhc The XHCI Instance.
866
867 **/
868 VOID
869 XhcClearBiosOwnership (
870 IN USB_XHCI_INSTANCE *Xhc
871 );
872
873 /**
874 Find out the slot id according to the device's route string.
875
876 @param Xhc The XHCI Instance.
877 @param RouteString The route string described the device location.
878
879 @return The slot id used by the device.
880
881 **/
882 UINT8
883 EFIAPI
884 XhcRouteStringToSlotId (
885 IN USB_XHCI_INSTANCE *Xhc,
886 IN USB_DEV_ROUTE RouteString
887 );
888
889 /**
890 Calculate the device context index by endpoint address and direction.
891
892 @param EpAddr The target endpoint number.
893 @param Direction The direction of the target endpoint.
894
895 @return The device context index of endpoint.
896
897 **/
898 UINT8
899 XhcEndpointToDci (
900 IN UINT8 EpAddr,
901 IN UINT8 Direction
902 );
903
904 /**
905 Ring the door bell to notify XHCI there is a transaction to be executed.
906
907 @param Xhc The XHCI Instance.
908 @param SlotId The slot id of the target device.
909 @param Dci The device context index of the target slot or endpoint.
910
911 @retval EFI_SUCCESS Successfully ring the door bell.
912
913 **/
914 EFI_STATUS
915 EFIAPI
916 XhcRingDoorBell (
917 IN USB_XHCI_INSTANCE *Xhc,
918 IN UINT8 SlotId,
919 IN UINT8 Dci
920 );
921
922 /**
923 Interrupt transfer periodic check handler.
924
925 @param Event Interrupt event.
926 @param Context Pointer to USB_XHCI_INSTANCE.
927
928 **/
929 VOID
930 EFIAPI
931 XhcMonitorAsyncRequests (
932 IN EFI_EVENT Event,
933 IN VOID *Context
934 );
935
936 /**
937 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
938
939 @param Xhc The XHCI Instance.
940 @param ParentRouteChart The route string pointed to the parent device if it exists.
941 @param Port The port to be polled.
942 @param PortState The port state.
943
944 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
945 @retval Others Should not appear.
946
947 **/
948 EFI_STATUS
949 EFIAPI
950 XhcPollPortStatusChange (
951 IN USB_XHCI_INSTANCE *Xhc,
952 IN USB_DEV_ROUTE ParentRouteChart,
953 IN UINT8 Port,
954 IN EFI_USB_PORT_STATUS *PortState
955 );
956
957 /**
958 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
959
960 @param Xhc The XHCI Instance.
961 @param SlotId The slot id to be configured.
962 @param PortNum The total number of downstream port supported by the hub.
963 @param TTT The TT think time of the hub device.
964 @param MTT The multi-TT of the hub device.
965
966 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
967
968 **/
969 EFI_STATUS
970 XhcConfigHubContext (
971 IN USB_XHCI_INSTANCE *Xhc,
972 IN UINT8 SlotId,
973 IN UINT8 PortNum,
974 IN UINT8 TTT,
975 IN UINT8 MTT
976 );
977
978
979 /**
980 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
981
982 @param Xhc The XHCI Instance.
983 @param SlotId The slot id to be configured.
984 @param PortNum The total number of downstream port supported by the hub.
985 @param TTT The TT think time of the hub device.
986 @param MTT The multi-TT of the hub device.
987
988 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
989
990 **/
991 EFI_STATUS
992 XhcConfigHubContext64 (
993 IN USB_XHCI_INSTANCE *Xhc,
994 IN UINT8 SlotId,
995 IN UINT8 PortNum,
996 IN UINT8 TTT,
997 IN UINT8 MTT
998 );
999
1000
1001 /**
1002 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1003
1004 @param Xhc The XHCI Instance.
1005 @param SlotId The slot id to be configured.
1006 @param DeviceSpeed The device's speed.
1007 @param ConfigDesc The pointer to the usb device configuration descriptor.
1008
1009 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1010
1011 **/
1012 EFI_STATUS
1013 EFIAPI
1014 XhcSetConfigCmd (
1015 IN USB_XHCI_INSTANCE *Xhc,
1016 IN UINT8 SlotId,
1017 IN UINT8 DeviceSpeed,
1018 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1019 );
1020
1021
1022 /**
1023 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1024
1025 @param Xhc The XHCI Instance.
1026 @param SlotId The slot id to be configured.
1027 @param DeviceSpeed The device's speed.
1028 @param ConfigDesc The pointer to the usb device configuration descriptor.
1029
1030 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1031
1032 **/
1033 EFI_STATUS
1034 EFIAPI
1035 XhcSetConfigCmd64 (
1036 IN USB_XHCI_INSTANCE *Xhc,
1037 IN UINT8 SlotId,
1038 IN UINT8 DeviceSpeed,
1039 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1040 );
1041
1042
1043 /**
1044 Find out the actual device address according to the requested device address from UsbBus.
1045
1046 @param Xhc The XHCI Instance.
1047 @param BusDevAddr The requested device address by UsbBus upper driver.
1048
1049 @return The actual device address assigned to the device.
1050
1051 **/
1052 UINT8
1053 EFIAPI
1054 XhcBusDevAddrToSlotId (
1055 IN USB_XHCI_INSTANCE *Xhc,
1056 IN UINT8 BusDevAddr
1057 );
1058
1059 /**
1060 Assign and initialize the device slot for a new device.
1061
1062 @param Xhc The XHCI Instance.
1063 @param ParentRouteChart The route string pointed to the parent device.
1064 @param ParentPort The port at which the device is located.
1065 @param RouteChart The route string pointed to the device.
1066 @param DeviceSpeed The device speed.
1067
1068 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1069
1070 **/
1071 EFI_STATUS
1072 EFIAPI
1073 XhcInitializeDeviceSlot (
1074 IN USB_XHCI_INSTANCE *Xhc,
1075 IN USB_DEV_ROUTE ParentRouteChart,
1076 IN UINT16 ParentPort,
1077 IN USB_DEV_ROUTE RouteChart,
1078 IN UINT8 DeviceSpeed
1079 );
1080
1081 /**
1082 Assign and initialize the device slot for a new device.
1083
1084 @param Xhc The XHCI Instance.
1085 @param ParentRouteChart The route string pointed to the parent device.
1086 @param ParentPort The port at which the device is located.
1087 @param RouteChart The route string pointed to the device.
1088 @param DeviceSpeed The device speed.
1089
1090 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1091
1092 **/
1093 EFI_STATUS
1094 EFIAPI
1095 XhcInitializeDeviceSlot64 (
1096 IN USB_XHCI_INSTANCE *Xhc,
1097 IN USB_DEV_ROUTE ParentRouteChart,
1098 IN UINT16 ParentPort,
1099 IN USB_DEV_ROUTE RouteChart,
1100 IN UINT8 DeviceSpeed
1101 );
1102
1103 /**
1104 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1105
1106 @param Xhc The XHCI Instance.
1107 @param SlotId The slot id to be evaluated.
1108 @param MaxPacketSize The max packet size supported by the device control transfer.
1109
1110 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1111
1112 **/
1113 EFI_STATUS
1114 EFIAPI
1115 XhcEvaluateContext (
1116 IN USB_XHCI_INSTANCE *Xhc,
1117 IN UINT8 SlotId,
1118 IN UINT32 MaxPacketSize
1119 );
1120
1121
1122 /**
1123 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1124
1125 @param Xhc The XHCI Instance.
1126 @param SlotId The slot id to be evaluated.
1127 @param MaxPacketSize The max packet size supported by the device control transfer.
1128
1129 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1130
1131 **/
1132 EFI_STATUS
1133 EFIAPI
1134 XhcEvaluateContext64 (
1135 IN USB_XHCI_INSTANCE *Xhc,
1136 IN UINT8 SlotId,
1137 IN UINT32 MaxPacketSize
1138 );
1139
1140
1141 /**
1142 Disable the specified device slot.
1143
1144 @param Xhc The XHCI Instance.
1145 @param SlotId The slot id to be disabled.
1146
1147 @retval EFI_SUCCESS Successfully disable the device slot.
1148
1149 **/
1150 EFI_STATUS
1151 EFIAPI
1152 XhcDisableSlotCmd (
1153 IN USB_XHCI_INSTANCE *Xhc,
1154 IN UINT8 SlotId
1155 );
1156
1157
1158 /**
1159 Disable the specified device slot.
1160
1161 @param Xhc The XHCI Instance.
1162 @param SlotId The slot id to be disabled.
1163
1164 @retval EFI_SUCCESS Successfully disable the device slot.
1165
1166 **/
1167 EFI_STATUS
1168 EFIAPI
1169 XhcDisableSlotCmd64 (
1170 IN USB_XHCI_INSTANCE *Xhc,
1171 IN UINT8 SlotId
1172 );
1173
1174
1175 /**
1176 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1177
1178 @param Xhc The XHCI Instance.
1179 @param TrsRing The transfer ring to sync.
1180
1181 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1182
1183 **/
1184 EFI_STATUS
1185 EFIAPI
1186 XhcSyncTrsRing (
1187 IN USB_XHCI_INSTANCE *Xhc,
1188 TRANSFER_RING *TrsRing
1189 );
1190
1191 /**
1192 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1193
1194 @param Xhc The XHCI Instance.
1195 @param EvtRing The event ring to sync.
1196
1197 @retval EFI_SUCCESS The event ring is synchronized successfully.
1198
1199 **/
1200 EFI_STATUS
1201 EFIAPI
1202 XhcSyncEventRing (
1203 IN USB_XHCI_INSTANCE *Xhc,
1204 EVENT_RING *EvtRing
1205 );
1206
1207 /**
1208 Check if there is a new generated event.
1209
1210 @param Xhc The XHCI Instance.
1211 @param EvtRing The event ring to check.
1212 @param NewEvtTrb The new event TRB found.
1213
1214 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1215 @retval EFI_NOT_READY The event ring has no new event.
1216
1217 **/
1218 EFI_STATUS
1219 EFIAPI
1220 XhcCheckNewEvent (
1221 IN USB_XHCI_INSTANCE *Xhc,
1222 IN EVENT_RING *EvtRing,
1223 OUT TRB_TEMPLATE **NewEvtTrb
1224 );
1225
1226 /**
1227 Create XHCI transfer ring.
1228
1229 @param Xhc The XHCI Instance.
1230 @param TrbNum The number of TRB in the ring.
1231 @param TransferRing The created transfer ring.
1232
1233 **/
1234 VOID
1235 CreateTransferRing (
1236 IN USB_XHCI_INSTANCE *Xhc,
1237 IN UINTN TrbNum,
1238 OUT TRANSFER_RING *TransferRing
1239 );
1240
1241 /**
1242 Create XHCI event ring.
1243
1244 @param Xhc The XHCI Instance.
1245 @param EventRing The created event ring.
1246
1247 **/
1248 VOID
1249 CreateEventRing (
1250 IN USB_XHCI_INSTANCE *Xhc,
1251 OUT EVENT_RING *EventRing
1252 );
1253
1254 /**
1255 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
1256 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
1257 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
1258 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
1259 Stopped to the Running state.
1260
1261 @param Xhc The XHCI Instance.
1262 @param Urb The urb which makes the endpoint halted.
1263
1264 @retval EFI_SUCCESS The recovery is successful.
1265 @retval Others Failed to recovery halted endpoint.
1266
1267 **/
1268 EFI_STATUS
1269 EFIAPI
1270 XhcRecoverHaltedEndpoint (
1271 IN USB_XHCI_INSTANCE *Xhc,
1272 IN URB *Urb
1273 );
1274
1275 /**
1276 Create a new URB for a new transaction.
1277
1278 @param Xhc The XHCI Instance
1279 @param DevAddr The device address
1280 @param EpAddr Endpoint addrress
1281 @param DevSpeed The device speed
1282 @param MaxPacket The max packet length of the endpoint
1283 @param Type The transaction type
1284 @param Request The standard USB request for control transfer
1285 @param Data The user data to transfer
1286 @param DataLen The length of data buffer
1287 @param Callback The function to call when data is transferred
1288 @param Context The context to the callback
1289
1290 @return Created URB or NULL
1291
1292 **/
1293 URB*
1294 XhcCreateUrb (
1295 IN USB_XHCI_INSTANCE *Xhc,
1296 IN UINT8 DevAddr,
1297 IN UINT8 EpAddr,
1298 IN UINT8 DevSpeed,
1299 IN UINTN MaxPacket,
1300 IN UINTN Type,
1301 IN EFI_USB_DEVICE_REQUEST *Request,
1302 IN VOID *Data,
1303 IN UINTN DataLen,
1304 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1305 IN VOID *Context
1306 );
1307
1308 /**
1309 Create a transfer TRB.
1310
1311 @param Xhc The XHCI Instance
1312 @param Urb The urb used to construct the transfer TRB.
1313
1314 @return Created TRB or NULL
1315
1316 **/
1317 EFI_STATUS
1318 XhcCreateTransferTrb (
1319 IN USB_XHCI_INSTANCE *Xhc,
1320 IN URB *Urb
1321 );
1322
1323 #endif
EFI Development Kit II mirror for PVE