2 16550 UART Serial Port library functions
4 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
5 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
6 Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR>
7 Copyright (c) 2020, ARM Limited. All rights reserved.
9 SPDX-License-Identifier: BSD-2-Clause-Patent
14 #include <IndustryStandard/Pci.h>
15 #include <Library/SerialPortLib.h>
16 #include <Library/PcdLib.h>
17 #include <Library/IoLib.h>
18 #include <Library/PciLib.h>
19 #include <Library/PlatformHookLib.h>
20 #include <Library/BaseLib.h>
25 #define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
28 // 16550 UART register offsets and bitfields
30 #define R_UART_RXBUF 0 // LCR_DLAB = 0
31 #define R_UART_TXBUF 0 // LCR_DLAB = 0
32 #define R_UART_BAUD_LOW 0 // LCR_DLAB = 1
33 #define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1
34 #define R_UART_IER 1 // LCR_DLAB = 0
36 #define B_UART_FCR_FIFOE BIT0
37 #define B_UART_FCR_FIFO64 BIT5
39 #define B_UART_LCR_DLAB BIT7
41 #define B_UART_MCR_DTRC BIT0
42 #define B_UART_MCR_RTS BIT1
44 #define B_UART_LSR_RXRDY BIT0
45 #define B_UART_LSR_TXRDY BIT5
46 #define B_UART_LSR_TEMT BIT6
48 #define B_UART_MSR_CTS BIT4
49 #define B_UART_MSR_DSR BIT5
50 #define B_UART_MSR_RI BIT6
51 #define B_UART_MSR_DCD BIT7
54 // 4-byte structure for each PCI node in PcdSerialPciDeviceInfo
59 UINT16 PowerManagementStatusAndControlRegister
;
60 } PCI_UART_DEVICE_INFO
;
63 Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
64 MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
65 parameter Offset is added to the base address of the 16550 registers that is specified
66 by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
67 width and defaults to 8 bit access, and supports 8 or 32 bit access.
69 @param Base The base address register of UART device.
70 @param Offset The offset of the 16550 register to read.
72 @return The value read from the 16550 register.
76 SerialPortReadRegister (
81 if (PcdGetBool (PcdSerialUseMmio
)) {
82 if (PcdGet8 (PcdSerialRegisterAccessWidth
) == 32) {
83 return (UINT8
) MmioRead32 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
));
85 return MmioRead8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
));
87 return IoRead8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
));
92 Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to
93 MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The
94 parameter Offset is added to the base address of the 16550 registers that is specified
95 by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
96 width and defaults to 8 bit access, and supports 8 or 32 bit access.
98 @param Base The base address register of UART device.
99 @param Offset The offset of the 16550 register to write.
100 @param Value The value to write to the 16550 register specified by Offset.
102 @return The value written to the 16550 register.
106 SerialPortWriteRegister (
112 if (PcdGetBool (PcdSerialUseMmio
)) {
113 if (PcdGet8 (PcdSerialRegisterAccessWidth
) == 32) {
114 return (UINT8
) MmioWrite32 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
), (UINT8
)Value
);
116 return MmioWrite8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
), Value
);
118 return IoWrite8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
), Value
);
123 Update the value of an 16-bit PCI configuration register in a PCI device. If the
124 PCI Configuration register specified by PciAddress is already programmed with a
125 non-zero value, then return the current value. Otherwise update the PCI configuration
126 register specified by PciAddress with the value specified by Value and return the
127 value programmed into the PCI configuration register. All values must be masked
128 using the bitmask specified by Mask.
130 @param PciAddress PCI Library address of the PCI Configuration register to update.
131 @param Value The value to program into the PCI Configuration Register.
132 @param Mask Bitmask of the bits to check and update in the PCI configuration register.
136 SerialPortLibUpdatePciRegister16 (
144 CurrentValue
= PciRead16 (PciAddress
) & Mask
;
145 if (CurrentValue
!= 0) {
148 return PciWrite16 (PciAddress
, Value
& Mask
);
152 Update the value of an 32-bit PCI configuration register in a PCI device. If the
153 PCI Configuration register specified by PciAddress is already programmed with a
154 non-zero value, then return the current value. Otherwise update the PCI configuration
155 register specified by PciAddress with the value specified by Value and return the
156 value programmed into the PCI configuration register. All values must be masked
157 using the bitmask specified by Mask.
159 @param PciAddress PCI Library address of the PCI Configuration register to update.
160 @param Value The value to program into the PCI Configuration Register.
161 @param Mask Bitmask of the bits to check and update in the PCI configuration register.
163 @return The Secondary bus number that is actually programed into the PCI to PCI Bridge device.
167 SerialPortLibUpdatePciRegister32 (
175 CurrentValue
= PciRead32 (PciAddress
) & Mask
;
176 if (CurrentValue
!= 0) {
179 return PciWrite32 (PciAddress
, Value
& Mask
);
183 Retrieve the I/O or MMIO base address register for the PCI UART device.
185 This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
186 Device if they are not already enabled.
188 @return The base address register of the UART device.
192 GetSerialRegisterBase (
198 UINTN SubordinateBusNumber
;
200 UINT32 ParentIoLimit
;
201 UINT16 ParentMemoryBase
;
202 UINT16 ParentMemoryLimit
;
207 UINTN SerialRegisterBase
;
209 UINT32 RegisterBaseMask
;
210 PCI_UART_DEVICE_INFO
*DeviceInfo
;
213 // Get PCI Device Info
215 DeviceInfo
= (PCI_UART_DEVICE_INFO
*) PcdGetPtr (PcdSerialPciDeviceInfo
);
218 // If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase
220 if (DeviceInfo
->Device
== 0xff) {
221 return (UINTN
)PcdGet64 (PcdSerialRegisterBase
);
225 // Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB
227 ParentMemoryBase
= 0 >> 16;
228 ParentMemoryLimit
= 0xfff00000 >> 16;
229 ParentIoBase
= 0 >> 12;
230 ParentIoLimit
= 0xf000 >> 12;
233 // Enable I/O and MMIO in PCI Bridge
234 // Assume Root Bus Numer is Zero.
236 for (BusNumber
= 0; (DeviceInfo
+ 1)->Device
!= 0xff; DeviceInfo
++) {
238 // Compute PCI Lib Address to PCI to PCI Bridge
240 PciLibAddress
= PCI_LIB_ADDRESS (BusNumber
, DeviceInfo
->Device
, DeviceInfo
->Function
, 0);
243 // Retrieve and verify the bus numbers in the PCI to PCI Bridge
245 BusNumber
= PciRead8 (PciLibAddress
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
);
246 SubordinateBusNumber
= PciRead8 (PciLibAddress
+ PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET
);
247 if (BusNumber
== 0 || BusNumber
> SubordinateBusNumber
) {
252 // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
254 if (PcdGetBool (PcdSerialUseMmio
)) {
255 MemoryLimit
= PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.MemoryLimit
)) & 0xfff0;
256 MemoryBase
= PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.MemoryBase
)) & 0xfff0;
259 // If PCI Bridge MMIO window is disabled, then return 0
261 if (MemoryLimit
< MemoryBase
) {
266 // If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0
268 if (MemoryBase
< ParentMemoryBase
|| MemoryBase
> ParentMemoryLimit
|| MemoryLimit
> ParentMemoryLimit
) {
271 ParentMemoryBase
= MemoryBase
;
272 ParentMemoryLimit
= MemoryLimit
;
274 IoLimit
= PciRead8 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoLimit
));
275 if ((IoLimit
& PCI_BRIDGE_32_BIT_IO_SPACE
) == 0) {
276 IoLimit
= IoLimit
>> 4;
278 IoLimit
= (PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoLimitUpper16
)) << 4) | (IoLimit
>> 4);
280 IoBase
= PciRead8 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoBase
));
281 if ((IoBase
& PCI_BRIDGE_32_BIT_IO_SPACE
) == 0) {
282 IoBase
= IoBase
>> 4;
284 IoBase
= (PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoBaseUpper16
)) << 4) | (IoBase
>> 4);
288 // If PCI Bridge I/O window is disabled, then return 0
290 if (IoLimit
< IoBase
) {
295 // If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0
297 if (IoBase
< ParentIoBase
|| IoBase
> ParentIoLimit
|| IoLimit
> ParentIoLimit
) {
300 ParentIoBase
= IoBase
;
301 ParentIoLimit
= IoLimit
;
306 // Compute PCI Lib Address to PCI UART
308 PciLibAddress
= PCI_LIB_ADDRESS (BusNumber
, DeviceInfo
->Device
, DeviceInfo
->Function
, 0);
311 // Find the first IO or MMIO BAR
313 RegisterBaseMask
= 0xFFFFFFF0;
314 for (BarIndex
= 0; BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
315 SerialRegisterBase
= PciRead32 (PciLibAddress
+ PCI_BASE_ADDRESSREG_OFFSET
+ BarIndex
* 4);
316 if (PcdGetBool (PcdSerialUseMmio
) && ((SerialRegisterBase
& BIT0
) == 0)) {
320 RegisterBaseMask
= 0xFFFFFFF0;
324 if ((!PcdGetBool (PcdSerialUseMmio
)) && ((SerialRegisterBase
& BIT0
) != 0)) {
328 RegisterBaseMask
= 0xFFFFFFF8;
334 // MMIO or IO BAR is not found.
336 if (BarIndex
== PCI_MAX_BAR
) {
343 SerialRegisterBase
= SerialPortLibUpdatePciRegister32 (
344 PciLibAddress
+ PCI_BASE_ADDRESSREG_OFFSET
+ BarIndex
* 4,
345 (UINT32
)PcdGet64 (PcdSerialRegisterBase
),
350 // Verify that the UART BAR is in the address range decoded by the parent PCI Bridge
352 if (PcdGetBool (PcdSerialUseMmio
)) {
353 if (((SerialRegisterBase
>> 16) & 0xfff0) < ParentMemoryBase
|| ((SerialRegisterBase
>> 16) & 0xfff0) > ParentMemoryLimit
) {
357 if ((SerialRegisterBase
>> 12) < ParentIoBase
|| (SerialRegisterBase
>> 12) > ParentIoLimit
) {
363 // Enable I/O and MMIO in PCI UART Device if they are not already enabled
366 PciLibAddress
+ PCI_COMMAND_OFFSET
,
367 PcdGetBool (PcdSerialUseMmio
) ? EFI_PCI_COMMAND_MEMORY_SPACE
: EFI_PCI_COMMAND_IO_SPACE
371 // Force D0 state if a Power Management and Status Register is specified
373 if (DeviceInfo
->PowerManagementStatusAndControlRegister
!= 0x00) {
374 if ((PciRead16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
) & (BIT0
| BIT1
)) != 0x00) {
375 PciAnd16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
, (UINT16
)~(BIT0
| BIT1
));
377 // If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs
379 SerialPortWriteRegister (SerialRegisterBase
, R_UART_FCR
, (UINT8
)(PcdGet8 (PcdSerialFifoControl
) & (B_UART_FCR_FIFOE
| B_UART_FCR_FIFO64
)));
384 // Get PCI Device Info
386 DeviceInfo
= (PCI_UART_DEVICE_INFO
*) PcdGetPtr (PcdSerialPciDeviceInfo
);
389 // Enable I/O or MMIO in PCI Bridge
390 // Assume Root Bus Numer is Zero.
392 for (BusNumber
= 0; (DeviceInfo
+ 1)->Device
!= 0xff; DeviceInfo
++) {
394 // Compute PCI Lib Address to PCI to PCI Bridge
396 PciLibAddress
= PCI_LIB_ADDRESS (BusNumber
, DeviceInfo
->Device
, DeviceInfo
->Function
, 0);
399 // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge
402 PciLibAddress
+ PCI_COMMAND_OFFSET
,
403 PcdGetBool (PcdSerialUseMmio
) ? EFI_PCI_COMMAND_MEMORY_SPACE
: EFI_PCI_COMMAND_IO_SPACE
407 // Force D0 state if a Power Management and Status Register is specified
409 if (DeviceInfo
->PowerManagementStatusAndControlRegister
!= 0x00) {
410 if ((PciRead16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
) & (BIT0
| BIT1
)) != 0x00) {
411 PciAnd16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
, (UINT16
)~(BIT0
| BIT1
));
415 BusNumber
= PciRead8 (PciLibAddress
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
);
418 return SerialRegisterBase
;
422 Return whether the hardware flow control signal allows writing.
424 @param SerialRegisterBase The base address register of UART device.
426 @retval TRUE The serial port is writable.
427 @retval FALSE The serial port is not writable.
431 UINTN SerialRegisterBase
434 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
435 if (PcdGetBool (PcdSerialDetectCable
)) {
437 // Wait for both DSR and CTS to be set
438 // DSR is set if a cable is connected.
439 // CTS is set if it is ok to transmit data
441 // DSR CTS Description Action
442 // === === ======================================== ========
443 // 0 0 No cable connected. Wait
444 // 0 1 No cable connected. Wait
445 // 1 0 Cable connected, but not clear to send. Wait
446 // 1 1 Cable connected, and clear to send. Transmit
448 return (BOOLEAN
) ((SerialPortReadRegister (SerialRegisterBase
, R_UART_MSR
) & (B_UART_MSR_DSR
| B_UART_MSR_CTS
)) == (B_UART_MSR_DSR
| B_UART_MSR_CTS
));
451 // Wait for both DSR and CTS to be set OR for DSR to be clear.
452 // DSR is set if a cable is connected.
453 // CTS is set if it is ok to transmit data
455 // DSR CTS Description Action
456 // === === ======================================== ========
457 // 0 0 No cable connected. Transmit
458 // 0 1 No cable connected. Transmit
459 // 1 0 Cable connected, but not clear to send. Wait
460 // 1 1 Cable connected, and clar to send. Transmit
462 return (BOOLEAN
) ((SerialPortReadRegister (SerialRegisterBase
, R_UART_MSR
) & (B_UART_MSR_DSR
| B_UART_MSR_CTS
)) != (B_UART_MSR_DSR
));
470 Initialize the serial device hardware.
472 If no initialization is required, then return RETURN_SUCCESS.
473 If the serial device was successfully initialized, then return RETURN_SUCCESS.
474 If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
476 @retval RETURN_SUCCESS The serial device was initialized.
477 @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
482 SerialPortInitialize (
486 RETURN_STATUS Status
;
487 UINTN SerialRegisterBase
;
489 UINT32 CurrentDivisor
;
493 // Perform platform specific initialization required to enable use of the 16550 device
494 // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
496 Status
= PlatformHookSerialPortInitialize ();
497 if (RETURN_ERROR (Status
)) {
502 // Calculate divisor for baud generator
503 // Ref_Clk_Rate / Baud_Rate / 16
505 Divisor
= PcdGet32 (PcdSerialClockRate
) / (PcdGet32 (PcdSerialBaudRate
) * 16);
506 if ((PcdGet32 (PcdSerialClockRate
) % (PcdGet32 (PcdSerialBaudRate
) * 16)) >= PcdGet32 (PcdSerialBaudRate
) * 8) {
511 // Get the base address of the serial port in either I/O or MMIO space
513 SerialRegisterBase
= GetSerialRegisterBase ();
514 if (SerialRegisterBase
==0) {
515 return RETURN_DEVICE_ERROR
;
519 // See if the serial port is already initialized
522 if ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LCR
) & 0x3F) != (PcdGet8 (PcdSerialLineControl
) & 0x3F)) {
525 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_LCR
) | B_UART_LCR_DLAB
));
526 CurrentDivisor
= SerialPortReadRegister (SerialRegisterBase
, R_UART_BAUD_HIGH
) << 8;
527 CurrentDivisor
|= (UINT32
) SerialPortReadRegister (SerialRegisterBase
, R_UART_BAUD_LOW
);
528 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_LCR
) & ~B_UART_LCR_DLAB
));
529 if (CurrentDivisor
!= Divisor
) {
533 return RETURN_SUCCESS
;
537 // Wait for the serial port to be ready.
538 // Verify that both the transmit FIFO and the shift register are empty.
540 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) != (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
));
543 // Configure baud rate
545 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, B_UART_LCR_DLAB
);
546 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_HIGH
, (UINT8
) (Divisor
>> 8));
547 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_LOW
, (UINT8
) (Divisor
& 0xff));
550 // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
551 // Strip reserved bits from PcdSerialLineControl
553 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
)(PcdGet8 (PcdSerialLineControl
) & 0x3F));
556 // Enable and reset FIFOs
557 // Strip reserved bits from PcdSerialFifoControl
559 SerialPortWriteRegister (SerialRegisterBase
, R_UART_FCR
, 0x00);
560 SerialPortWriteRegister (SerialRegisterBase
, R_UART_FCR
, (UINT8
)(PcdGet8 (PcdSerialFifoControl
) & (B_UART_FCR_FIFOE
| B_UART_FCR_FIFO64
)));
563 // Set FIFO Polled Mode by clearing IER after setting FCR
565 SerialPortWriteRegister (SerialRegisterBase
, R_UART_IER
, 0x00);
568 // Put Modem Control Register(MCR) into its reset state of 0x00.
570 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, 0x00);
572 return RETURN_SUCCESS
;
576 Write data from buffer to serial device.
578 Writes NumberOfBytes data bytes from Buffer to the serial device.
579 The number of bytes actually written to the serial device is returned.
580 If the return value is less than NumberOfBytes, then the write operation failed.
582 If Buffer is NULL, then ASSERT().
584 If NumberOfBytes is zero, then return 0.
586 @param Buffer Pointer to the data buffer to be written.
587 @param NumberOfBytes Number of bytes to written to the serial device.
589 @retval 0 NumberOfBytes is 0.
590 @retval >0 The number of bytes written to the serial device.
591 If this value is less than NumberOfBytes, then the write operation failed.
598 IN UINTN NumberOfBytes
601 UINTN SerialRegisterBase
;
606 if (Buffer
== NULL
) {
610 SerialRegisterBase
= GetSerialRegisterBase ();
611 if (SerialRegisterBase
==0) {
615 if (NumberOfBytes
== 0) {
617 // Flush the hardware
621 // Wait for both the transmit FIFO and shift register empty.
623 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) != (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
));
626 // Wait for the hardware flow control signal
628 while (!SerialPortWritable (SerialRegisterBase
));
633 // Compute the maximum size of the Tx FIFO
636 if ((PcdGet8 (PcdSerialFifoControl
) & B_UART_FCR_FIFOE
) != 0) {
637 if ((PcdGet8 (PcdSerialFifoControl
) & B_UART_FCR_FIFO64
) == 0) {
640 FifoSize
= PcdGet32 (PcdSerialExtendedTxFifoSize
);
644 Result
= NumberOfBytes
;
645 while (NumberOfBytes
!= 0) {
647 // Wait for the serial port to be ready, to make sure both the transmit FIFO
648 // and shift register empty.
650 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) != (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
));
653 // Fill then entire Tx FIFO
655 for (Index
= 0; Index
< FifoSize
&& NumberOfBytes
!= 0; Index
++, NumberOfBytes
--, Buffer
++) {
657 // Wait for the hardware flow control signal
659 while (!SerialPortWritable (SerialRegisterBase
));
662 // Write byte to the transmit buffer.
664 SerialPortWriteRegister (SerialRegisterBase
, R_UART_TXBUF
, *Buffer
);
671 Reads data from a serial device into a buffer.
673 @param Buffer Pointer to the data buffer to store the data read from the serial device.
674 @param NumberOfBytes Number of bytes to read from the serial device.
676 @retval 0 NumberOfBytes is 0.
677 @retval >0 The number of bytes read from the serial device.
678 If this value is less than NumberOfBytes, then the read operation failed.
685 IN UINTN NumberOfBytes
688 UINTN SerialRegisterBase
;
692 if (NULL
== Buffer
) {
696 SerialRegisterBase
= GetSerialRegisterBase ();
697 if (SerialRegisterBase
==0) {
701 Mcr
= (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
) & ~B_UART_MCR_RTS
);
703 for (Result
= 0; NumberOfBytes
-- != 0; Result
++, Buffer
++) {
705 // Wait for the serial port to have some data.
707 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & B_UART_LSR_RXRDY
) == 0) {
708 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
710 // Set RTS to let the peer send some data
712 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, (UINT8
)(Mcr
| B_UART_MCR_RTS
));
715 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
717 // Clear RTS to prevent peer from sending data
719 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, Mcr
);
723 // Read byte from the receive buffer.
725 *Buffer
= SerialPortReadRegister (SerialRegisterBase
, R_UART_RXBUF
);
733 Polls a serial device to see if there is any data waiting to be read.
735 Polls aserial device to see if there is any data waiting to be read.
736 If there is data waiting to be read from the serial device, then TRUE is returned.
737 If there is no data waiting to be read from the serial device, then FALSE is returned.
739 @retval TRUE Data is waiting to be read from the serial device.
740 @retval FALSE There is no data waiting to be read from the serial device.
749 UINTN SerialRegisterBase
;
751 SerialRegisterBase
= GetSerialRegisterBase ();
752 if (SerialRegisterBase
==0) {
757 // Read the serial port status
759 if ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & B_UART_LSR_RXRDY
) != 0) {
760 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
762 // Clear RTS to prevent peer from sending data
764 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
) & ~B_UART_MCR_RTS
));
769 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
771 // Set RTS to let the peer send some data
773 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
) | B_UART_MCR_RTS
));
780 Sets the control bits on a serial device.
782 @param Control Sets the bits of Control that are settable.
784 @retval RETURN_SUCCESS The new control bits were set on the serial device.
785 @retval RETURN_UNSUPPORTED The serial device does not support this operation.
786 @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
791 SerialPortSetControl (
795 UINTN SerialRegisterBase
;
799 // First determine the parameter is invalid.
801 if ((Control
& (~(EFI_SERIAL_REQUEST_TO_SEND
| EFI_SERIAL_DATA_TERMINAL_READY
|
802 EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE
))) != 0) {
803 return RETURN_UNSUPPORTED
;
806 SerialRegisterBase
= GetSerialRegisterBase ();
807 if (SerialRegisterBase
==0) {
808 return RETURN_UNSUPPORTED
;
812 // Read the Modem Control Register.
814 Mcr
= SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
);
815 Mcr
&= (~(B_UART_MCR_DTRC
| B_UART_MCR_RTS
));
817 if ((Control
& EFI_SERIAL_DATA_TERMINAL_READY
) == EFI_SERIAL_DATA_TERMINAL_READY
) {
818 Mcr
|= B_UART_MCR_DTRC
;
821 if ((Control
& EFI_SERIAL_REQUEST_TO_SEND
) == EFI_SERIAL_REQUEST_TO_SEND
) {
822 Mcr
|= B_UART_MCR_RTS
;
826 // Write the Modem Control Register.
828 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, Mcr
);
830 return RETURN_SUCCESS
;
834 Retrieve the status of the control bits on a serial device.
836 @param Control A pointer to return the current control signals from the serial device.
838 @retval RETURN_SUCCESS The control bits were read from the serial device.
839 @retval RETURN_UNSUPPORTED The serial device does not support this operation.
840 @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
845 SerialPortGetControl (
849 UINTN SerialRegisterBase
;
854 SerialRegisterBase
= GetSerialRegisterBase ();
855 if (SerialRegisterBase
==0) {
856 return RETURN_UNSUPPORTED
;
862 // Read the Modem Status Register.
864 Msr
= SerialPortReadRegister (SerialRegisterBase
, R_UART_MSR
);
866 if ((Msr
& B_UART_MSR_CTS
) == B_UART_MSR_CTS
) {
867 *Control
|= EFI_SERIAL_CLEAR_TO_SEND
;
870 if ((Msr
& B_UART_MSR_DSR
) == B_UART_MSR_DSR
) {
871 *Control
|= EFI_SERIAL_DATA_SET_READY
;
874 if ((Msr
& B_UART_MSR_RI
) == B_UART_MSR_RI
) {
875 *Control
|= EFI_SERIAL_RING_INDICATE
;
878 if ((Msr
& B_UART_MSR_DCD
) == B_UART_MSR_DCD
) {
879 *Control
|= EFI_SERIAL_CARRIER_DETECT
;
883 // Read the Modem Control Register.
885 Mcr
= SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
);
887 if ((Mcr
& B_UART_MCR_DTRC
) == B_UART_MCR_DTRC
) {
888 *Control
|= EFI_SERIAL_DATA_TERMINAL_READY
;
891 if ((Mcr
& B_UART_MCR_RTS
) == B_UART_MCR_RTS
) {
892 *Control
|= EFI_SERIAL_REQUEST_TO_SEND
;
895 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
896 *Control
|= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE
;
900 // Read the Line Status Register.
902 Lsr
= SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
);
904 if ((Lsr
& (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) == (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) {
905 *Control
|= EFI_SERIAL_OUTPUT_BUFFER_EMPTY
;
908 if ((Lsr
& B_UART_LSR_RXRDY
) == 0) {
909 *Control
|= EFI_SERIAL_INPUT_BUFFER_EMPTY
;
912 return RETURN_SUCCESS
;
916 Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
917 data bits, and stop bits on a serial device.
919 @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
920 device's default interface speed.
921 On output, the value actually set.
922 @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
923 serial interface. A ReceiveFifoDepth value of 0 will use
924 the device's default FIFO depth.
925 On output, the value actually set.
926 @param Timeout The requested time out for a single character in microseconds.
927 This timeout applies to both the transmit and receive side of the
928 interface. A Timeout value of 0 will use the device's default time
930 On output, the value actually set.
931 @param Parity The type of parity to use on this serial device. A Parity value of
932 DefaultParity will use the device's default parity value.
933 On output, the value actually set.
934 @param DataBits The number of data bits to use on the serial device. A DataBits
935 vaule of 0 will use the device's default data bit setting.
936 On output, the value actually set.
937 @param StopBits The number of stop bits to use on this serial device. A StopBits
938 value of DefaultStopBits will use the device's default number of
940 On output, the value actually set.
942 @retval RETURN_SUCCESS The new attributes were set on the serial device.
943 @retval RETURN_UNSUPPORTED The serial device does not support this operation.
944 @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
945 @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
950 SerialPortSetAttributes (
951 IN OUT UINT64
*BaudRate
,
952 IN OUT UINT32
*ReceiveFifoDepth
,
953 IN OUT UINT32
*Timeout
,
954 IN OUT EFI_PARITY_TYPE
*Parity
,
955 IN OUT UINT8
*DataBits
,
956 IN OUT EFI_STOP_BITS_TYPE
*StopBits
959 UINTN SerialRegisterBase
;
960 UINT32 SerialBaudRate
;
967 SerialRegisterBase
= GetSerialRegisterBase ();
968 if (SerialRegisterBase
==0) {
969 return RETURN_UNSUPPORTED
;
973 // Check for default settings and fill in actual values.
975 if (*BaudRate
== 0) {
976 *BaudRate
= PcdGet32 (PcdSerialBaudRate
);
978 SerialBaudRate
= (UINT32
) *BaudRate
;
980 if (*DataBits
== 0) {
981 LcrData
= (UINT8
) (PcdGet8 (PcdSerialLineControl
) & 0x3);
982 *DataBits
= LcrData
+ 5;
984 if ((*DataBits
< 5) || (*DataBits
> 8)) {
985 return RETURN_INVALID_PARAMETER
;
990 LcrData
= (UINT8
) (*DataBits
- (UINT8
) 5);
993 if (*Parity
== DefaultParity
) {
994 LcrParity
= (UINT8
) ((PcdGet8 (PcdSerialLineControl
) >> 3) & 0x7);
1001 *Parity
= EvenParity
;
1005 *Parity
= OddParity
;
1009 *Parity
= SpaceParity
;
1013 *Parity
= MarkParity
;
1042 return RETURN_INVALID_PARAMETER
;
1046 if (*StopBits
== DefaultStopBits
) {
1047 LcrStop
= (UINT8
) ((PcdGet8 (PcdSerialLineControl
) >> 2) & 0x1);
1050 *StopBits
= OneStopBit
;
1054 if (*DataBits
== 5) {
1055 *StopBits
= OneFiveStopBits
;
1057 *StopBits
= TwoStopBits
;
1065 switch (*StopBits
) {
1070 case OneFiveStopBits
:
1076 return RETURN_INVALID_PARAMETER
;
1081 // Calculate divisor for baud generator
1082 // Ref_Clk_Rate / Baud_Rate / 16
1084 Divisor
= PcdGet32 (PcdSerialClockRate
) / (SerialBaudRate
* 16);
1085 if ((PcdGet32 (PcdSerialClockRate
) % (SerialBaudRate
* 16)) >= SerialBaudRate
* 8) {
1090 // Configure baud rate
1092 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, B_UART_LCR_DLAB
);
1093 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_HIGH
, (UINT8
) (Divisor
>> 8));
1094 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_LOW
, (UINT8
) (Divisor
& 0xff));
1097 // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
1098 // Strip reserved bits from line control value
1100 Lcr
= (UINT8
) ((LcrParity
<< 3) | (LcrStop
<< 2) | LcrData
);
1101 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
) (Lcr
& 0x3F));
1103 return RETURN_SUCCESS
;
1106 /** Base Serial Port 16550 Library Constructor
1108 @retval RETURN_SUCCESS Success.
1112 BaseSerialPortLib16550 (
1116 // Nothing to do here. This constructor is added to
1117 // enable the chain of constructor invocation for
1118 // dependent libraries.
1119 return RETURN_SUCCESS
;