MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c

   1 /** @file
   2   Set a IDT entry for debug purpose
   3
   4   Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
   5
   6 Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
   7
   8 This program and the accompanying materials
   9 are licensed and made available under the terms and conditions of the BSD License
  10 which accompanies this distribution.  The full text of the license may be found at
  11 http://opensource.org/licenses/bsd-license.php
  12
  13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 **/
  17 #include "ScriptExecute.h"
  18
  19 #define IA32_PG_P                   BIT0
  20 #define IA32_PG_RW                  BIT1
  21 #define IA32_PG_PS                  BIT7
  22
  23 UINT64                             mPhyMask;
  24 BOOLEAN                            mPage1GSupport;
  25 VOID                               *mOriginalHandler;
  26 UINTN                              mS3NvsPageTableAddress;
  27
  28 /**
  29   Page fault handler.
  30
  31 **/
  32 VOID
  33 EFIAPI
  34 PageFaultHandlerHook (
  35   VOID
  36   );
  37
  38 /**
  39   Hook IDT with our page fault handler so that the on-demand paging works on page fault.
  40
  41   @param  IdtEntry  a pointer to IDT entry
  42
  43 **/
  44 VOID
  45 HookPageFaultHandler (
  46   IN IA32_IDT_GATE_DESCRIPTOR                   *IdtEntry
  47   )
  48 {
  49   UINT32         RegEax;
  50   UINT32         RegEdx;
  51   UINTN          PageFaultHandlerHookAddress;
  52
  53   AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
  54   mPhyMask = LShiftU64 (1, (UINT8)RegEax) - 1;
  55   mPhyMask &= (1ull << 48) - SIZE_4KB;
  56
  57   mPage1GSupport = FALSE;
  58   if (PcdGetBool(PcdUse1GPageTable)) {
  59     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
  60     if (RegEax >= 0x80000001) {
  61       AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
  62       if ((RegEdx & BIT26) != 0) {
  63         mPage1GSupport = TRUE;
  64       }
  65     }
  66   }
  67
  68   //
  69   // Set Page Fault entry to catch >4G access
  70   //
  71   PageFaultHandlerHookAddress = (UINTN)PageFaultHandlerHook;
  72   mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));
  73   IdtEntry->Bits.OffsetLow      = (UINT16)PageFaultHandlerHookAddress;
  74   IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();
  75   IdtEntry->Bits.Reserved_0     = 0;
  76   IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;
  77   IdtEntry->Bits.OffsetHigh     = (UINT16)(PageFaultHandlerHookAddress >> 16);
  78   IdtEntry->Bits.OffsetUpper    = (UINT32)(PageFaultHandlerHookAddress >> 32);
  79   IdtEntry->Bits.Reserved_1     = 0;
  80
  81   if (mPage1GSupport) {
  82     mS3NvsPageTableAddress = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);
  83   }else {
  84     mS3NvsPageTableAddress = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);
  85   }
  86 }
  87
  88 /**
  89   Set a IDT entry for interrupt vector 3 for debug purpose.
  90
  91   @param  AcpiS3Context  a pointer to a structure of ACPI_S3_CONTEXT
  92
  93 **/
  94 VOID
  95 SetIdtEntry (
  96   IN ACPI_S3_CONTEXT     *AcpiS3Context
  97   )
  98 {
  99   IA32_IDT_GATE_DESCRIPTOR                      *IdtEntry;
 100   IA32_DESCRIPTOR                               *IdtDescriptor;
 101   UINTN                                         S3DebugBuffer;
 102
 103   //
 104   // Restore IDT for debug
 105   //
 106   IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);
 107   AsmWriteIdtr (IdtDescriptor);
 108
 109   //
 110   // Setup the default CPU exception handlers
 111   //
 112   SetupCpuExceptionHandlers ();
 113
 114   DEBUG_CODE (
 115     //
 116     // Update IDT entry INT3 if the instruction is valid in it
 117     //
 118     S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);
 119     if (*(UINTN *)S3DebugBuffer != (UINTN) -1) {
 120       IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));
 121       IdtEntry->Bits.OffsetLow      = (UINT16)S3DebugBuffer;
 122       IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();
 123       IdtEntry->Bits.Reserved_0     = 0;
 124       IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;
 125       IdtEntry->Bits.OffsetHigh     = (UINT16)(S3DebugBuffer >> 16);
 126       IdtEntry->Bits.OffsetUpper    = (UINT32)(S3DebugBuffer >> 32);
 127       IdtEntry->Bits.Reserved_1     = 0;
 128     }
 129   );
 130
 131   IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));
 132   HookPageFaultHandler (IdtEntry);
 133 }
 134
 135 /**
 136   Get new page address.
 137
 138   @param  PageNum  new page number needed
 139
 140   @return new page address
 141 **/
 142 UINTN
 143 GetNewPage (
 144   IN UINTN  PageNum
 145   )
 146 {
 147   UINTN  NewPage;
 148   NewPage = mS3NvsPageTableAddress;
 149   ZeroMem ((VOID *)NewPage, EFI_PAGES_TO_SIZE(PageNum));
 150   mS3NvsPageTableAddress += EFI_PAGES_TO_SIZE(PageNum);
 151   return NewPage;
 152 }
 153
 154 /**
 155   The page fault handler that on-demand read >4G memory/MMIO.
 156
 157   @retval TRUE     The page fault is correctly handled.
 158   @retval FALSE    The page fault is not handled and is passed through to original handler.
 159
 160 **/
 161 BOOLEAN
 162 EFIAPI
 163 PageFaultHandler (
 164   VOID
 165   )
 166 {
 167   UINT64         *PageTable;
 168   UINT64         PFAddress;
 169   UINTN          PTIndex;
 170
 171   PFAddress = AsmReadCr2 ();
 172   DEBUG ((EFI_D_ERROR, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));
 173
 174   if (PFAddress >= mPhyMask + SIZE_4KB) {
 175     return FALSE;
 176   }
 177   PFAddress &= mPhyMask;
 178
 179   PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);
 180
 181   PTIndex = BitFieldRead64 (PFAddress, 39, 47);
 182   // PML4E
 183   if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
 184     PageTable[PTIndex] = GetNewPage (1) | IA32_PG_P | IA32_PG_RW;
 185   }
 186   PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
 187   PTIndex = BitFieldRead64 (PFAddress, 30, 38);
 188   // PDPTE
 189   if (mPage1GSupport) {
 190     PageTable[PTIndex] = PFAddress | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
 191   } else {
 192     if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
 193       PageTable[PTIndex] = GetNewPage (1) | IA32_PG_P | IA32_PG_RW;
 194     }
 195     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
 196     PTIndex = BitFieldRead64 (PFAddress, 21, 29);
 197     // PD
 198     PageTable[PTIndex] = PFAddress | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
 199   }
 200
 201   return TRUE;
 202 }