MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c

   1 /** @file
   2   Set a IDT entry for debug purpose
   3
   4   Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
   5
   6 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
   7
   8 This program and the accompanying materials
   9 are licensed and made available under the terms and conditions of the BSD License
  10 which accompanies this distribution.  The full text of the license may be found at
  11 http://opensource.org/licenses/bsd-license.php
  12
  13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 **/
  17 #include "ScriptExecute.h"
  18 //
  19 // INTERRUPT_GATE_DESCRIPTOR and SetIdtEntry () are used to setup IDT to do debug
  20 //
  21
  22 #pragma pack(1)
  23
  24 typedef struct {
  25   UINT16    Offset15To0;
  26   UINT16    SegmentSelector;
  27   UINT16    Attributes;
  28   UINT16    Offset31To16;
  29   UINT32    Offset63To32;
  30   UINT32    Reserved;
  31 } INTERRUPT_GATE_DESCRIPTOR;
  32
  33 #define INTERRUPT_GATE_ATTRIBUTE   0x8e00
  34
  35 #pragma pack()
  36
  37 #define IA32_PG_P                   BIT0
  38 #define IA32_PG_RW                  BIT1
  39 #define IA32_PG_PS                  BIT7
  40
  41 UINT64                             mPhyMask;
  42 BOOLEAN                            mPage1GSupport;
  43 VOID                               *mOriginalHandler;
  44 UINTN                              mS3NvsPageTableAddress;
  45
  46 /**
  47   Page fault handler.
  48
  49 **/
  50 VOID
  51 EFIAPI
  52 PageFaultHandlerHook (
  53   VOID
  54   );
  55
  56 /**
  57   Hook IDT with our page fault handler so that the on-demand paging works on page fault.
  58
  59   @param  IdtEntry  a pointer to IDT entry
  60
  61 **/
  62 VOID
  63 HookPageFaultHandler (
  64   IN INTERRUPT_GATE_DESCRIPTOR                     *IdtEntry
  65   )
  66 {
  67   UINT32         RegEax;
  68   UINT32         RegEdx;
  69
  70   AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
  71   mPhyMask = LShiftU64 (1, (UINT8)RegEax) - 1;
  72   mPhyMask &= (1ull << 48) - SIZE_4KB;
  73
  74   mPage1GSupport = FALSE;
  75   if (PcdGetBool(PcdUse1GPageTable)) {
  76     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
  77     if (RegEax >= 0x80000001) {
  78       AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
  79       if ((RegEdx & BIT26) != 0) {
  80         mPage1GSupport = TRUE;
  81       }
  82     }
  83   }
  84
  85   //
  86   // Set Page Fault entry to catch >4G access
  87   //
  88   mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Offset63To32, 32) + IdtEntry->Offset15To0 + (IdtEntry->Offset31To16 << 16));
  89   IdtEntry->Offset15To0     = (UINT16)((UINTN)PageFaultHandlerHook);
  90   IdtEntry->SegmentSelector = (UINT16)AsmReadCs ();
  91   IdtEntry->Attributes      = (UINT16)INTERRUPT_GATE_ATTRIBUTE;
  92   IdtEntry->Offset31To16    = (UINT16)((UINTN)PageFaultHandlerHook >> 16);
  93   IdtEntry->Offset63To32    = (UINT32)((UINTN)PageFaultHandlerHook >> 32);
  94   IdtEntry->Reserved        = 0;
  95
  96   if (mPage1GSupport) {
  97     mS3NvsPageTableAddress = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);
  98   }else {
  99     mS3NvsPageTableAddress = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);
 100   }
 101 }
 102
 103 /**
 104   Set a IDT entry for interrupt vector 3 for debug purpose.
 105
 106   @param  AcpiS3Context  a pointer to a structure of ACPI_S3_CONTEXT
 107
 108 **/
 109 VOID
 110 SetIdtEntry (
 111   IN ACPI_S3_CONTEXT     *AcpiS3Context
 112   )
 113 {
 114   INTERRUPT_GATE_DESCRIPTOR                     *IdtEntry;
 115   IA32_DESCRIPTOR                               *IdtDescriptor;
 116   UINTN                                         S3DebugBuffer;
 117
 118   //
 119   // Restore IDT for debug
 120   //
 121   IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);
 122   AsmWriteIdtr (IdtDescriptor);
 123
 124   //
 125   // Setup the default CPU exception handlers
 126   //
 127   SetupCpuExceptionHandlers ();
 128
 129   DEBUG_CODE (
 130     //
 131     // Update IDT entry INT3 if the instruction is valid in it
 132     //
 133     S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);
 134     if (*(UINTN *)S3DebugBuffer != (UINTN) -1) {
 135       IdtEntry = (INTERRUPT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (INTERRUPT_GATE_DESCRIPTOR)));
 136       IdtEntry->Offset15To0     = (UINT16)S3DebugBuffer;
 137       IdtEntry->SegmentSelector = (UINT16)AsmReadCs ();
 138       IdtEntry->Attributes      = (UINT16)INTERRUPT_GATE_ATTRIBUTE;
 139       IdtEntry->Offset31To16    = (UINT16)(S3DebugBuffer >> 16);
 140       IdtEntry->Offset63To32    = (UINT32)(S3DebugBuffer >> 32);
 141       IdtEntry->Reserved        = 0;
 142     }
 143   );
 144
 145   IdtEntry = (INTERRUPT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (14 * sizeof (INTERRUPT_GATE_DESCRIPTOR)));
 146   HookPageFaultHandler (IdtEntry);
 147 }
 148
 149 /**
 150   Get new page address.
 151
 152   @param  PageNum  new page number needed
 153
 154   @return new page address
 155 **/
 156 UINTN
 157 GetNewPage (
 158   IN UINTN  PageNum
 159   )
 160 {
 161   UINTN  NewPage;
 162   NewPage = mS3NvsPageTableAddress;
 163   ZeroMem ((VOID *)NewPage, EFI_PAGES_TO_SIZE(PageNum));
 164   mS3NvsPageTableAddress += EFI_PAGES_TO_SIZE(PageNum);
 165   return NewPage;
 166 }
 167
 168 /**
 169   The page fault handler that on-demand read >4G memory/MMIO.
 170
 171   @retval TRUE     The page fault is correctly handled.
 172   @retval FALSE    The page fault is not handled and is passed through to original handler.
 173
 174 **/
 175 BOOLEAN
 176 EFIAPI
 177 PageFaultHandler (
 178   VOID
 179   )
 180 {
 181   UINT64         *PageTable;
 182   UINT64         PFAddress;
 183   UINTN          PTIndex;
 184
 185   PFAddress = AsmReadCr2 ();
 186   DEBUG ((EFI_D_ERROR, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));
 187
 188   if (PFAddress >= mPhyMask + SIZE_4KB) {
 189     return FALSE;
 190   }
 191   PFAddress &= mPhyMask;
 192
 193   PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);
 194
 195   PTIndex = BitFieldRead64 (PFAddress, 39, 47);
 196   // PML4E
 197   if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
 198     PageTable[PTIndex] = GetNewPage (1) | IA32_PG_P | IA32_PG_RW;
 199   }
 200   PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
 201   PTIndex = BitFieldRead64 (PFAddress, 30, 38);
 202   // PDPTE
 203   if (mPage1GSupport) {
 204     PageTable[PTIndex] = PFAddress | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
 205   } else {
 206     if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
 207       PageTable[PTIndex] = GetNewPage (1) | IA32_PG_P | IA32_PG_RW;
 208     }
 209     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
 210     PTIndex = BitFieldRead64 (PFAddress, 21, 29);
 211     // PD
 212     PageTable[PTIndex] = PFAddress | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
 213   }
 214
 215   return TRUE;
 216 }